Departement Elektriese, Elektroniese Department of Electrical, Electronic

en Rekenaaringenieurswese and Computer Engineering

Semestertoets 2 Semester test 2

Kopiereg voorbehou Copyright reserved
Analoog Elektronika - ENE 310 Analogue Electronics - ENE 310
16 Mei 2019 16 May 2019
HANDIG HIERDIE BLADSY IN VIR ASSESSERING / SUBMIT THIS SHEET FOR ASSESSMENT
Student se besonderhede / Student details
Van: Naam: Studentenommer:
Surname: Name: Student number:
Tel. nr. gedurende Tel. nr. na eksamen: Groep: Afr
eksamen: Tel. no. after examination: Group: Eng
Tel. no. during
examination:
Ek het die belangrike inligting en die instruksies vir elektroniese inhandiging
(beskikbaar op die bediener) gelees, en ek verstaan dit:
I have read the important information and the instructions for electronic
submission (available on the server), and I understand it: Signature / Handtekening

Toetsinligting:
Test information:
Maksimum punte: 59 Volpunte: 55
Maximum marks: Full marks:
Duur van vraestel: 90 minute (beide dele) Toeboek (PDFs voorsien): Gedeeltelik Oop
Duration of paper: 90 minutes (both sections) Closed book (PDFs provided): Partially Open
Totale aantal bladsye (hierdie blad ingesluit): Punt:
Total number of pages (including this page): 6 Mark:
BELANGRIK- IMPORTANT
1. Die toets & eksaminerings regulasies van die Universiteit van Pretoria is van toepassing.
The test & examination regulations of the University of Pretoria apply.

2. Vrae moet in onuitveebare ink geskryf word. Antwoorde in potlood sal nie gemerk word nie!
Questions must be answered in indelible ink. Answers in pencil will not be marked!

3. Antwoord al die vrae in die voorsiende invulvraestel EN die elektroniese XLS dokument.
Answer all the questions in the supplied fill in question paper AND in the electronic XLS document.

4. Dui alle bewerkings waar van toepassing aan in die voorsiende rofweg antwoordboeke. Sou handevaluasie van toepassing wees, sal geen punte gegee
word vir korrekte antwoorde wat nie gestaaf word met bewerkings/denkwyse nie.
Show all calculations where applicable in the provided answer books. Should manual evaluation apply, no marks will be given for correct answers without
calculations/reasoning to support them.

5. Gebruik duidelike en geregverdigde ingenieursbenaderings (en/of aannames) waar van toepassing. Alle aannames moet gestaaf word.
Use clearly justified & educated engineering approximations (and/or stated assumptions) where/as appropriate. All assumptions must be justified.

6. Die elektroniese evaluasie regulasies van die Departement Elektries, Elektronies en Rekenaaringenieurswese is van toepassing.
The electronic evaluation regulations of the Department of Electrical, Electronic and Computer Engineering apply.
Dosent(e): 1. Dr Johan Schoeman
Lecturer(s): 2. Dr Trudi H Joubert
 Vraag 1 - Toepassing van teorie [21] Question 1 - Application of theory

1) Multiple choice questions

For the questions below, select the most appropriate answer(s). More than one option can be correct. This is entered as a
comma separated list, for example: a, d, e. Note that incorrect answers will be negatively marked, so make absolutely sure that
only correct options are entered.

Veelvuldige keuse vrae

Vir die vrae hieronder, kies die mees geskikte antwoord(e). Meer as een keuse kan reg wees. Hierdie word ingevoer as ‘n lys
met kommas, bv.: a, d, e. Let daarop dat verkeerde antwoorde negatief gemerk word. Maak dus absoluut seker dat slegs
korrekte antwoorde ingevoer word.

1.1) Beskikbare keuses vir filter argitekture [3] 1.1) Options available for filter architectures

A: KRC filter
B: Multiple feedback filter
C: State variable filter
D: Biquad filter
E: None of the above
F: All of the above

1.1.1) Hierdie filters is geskik vir Q-waardes kleiner as 10. 1.1.1) These filters are well suited for Q values less than
10.

1.1.2) Hierdie filters is geskik vir Q-waardes groter as 10. 1.1.2) These filters are well suited for Q values more than
10.

1.1.3) Hierdie filters is maklik om in te stem. 1.1.3) These filters are easy to tune.

1.2) Beskikbare keuses vir OV beperkings [10] 1.2) Options available for OA limitations

A: Input bias currents

B: Input offset currents
C: Input offset voltage
D: CMRR
E: PSRR
F: Maximum ratings
G: GBP
H: Input impedance
I: Output impedance
J: Settling time
K: Slew rate

1.2.1) Hierdie beperkings bestaan weens OV transistor 1.2.1) These limitations exist due to OA transistor
voorspanning. biasing.

1.2.2) Hierdie beperkings is ‘n funksie van veranderinge 1.2.2) These limitations are a function of changes in
in die voorspannigspunt biasing.

1.2.3) Hierdie kleinsein beperkings beinvloed die uitset 1.2.3) These small signal limitations influence the output
frekwensierespons. frequency response.

1.2.4) Hierdie beperkings kan verbeter word met eksterne 1.2.4) These limitations can be improved with external
komponente. components.

1.2.5) Hierdie beperkings kan verbeter word deur ‘n OV 1.2.5) These limitations can be improved by selecting an
te kies wat gebruik maak van veldeffek transistors eerder OA using field effect transistors rather than bipolar
as bipolêre transistors. transistors.

ENE310 Semester Test 2 2

Copyright © 2019, Johan Schoeman, University of Pretoria
1.3) List 4 advantages (excluding low output impedance) of instrumentation amplifiers over difference amplifiers.
Noem 4 voordele (lae uitset impedansie uitgesluit) van instrumentasie versterkers bo verskilversterkers. [4]

1.4) List 4 advantages of voltage to frequency converters over voltage controlled oscillators.
Noem 4 voordele van spanning na frekwensie omskakelaars bo spanningsbeheerde ossillators. [4]

Voltooi vir Vraag 1 / Complete for Question 1:

Studente vul in / Students fill in: Evalueerder voltooi / Evaluator completes:

Vraag / Evaluasie / Finale punt /

Question Omkring korrekte opsie / Circle correct option Evaluation Final mark
√ of / or X
1.1.1 A B C D E F G H I J K /3
1.1.2 A B C D E F G H I J K
1.1.3 A B C D E F G H I J K
1.2.1 A B C D E F G H I J K / 10
1.2.2 A B C D E F G H I J K
1.2.3 A B C D E F G H I J K
1.2.4 A B C D E F G H I J K
1.2.5 A B C D E F G H I J K

Vraag / Summary (i.e. very brief description) of advantages / Opsomming Evaluasie / Finale punt /
Question (m.a.w. beskryf baie kortliks) van die voordele Evaluation Final mark
√ of / or X
1.3.1 /4
1.3.2
1.3.3
1.3.4

Vraag / Summary (i.e. very brief description) of advantages / Opsomming Evaluasie / Finale punt /
Question (m.a.w. beskryf baie kortliks) van die voordele Evaluation Final mark
√ of / or X
1.4.1 /4
1.4.2
1.4.3
1.4.4

ENE310 Semester Test 2 3

Copyright © 2019, Johan Schoeman, University of Pretoria
 Vraag 2 – Filter ontwerp
Oorweeg die spektrum hieronder. Jy besluit om ‘n
toestandsveranderlike filter te implimenteer om die mono
klanksein (L+R) en die draer te verwyder met ‘n enkele
filter topologie.
[17] Question 2 – Filter design
Consider the spectrum below. You decide to implement a
state-variable filter to remove the mono audio signal
(L+R) and the carrier with a single filter topology.

2.1.1) Watter sein sal die draer uitset wees? [1] 2.1.1) Which signal will provide the carrier output?
2.1.2) Watter sein sal die mono klanksein voorsien? [1] 2.1.2) Which signal will provide the mono audio?

2.2) Ontwerp die filter om aan die volgende spesifikasies [15] 2.2) Design the filter to meet the following requirements:
te voldoen:

• a low-pass gain magnitude of 10 V/V

• a high-pass gain magnitude of 1 V/V
• a band-pass gain magnitude of 10 V/V
• a quality factor of 10
• a cut-off frequency derived from the problem statement
• component values within a practically feasible range and with the closest standard resistor and capacitor values
provided / komponentwaardes binne ‘n prakties haalbare bereik en met die naaste standaard weerstand- en
kapasitorwaardes voorsien.

Source: Wikipedia (https://en.wikipedia.org/wiki/FM_broadcasting)

Voltooi vir 2 / Complete for 2:

Studente vul in / Students fill in: Evalueerder voltooi / Evaluator completes:

Waarde / Value Evaluasie / Evaluation Punt /
Mark
2.1.1 Carrier output 2.1.1 Signal name 1
2.1.2 Mono audio output 2.1.2 Signal name 1

ENE310 Semester Test 2 4

Copyright © 2019, Johan Schoeman, University of Pretoria
2.2
C1 nF 2.2 Aspects of design
C2 nF 2.2a Achieve gain (LPF) 2
R1 kΩ 2.2b Achieve gain (HPF) 2
R2 kΩ 2.2c Achieve gain (BPF) 2
R3 kΩ 2.2d Achieve frequency 3
R4 kΩ 2.2d Achieve Q 3
R5 kΩ 2.2.e Component selection 3
R6 kΩ
R7 kΩ TOTAL: 17

Vraag 3 – Schmitt sneller [9] Question 3 – Schmitt trigger

3.1) Voorsien die SOK van ‘n enkel spanningstoevoer
omkeer SOK afset Schmitt sneller met ‘n toevoer spanning
VCC = 5 V, VOL = 0 V, VOH = 5 V, VTL = 1.25 V en VTH =
3.25 V. Dui duidelik alle relevante spannings op die grafiek
aan, sowel as die rigting van verandering in die SOK in die
vertikale oorgange. Gebruik Blok 01 in die voorsiende EPS
antwoordblad. Teken beide grafieke in die enkele blok.
Hierdie vraag sal met die hand gemerk word.
[4] 3.1) Provide the VTC of a single supply inverting VTC
offset Schmitt trigger with a supply voltage V CC = 5 V,
VOL = 0 V, VOH = 5 V, VTL = 1.25 V and VTH = 3.25 V.
Clearly indicate all the relevant voltages on the graph,
as well as the direction of travel of the VTC in the
vertical transitions. Use Block 01 in the supplied EPS
answer sheets. Draw both graphs in the single block.
This will be manually evaluated.

3.2) Ontwerp ‘n stroombaan en voorsien geskikte [5] 3.2) Design a circuit and provide suitable resistor values
weerstandswaardes om die boonste spesifikasies te behaal. to achieve the above specifications.

Voltooi vir 3 / Complete for 3:

Studente vul in / Students fill in: Evalueerder voltooi / Evaluator completes:

3.1 Nothing here. Complete the green EPS form. Evaluasie / Evaluation Punt / Mark
3.1a Voltage labels 2
3.1b Transitions 1
3.1c Offset(s) 1

3.2 Approach and calculations to meet:

R1 kΩ 3.2a VTL requirements 2
R2 kΩ 3.2b VTH requirements 2
R3 kΩ 3.2c Component selection 1
R4 kΩ TOTAL: 9

ENE310 Semester Test 2 5

Copyright © 2019, Johan Schoeman, University of Pretoria
 Vraag 4 - Ossillator stroombane
4.1) Ontwerp ‘n Hartley LC ossillator met ‘n omkeer OV
stroombaan. Die stroombaan moet ossilleer by f 0 = 40 kHz.
Jy het slegs een induktor van 1000 nH (L 1) beskikbaar.
Vind die komponentwaardes van die tweede induktor (L2),
die kapasitor (C3) en alle weerstande om die ontwerps-
kriteria te behaal. ‘n Winsverhouding van -20 V/V word
benodig.
[12] Question 4 - Oscillator circuits
[5] 4.1) Design a Hartley LC oscillator with an inverting
OA circuit. The circuit should oscillate at f 0 = 40 kHz.
You only have one inductor of 1000 nH (L 1) available.
Find the component values of the second inductor (L2),
the capacitor (C3) and all resistors to meet the design
criteria. A gain ratio of -20 V/V is required.

4.2) Ontwerp ‘n AIO vir L2 hierbo en gebruik C4 = 1 nF. [4] 4.2) Design a GIC for L2 above using C4 = 1 nF. Limit
Beperk die weerstandskeuse tot praktiese waardes. resistor choices to practical values.

4.3) Gee die volledige stroombaandiagram van die
ossillator. Gebruik Blok 02 in die voorsiende EPS
antwoordblad. Teken die volledige stroombaandiagram in
die enkele blok. Hierdie vraag sal met die hand gemerk
word.
[3] 4.3) Provide the complete circuit diagram of the
oscillator. Use Block 02 in the supplied EPS answer
sheets. Draw the circuit diagram in the single block.
This will be manually evaluated.

Voltooi vir 4 / Complete for 4:

Studente vul in / Students fill in: Evalueerder voltooi / Evaluator completes:

Waarde / Value Evaluasie / Evaluation Punt / Mark
4.1.1 L1 1000 nH Approach and calculations to meet:
4.1.2 L2 nH
4.1.3 C3 nF 4.1a Gain criteria 2
4.1.4 R1 kΩ 4.1b Frequency criteria 2
4.1.5 R2 kΩ 4.1c Component selection 1

4.2.1 Z1 nF or kΩ 4.1a Design approach 3

4.2.2 Z2 nF or kΩ 4.1b Component selection 1
4.2.3 Z3 nF or kΩ
4.2.4 Z4 1 nF
4.2.5 Z5 nF or kΩ

4.3 Use green EPS form ----------------- 4.3 Circuit configuration 3

TOTAL: 7

EINDE / END

ENE310 Semester Test 2 6

Copyright © 2019, Johan Schoeman, University of Pretoria