Mux 41:

Porgram :
entity mux4v1 is
Port (e0,e1,e2,e3,sel0,sel1: in std_logic; s: out std_logic);
end mux4v1;

architecture Behavioral of mux4v1 is

component mux2v1
port(a,b,e : in std_logic; s0: out std_logic);
end component;
signal i0, i1 : std_logic;
begin
m1 : mux2v1 port map (a=>e0, b=>e1, e=>sel0, s0=>i0);
m2 : mux2v1 port map(a=>e2, b=>e3, e=>sel0, s0=>i1);
m3 : mux2v1 port map(a=>i0, b=>i1, s0=>s, e=>sel1);
end Behavioral;

Simulation :
entity testadd is
-- Port ( );
end testadd;

architecture Behavioral of testadd is

component mux4v1
port(e0,e1,e2,e3,sel0,sel1 : in std_logic; s: out std_logic);
end component;
signal e0,e1,e2,e3,sel0,sel1,s : std_logic;
begin
m1: mux4v1 port map(e0,e1,e2,e3,sel0,sel1,s);
process
begin
e0 <= '1';
e1 <= '0';
e2 <= '0';
e3 <= '0';
sel0 <= '0';
sel1 <= '0';
wait for 20ns;
e0 <= '0';
e1 <= '1';
e2 <= '0';
e3 <= '0';
sel0 <= '1';
sel1 <= '0';
wait for 20ns;
e0 <= '0';
e1 <= '0';
e2 <= '1';
e3 <= '0';
sel0 <= '0';
sel1 <= '1';
wait for 20ns;
e0 <= '0';
e1 <= '0';
e2 <= '0';
e3 <= '1';
sel0 <= '1';
sel1 <= '1';
wait;
end process;
end Behavioral;

MUX21:

entity mux2v1 is
Port (a,b,e : in std_logic; s0 : out std_logic);
end mux2v1;

architecture Behavioral of mux2v1 is

begin

s0 <= (not(e) and a) or (e and a);

end Behavioral;