Atpg GD OCC

Chapter 17
Tessent On-Chip Clock Controller
In modern designs, on-chip clock control (OCC) circuits are commonly used to manage clocks
during test. Such clock controllers can generate slow-speed or at-speed clock sequences under
the control of ATPG process. Tessent OCC is an implementation of a clock controller created
by Tessent Shell that has been designed to meet the requirements of scan test for ATPG, Logic
BIST, EDT, and Low Pin Count Test.
Tessent OCC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Primary OCC Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
On-Chip Clock Controller Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
The Standard OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Standard OCC With IJTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
The Parent OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
The Child OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Tessent OCC Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Inserting the OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
occ.dft_spec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
post_dft_insertion_procedure.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
OCC Insertion When Using an Existing Clock as the test_clk DFT Signal. . . . . . . . . . . . 624
Core OCC Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Tessent OCC Overview

Using Tessent Shell, you can generate and insert Tessent OCCs into your design. You configure
the OCCs to generate programmable clock pulses under ATPG control. Additionally, you can
interface the TK/LBIST hybrid controller to a Tessent OCC that has a capture-enabled trigger
and external clock control capability.
In this capacity, a Tessent OCC is used to ensure that the following requirements are met:
• Independent control by ATPG of each clock domain to improve coverage, reduce

pattern count, and achieve safe clocking with minimal user intervention.
• During capture, deliver correct number of clock pulses on a per-pattern basis.
• Cleanly switch between shift and capture clocks.
• Enable slow or fast clocks during capture for application of slow and at-speed patterns.
• Scan-programmable clock waveforms generated within a wrapped core are ideal for
generating patterns at the core level. These patterns can be retargeted to the top level and
Tessent® Scan and ATPG User's Manual, v2018.1 601

March 2018
Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Primary OCC Functions
merged to simultaneously test multiple cores without conflicts in how clocks are
controlled within each core.
You can use the Tessent OCC with the following:
• OCC Tessent Core Description-based automation for ATPG

• TK/LBIST Hybrid Controller
Note
The Tessent on-chip clock control methodology is intended for use on designs where all
clock domains are internal. If you also have external clocks then you must divide your
transition ATPG into two separate sessions: one session for the external clocks and one session
for the internal clocks.

Typical on-chip clock controllers have three primary functions: control clock selection, clock
chopping control, and clock gating.
• Clock Selection
o Selects which always-capture or always-pulse clock is used.
o Selection of clock based upon frequency, test type, and other criteria.
• Clock Chopping Control
o Scan-programmable shift register controls clock pulse suppression.
o Creates enable signal for clock gating.
• Clock Gating
o Gates clock based upon clock chopping enable signal.
The Tessent OCC, by default, contains an internal clock gater. This option can be
disabled during the generation step.When the design already contains clock gaters,
the Tessent OCC can be generated with a clock enable signal. For information, see
the OCC section in the Tessent Shell Reference Manual.
When a Tessent OCC with a clock enable is used, the tool detects clock gating cell
controlled by the OCC. This process is automatic and does not require user input.
To allow proper detection of clock gating cells controlled by the OCC, the cells need
to be properly modeled in the Cell Library with the appropriate simulation functions.
For more information on library models, see Cell Library in the Tessent Cell Library
Manual.
Figure 17-1 shows the relationship of these three functions.
602 Tessent® Scan and ATPG User's Manual, v2018.1

March 2018
Figure 17-1. OCC Clock Control Components

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On-Chip Clock Controller Design Description
On-Chip Clock Controller Design Description

There are three types of on-chip controller designs: standard, parent, and child. You select them
based upon the requirements for your design.When using an OCC, you must consider the design
elements discussed in this section.
The Standard OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Design Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
Standard OCC Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
OCC With Capture Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Clock Control Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Standard OCC With IJTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
The Parent OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
The Child OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

March 2018
The Standard OCC
The Standard OCC

The standard OCC provides a fast clock for fast capture and a slow clock for shift and slow
capture. A scan programmable shift register allows ATPG to suppress or pulse clock cycles as
required. One usage for the standard OCC is Intest mode for pattern retargeting.
The standard OCC performs all three OCC functions: clock selection, clock chopping control,
and clock gating. Figure 17-2 shows a standard OCC implementation.
The standard OCC is the recommended OCC for use in hierarchical cores. For more
information, see “Core OCC Recommendation”.
Figure 17-2. Standard OCC Example
Design Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Standard OCC Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
OCC With Capture Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Clock Control Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Design Placement
The OCC should be inserted such that the fast clock input of the OCC is driven by the functional
clock source, typically a PLL. Ideally, the OCC is placed near the clock source (PLL) but
should be placed inside cores to allow for local clock control as needed for pattern retargeting
flows. The OCC uses a top-level slow clock for shift and slow capture as well as a test mode
signal that determines if a test or functional clock is supplied to the design.
Figure 17-3 shows an example of OCC placement.

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The Standard OCC
Figure 17-3. Clock Control Logic Design Placement
Depending on your design style, you may need to guide the Clock Tree Synthesis (CTS) not to
balance the flops and latches in the OCC with the clock tree it drives.
There is no reason for you to add a clock mux after the OCC for functional mode because the
fast_clock propagates through when the test mode signal is de-asserted. Additionally, having a
common path for the fast clock in functional mode and test mode simplifies clock tree synthesis
and timing closure.
The clock control design is used to supply the clock when in functional and test modes. In
functional mode, the fast clock is passed to the design. In test mode, the fast clock is used for at-
speed capture while a top-level slow clock will be used for shift and slow capture. The reference
clock supplied to the PLL is a free-running clock, typically pulse-always.
It is recommended not to flatten the clock control blocks during layout in order to ease
automation of defining the clock gating logic and its operation.
Standard OCC Schematic

The schematic for the on-chip clock control circuit is shown in this figure.
The schematics shown represent an OCC that is generated without an IJTAG interface. To learn
how an OCC with an IJTAG interface differs, see “Standard OCC With IJTAG Interface.”

March 2018
The Standard OCC
Figure 17-4. On-Chip Clock Controller Logic Schematic
Table 17-1 describes the functionality of the clock controller I/O signals.
Table 17-1. Clock Controller I/O Signals
Name Direction Description
scan_en Input Scan enable driven by top-level
pin
capture_cycle_width:[1:0] Input1 Configures the maximum number
of clock pulses during capture
cycle as well as the length of the
scan chain:
00 - 1 pulse - 1 scan cell
01 - 2 pulses - 2 scan cells
For example, if the max sequential
depth to be used is 2, this bus can
be configured to "01" instead of
default "11". This can reduce the
number of shift cycles, and more
importantly reduces the number of
bits which need to be encoded if
the OCC chain is driven by a
decompressor.
scan_in Input Scan chain input for loading shift
register
fast_capture_mode Input1 Selects fast or slow capture clock
(0 = slow, 1 = fast)

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The Standard OCC
Table 17-1. Clock Controller I/O Signals (cont.)

test_mode Input1 Selects test or functional mode (0
= functional, 1 = test). When test
mode is disabled, fast clock drives
clock_out to enable functional
mode. Remaining clock gaters are
disabled to minimize switching
activity
fast_clock Input Clock for fast capture (typically
output of PLL, free_running or
pulse_always)
slow_clock Input Clock for shift and slow capture
scan_out Output Scan chain output for unloading
shift register
clock_out Output Controlled clock output
1. Static signals that do not change during the test session should be controlled through on-chip
controllers (such as IJTAG) or other means in order to reduce the need for top-level pins.
Slow Clock Driving Sequential Elements

The top-level slow clock used for shift and slow capture must not control any sequential
elements directly because slow clock acts as a trigger for capture during fast-capture mode.
During fast-capture, the necessary slow clock pulse(s) are not simulated by the tool and can
result in simulation mismatches. This requirement is explained in more detail in the following
section.
Scan Enable Synchronization

In order to synchronize the top-level scan enable signal with the fast clock (PLL output), a two
flop synchronization cell is used and clocked by fast clock. This is important because scan
enable is used as the trigger signal to gate the clock to the shift register. The output of the
synchronization cell produces a scan enable signal which is synchronized with the fast clock
and can be used during fast capture test.
Additionally, a flop is used on the input side of the synchronization cell and clocked by the
trailing edge of slow clock. Since scan enable normally fans out to the entire circuit and may
arrive after fast clock, the flop on slow clock ensures that scan enable is not synchronized by the
fast clock until slow clock is pulsed, thus reducing the risk of a race condition.
In order to ensure proper DRC analysis and simulation, the output of the clock gater cell driven
by the synchronization logic is defined as a pulse-in-capture internal clock. When using the
TCD flow for pattern generation, the tool automatically defines the internal clock as a pulse-in-

March 2018
The Standard OCC
capture clock. This ensures correct simulation of the logic during load_unload and avoids
unnecessary DRC violations.
The synchronization cell (sync_cell) shown in Figure 17-4 has an asynchronous reset port that
is driven by scan_en if it is active high. If the reset port of the synchronous cell is active low it is
driven by ~scan_en.
In the RTL description, the synchronization cell is described as a separate module so that it can
be replaced with a technology specific synchronization cell from the appropriate library.
Slow Clock Pulses in Capture

Given that slow clock is used to capture scan enable before it is synchronized by fast clock, it
must not directly drive any sequential elements that may impact the scan operation. This is
because the slow and fast clocks are not assumed to be synchronized thus the pulse on slow
clock at the beginning of capture is defined in the external_capture procedure used for fast
capture:
procedure external_capture ext_fast_cap_proc =

timeplate tmp1 ;
cycle =
force_pi ;
pulse slow_clock;
end;
end;
The tool does not simulate clock pulses defined in external_capture procedures when it
calculates the expect values in the patterns. The clock pulses defined in this procedure are added
to the created patterns after ATPG to ensure correct operation in fast capture mode. Since the
output of the clock gating logic is defined as a pulse-in-capture internal clock, the tool does not
need to simulate the clock pulse on the register that first captures scan enable. However, if slow
clock controls any other sequential elements, it can result in simulation mismatches.
Handling Slow Scan Enable Transitions

If the frequencies of slow and fast clocks are close, it may be necessary to add more delay
before the fast capture pulses in order to allow scan enable enough time to settle to 0. Similarly,
it may be desired to delay the scan enable transition from 0 to 1 after capture and before the next

March 2018
The Standard OCC
load/unload operation. This requires additional cycles to be added to the external_capture

procedure as shown in the following example:
procedure external_capture ext_fast_cap_proc =

timeplate tmp1 ;
cycle =
force_pi ;
end;
cycle =
end;
cycle =
end;
cycle =
pulse slow_clock;
end;
cycle =
end;
cycle =
end;
end;
Adding external_capture cycles with no slow_clock pulses before the cycle that pulses
slow_clock, delays the fast clock pulses to give scan enable sufficient time to transition to 0.
Empty cycles after the pulse on slow_clock, delay the load/unload operation to give scan enable
sufficient time to transition to 1.
Note
The scan enable synchronization operation described in this section is not used for slow
capture mode which uses slow clock for shift and capture.
Fast Capture Commands

When not using named capture procedures (NCP), the following three commands are
automatically set by the create_patterns command for fast capture:
set_output_masks on
add_input_constraints -all -hold
set_clock_restriction domain_clock -any_interaction \
-compatible_clocks_between_loads on
The preceding three commands are not needed when using NCPs because the capture clock
sequence and time for forcing PIs and measuring POs are explicitly defined by the user in
NCPs.
However, you will need to specify:
set_external_capture_options ...

March 2018
The Standard OCC
Bypass Shift Path

Figure 17-4 shows the standard OCC schematic has a single BYPASS_SHIFT_FF_reg flop.
This flop is also in the parent and child OCCs. Setting the test_mode signal of OCCs not used
for a particular test mode puts them into functional mode. The OCC sub-chain is part of the
design’s scan chains and, even when the OCC is not being used for a particular test mode and
other parts of the design are being tested, the scan chains must continue to work. While in the
functional mode, the path from scan_in to scan _out remains accessible by shifting through the
BYPASS_SHIFT_FF_reg flop.
OCC With Capture Enable

There is an OCC with a capture_enable input that can be used with a free-running slow clock.
When the OCC is specified with capture enabled (capture_trigger : capture_en), a clock gater is
added on the input free-running slow clock to generate appropriate clock pulses from the free
running clock input. The enable signal for this clock gater is an OR gate output whose inputs are
scan_en and capture_en. This allows the slow_clock pulses to be generated during shift and
capture cycles respectively.
Figure 17-5 shows the OCC schematic with the clock gater at the lower left.
Figure 17-5. OCC with capture_en
This version of the OCC can also be used with a tester provided slow clock (that is not free
running). In this case, the new clock gater simply lets the controlled slow clock pass through
during shift and capture.

March 2018
The Standard OCC
For LBIST and LPCT applications, an OCC that uses a free-running slow clock is required. This
free running clock is connected to either the shift_clock of the LBIST controller or the LPCT
input clock.
Clock Control Operation Modes

There are four modes as follows.
Functional Mode
When operating in functional mode (test_mode = 0), the fast clock gater is enabled to supply
fast clock to the design. The slow clock and internal clock gaters are disabled to reduce power.
Figure 17-6. Functional Mode Operation
Shift Mode
In shift mode (scan_en = 1), slow_clock is used to load/unload scan chains which include the
condition bits in ShiftReg.

March 2018
The Standard OCC
Figure 17-7. Shift Mode Operation
Shift-Only Mode
In shift-only mode, the OCC is disabled (test_mode = 0) but shift is enabled (scan_en = 1). In
this mode, the slow_clock clock gater is enabled to ensure slow clock path is always used for
shift. Additionally, bypass shift is enabled.
Figure 17-8 shows that both inactive (test_mode = 0) and active OCCs use slow_clock for shift.
By default, Standard and Parent OCCs will enable the shift clock path anytime scan_en is 1,
even if the OCC is inactive; this ensures consistent shift timing in internal and external modes.
Figure 17-8. OCC Shift Clocking
To change the default and use the functional clock instead of the test clock, set the
shift_only_mode OCC wrapper property to off.

March 2018
The Standard OCC
Slow Capture Mode

In slow capture mode (fast_capture_mode = 0), slow_clock is used to capture data into scan
cells and to shift the condition bits in ShiftReg.
Figure 17-9. Slow Capture Mode
Fast Capture Mode

In fast capture mode (fast_capture_mode = 1), fast_clock is used to capture data into scan cells
and to shift the condition bits in ShiftReg.
Figure 17-10. Fast Capture Mode Operation

March 2018
The Standard OCC
Timing Diagrams
The timing diagram for slow speed capture (fast_capture_mode = 0) is shown in the following
figure:
Figure 17-11. Slow Speed Capture Timing Diagram
For this example, capture_cycle_width is set to “10” resulting in a maximum sequential depth
of 3. In this mode, slow clock is used for shift as well as capture. Based on condition bits loaded
into the shift register, the clock_out port will generate the appropriate number of slow clock
pulses.
In fast capture mode (fast_capture_mode = 1) the waveforms in Figure 17-12 are generated.
Similar to the previous example, capture_cycle_width is set to “10” here resulting in a
maximum sequential depth of 3. In this mode, the slow_clock is still used for shift but the fast
capture pulses on clock_out are based on fast_clock.
Figure 17-12. Fast Capture Timing Diagram
As shown, the scan enable signal which has been synchronized to the fast clock (sync_cell/q) is
used to trigger the fast clock pulses on ShiftReg/clk. The ShiftReg/clk signal is the clock source
for the shift register containing the condition bits. Based on the condition bits loaded during
shift, the correct number of fast clock pulses will appear on clock_out.

March 2018
Standard OCC With IJTAG Interface
Standard OCC With IJTAG Interface

An OCC created with an IJTAG interface has an additional multiplexer not present in an OCC
without IJTAG.
As shown in Figure 17-13, a multiplexer is added to the slow_clock path to inject ijtag_tck
when an OCC is created with an IJTAG interface (when ijtag_host_interface is set to something
other than none).
Figure 17-13. Standard OCC with IJTAG Interface
Figure 17-14 highlights the functionality of the mux added to the slow_clock input of the OCC.
When inject_tck is 1, the mux selects ijtag_tck which drives clock_out through the slow clock
gater and the output mux.

March 2018
The Parent OCC
Figure 17-14. OCC With IJTAG Interface: ijtag_tck injected for slow clock
The Parent OCC

As one of the three OCC types, the parent OCC has two modes, standard mode and parent
mode. In standard mode it selects and gates clocks for testing top-level logic. In parent mode,
this OCC is used for clock selection only.
Parent OCC Schematic in Standard Mode Figure 17-15 shows a parent OCC used in standard
mode. A typical use for this mode is pattern retargeting in Extest mode, when interactions
between core-level boundary logic (wrapper chains) and top-level logic are being tested.
Figure 17-15. Parent OCC in Standard Mode (Extest Mode)

March 2018
The Parent OCC
In parent mode, the OCC is used for clock selection only. The parent OCC typically feeds the
clock input of a child OCC. Figure 17-16 shows a parent OCC in parent mode. An example use
for this mode is pattern retargeting in Intest mode.
Figure 17-16. Parent OCC in Parent Mode (Intest Mode)
Figure 17-17 shows the parent on-chip controller logic. In parent mode, the OCC injects the
shift clock at the base of the clock in shift mode. When scan _en is low, it lets a programmable
constant set of clock pulses go through.
The parent OCC usually feeds the clock input of a child OCC which, in turn, enables the scan-
based test pattern generation tool to control which clock pulses go through or not.
Figure 17-17. Parent On-Chip Controller Logic Schematic
Table 17-2 describes the functionality of the clock controller I/O signals.

March 2018
The Child OCC
Table 17-2. Parent OCC I/O Signals

parent_mode Input Defines whether the OCC is
used in parent mode. When
the default (0) is used, the
OCC functions in standard
mode, selecting and gating
clocks for top-level testing.
When in parent mode (1), the
OCC is used for clock
selection only.
For a description of remaining I/O signals, see Table 17-1 in the Standard OCC Schematic
section.
The Child OCC

The child OCC is one of the three OCC types. It performs the clock chopping control function
of the OCC and, optionally, also gates the clock.
By default, the child OCC creates the clock enable signal based on values loaded into the scan-
programmable shift register. This enable signal is used to control the (optional) clock gater
inside the OCC as shown in Figure 17-18.
Figure 17-18. Child OCC Gates and Creates Clocks (with Parent OCC)
Figure 17-19 shows a detailed example schematic of the child on-chip controller with a clock
gater.

March 2018
The Child OCC
Figure 17-19. Child On-Chip Controller Logic Schematic
In some cases, it is not practical to use a child OCC with an internal clock gater. Optionally, the
child OCC can be created without the internal clock gater. The created signal enables layout
tools to replicate and control the design’s clock gaters for implementations such as a clock
mesh. The handling of user provided clock gating cells is transparent to the user. This is shown
in Figure 17-20.
Figure 17-20. Child OCC Creates Enable for Clock Gaters (with Parent OCC)
Figure 17-21 shows the child on-chip controller logic without the clock gater.
Figure 17-21. Child On-Chip Controller Logic Schematic, no Clock-Gater

March 2018
The Child OCC
To properly operate the clock gaters during capture, a sensitized path must exist between the
OCC clock enable port and the clock gaters. If there is no sensitized path from the OCC to the
clock gaters, but a structural connection exists, the tool verifies that the clock gaters are disabled
during capture.

March 2018
Tessent OCC Insertion
Tessent OCC Insertion

Tessent Shell is used to insert the OCC.
You define the Tessent OCC using DftSpecification configuration syntax. The OCC
DftSpecification defines connections for slow clock, scan enable, and static OCC signals.
To achieve the best configuration for compressed ATPG, you will need to stitch the OCC sub-
chains into the scan chains. For more information, refer to “OCC Sub-Chain Stitching” in the
Tessent TestKompress User’s Manual.
The basic procedure for inserting Tessent OCCs is described below. For more detailed
examples of inserting OCCs in a flow and using them for pattern generation, refer to “Tessent
Shell Flow for Flat Designs” and “Tessent Shell Flow for Hierarchical Designs” in the Tessent
Shell User’s Manual.
Inserting the OCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

occ.dft_spec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
post_dft_insertion_procedure.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
OCC Insertion When Using an Existing Clock as the test_clk DFT Signal . . . . . . . . . . 624
Inserting the OCC

This procedure uses Tessent Shell to insert an instance of the OCC logic for each internal clock.
Procedure
1. Invoke Tessent Shell from the shell prompt.
% tessent -shell
2. Set the Tessent Shell context to ‘dft’.

SETUP> set_context dft -no_rtl -design_identifier occ
3. Read in the design netlist. For example:w

SETUP> read_verilog cpu_core.vg.gz
4. Read cell library to allow creation of some instances such as muxes. For example:
SETUP> read_cell_library adk.tcelllib
5. Set the current design. For example:

SETUP> set_current_design cpu
SETUP> set_design_level sub_block

March 2018
occ.dft_spec
6. Read the configuration file to specify OCC insertion parameters. For example:
SETUP> read_config_data occ.dft_spec
7. Optionally define the port list and procedure to insert on-chip control for clocks and to
connect condition bits of OCC into new scan chain after DFT spec is processed. See
post_dft_insertion_procedure.tcl for an example.
8. Validate and process the content defined in the DftSpecification wrapper.
SETUP> process_dft_specification
9. Synthesize the generated RTL. For example:

SETUP> run_synthesis
This step only applies when inserting the OCC RTL into a gate-level netlist. When
inserting into an RTL design, the OCC is synthesized along with the rest of the design.
The run_synthesis command also writes the updated netlist to the TSDB directory.
10. If needed, optionally write out the updated netlist. For example:
SETUP> set_current_design
SETUP> write_design
-output_file cpu_core_post_occ_insertion.vg.gz -replace
11. Exit the tool.

SETUP> exit
occ.dft_spec
The following example shows a basic OCC DftSpecification:
DftSpecification(cpu, occ_core) {
reuse_modules_when_possible: on;
OCC {
Controller(CLK1_OCC) {
// DEFINE ROOT OF CLOCK DOMAIN WHERE OCC SHOULD BE INSERTED
clock_intercept_node: /BUF_OCC_1/Y;
}
}
}
}
}

March 2018
post_dft_insertion_procedure.tcl
post_dft_insertion_procedure.tcl
Tcl procedure for post-DFT insertion.
This OCC insertion example contains the process_dft_specification.post_insertion procedure.
The procedure name is a keyword that instructs the process_dft_specification command to
execute the content of the procedure immediately after inserting the specified DFT logic.
The post-insertion script creates a scan chain that concatenates the shift registers of all inserted
OCCs into one uncompressed scan chain. Additionally, a dofile is created for adding the clock
control scan chain in subsequent steps. Typically, the OCC sub-chains will be stitched to the
design's scan chains during scan insertion. In this post-scan insertion example, the
post_dft_insertion example is used to demonstrate the capability of making design edits after
insertion
proc process_dft_specification.post_insertion {cpu args} {

# Create ports for control scan chain
create_port occ_control_scan_in -direction input
create_port occ_control_scan_out -direction output
# Concatenate OCC condition bit shift registers into new control scan
#chain
set first_inst 1
foreach inst_name [get_name_list [get_instances -of_module
cpu_occ_core_tessent_occ]] {
if ($first_inst) {
create_connection occ_control_scan_in $inst_name/scan_in
set first_inst 0
set last_inst_name $inst_name
} else {
create_connection $last_inst_name/scan_out $inst_name/scan_in
set last_inst_name $inst_name
}
}
create_connection $last_inst_name/scan_out occ_control_scan_out
}
# Create dofile to define OCC control scan chain
set file_dofile [open source/dofiles/occ_scan_setup.dofile w]
puts $file_dofile
“# Define clock control scan chain. Should be
uncompressed if number of OCCs is high to reduce specified bits.”
puts $file_dofile “add_scan_chains clock_control_chain grp1
occ_control_scan_in occ_control_scan_out”
close $file_dofile
OCC Insertion When Using an Existing Clock as the

test_clk DFT Signal
To prevent D1 DRC errors when using an existing clock as the test_clock DFT signal, you must
insert an OCC in the functional clock path that does not interfere with the clock gating cells.

March 2018
OCC Insertion When Using an Existing Clock as the test_clk DFT Signal
Figure 17-22 shows a clock, created using the command “add_clocks clk -pulse_always”,
driving sequential elements.
Figure 17-22. Original Clocking
You want to use the clk pin as the DFT test_clock, so you use the command, “add_dft_signals
test_clock -source_nodes clk”. You also create the DFT signals edt_clock and
shift_capture_clock from the test_clock DFT signal using the command “add_dft_signals
{edt_clock shift_capture_clock} -create_from_other_signals”.
Figure 17-23 shows the design with the clock gating cells that are added by the tool for
edt_clock and shift_capture_clock. It also shows the OCC inserted in a location where it
intercepts the clock signal “clk”. This OCC placement interferes with your goal of a direct,
free-running clock to the clock gating cells.
Figure 17-23. Incorrect OCC Placement

March 2018
Core OCC Recommendation
To correct this issue, you must move the OCC to a location on the functional clock path that will
not interfere with the direct, free-running clock to the clock gating cells. In some cases, you may
need to add an anchor point for the OCC, such as a buffer. Figure 17-24 shows the OCC in a
suitable location at the output of a user-added buffer.
Figure 17-24. Correct OCC Placement

The standard OCC is recommended for use in hierarchical cores to simplify timing closure and
ATPG setup.
The standard OCC is preferred for core-level implementation instead of a parent/child OCC
combination. It has a fast and slow clock, as well as a scan programmable shift register, which
allow it to be used without the additional requirements that come with using a child OCC. See
The Standard OCC section for more information.
Although it is not recommended for use in hierarchical cores, the parent/child OCC
implementation is useful in designs that use a clock mesh or when a mux is not allowed inside
the hierarchical core.
Shift Timing for Core-level Child OCC

The core-level child OCC has a single clock on the core boundary. The clock is used for shift as
well as slow and fast capture. This feature creates additional requirements to meet shift timing
in the core. Figure 17-25 shows a core with two clocks, each with a child OCC that drives scan
cells. There is also a test clock used during shift to control test logic, EDT logic, and other logic
in the core.

March 2018
Figure 17-25. Child OCC in Core
When you use a child OCC in the core, these items need to be considered and addressed during
shift mode:
• There are multiple clocks on the boundary of the core that drive the scan cells.
• Timing closure at the core level must balance multiple clock paths, during shift mode, in
addition to functional mode.
• The top-level clock path timing from the parent OCC to the core impacts shift and
capture.
• Timing closure must balance functional clock paths for test clock.
Shift Timing for Core-level Standard OCC

The features of the standard OCC make is simpler to meet core-level shift timing requirements.
Figure 17-26 shows a core with a standard OCC implementation.

March 2018
Figure 17-26. Standard OCC in Core
These are some of the benefits when you use a standard OCC at the core level:
• During shift, all scan cell clocks are sourced from test clock.
• Timing analysis can be closed in shift mode without skew between different clock
branches.
• The top-level functional clock paths do not impact shift.
• There is no need to balance functional clock paths to test clock for shift mode.
Fast Capture ATPG Timeplate Setup

Another requirement that increases the complexity of using a child OCC for hierarchical cores
is that two timeplates are required for accurate simulation of the core’s fast capture patterns.
This is due to the fact that the single child OCC clock is used for shift as well as slow and fast
capture.
The timeplates are supplied to the tool with the following command:
set_procfile_name <file_with_two_timeplates>

March 2018
By default, the first timeplate in the file is considered the default timeplate and is used for shift.
If the first timeplate in the file is not for shift, use this command:
set_procedure_retargeting_options -timeplate <name_of_shift_timeplate>
The timeplate for capture is defined using this command:
set_external_capture_options -pll_cycles <name_of_capture_timeplate>
The timeplate for shift defines a single pulse on clock and for capture, it defines multiple clock
pulses to match the functional frequency of the clock:
set time scale 1 ps;

timeplate shift_tp =
force_pi 50;
measure_po 100;
pulse func_clk1 1600 3200; //156 MHz
pulse func_clk2 1600 3200; //156 MHz
period 6400;
end;
timeplate capture_tp =
force_pi 50;
measure_po 100;
pulse func_clk1 800 1600, 4000 1600; //312 MHz
pulse func_clk2 400 800, 2000 800, 3600 800, 5200 800; //625 MHz
period 6400;
end;

March 2018

March 2018

Atpg GD OCC

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Chapter 17

Tessent On-Chip Clock Controller

Tessent OCC Overview

• Independent control by ATPG of each clock domain to improve coverage, reduce

Tessent® Scan and ATPG User's Manual, v2018.1 601

• OCC Tessent Core Description-based automation for ATPG

Primary OCC Functions

602 Tessent® Scan and ATPG User's Manual, v2018.1

Figure 17-1. OCC Clock Control Components

Tessent® Scan and ATPG User's Manual, v2018.1 603

On-Chip Clock Controller Design Description

604 Tessent® Scan and ATPG User's Manual, v2018.1

The Standard OCC

Figure 17-2. Standard OCC Example

Design Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Tessent® Scan and ATPG User's Manual, v2018.1 605

Figure 17-3. Clock Control Logic Design Placement

Standard OCC Schematic

606 Tessent® Scan and ATPG User's Manual, v2018.1

Figure 17-4. On-Chip Clock Controller Logic Schematic

Tessent® Scan and ATPG User's Manual, v2018.1 607

Table 17-1. Clock Controller I/O Signals (cont.)

Slow Clock Driving Sequential Elements

Scan Enable Synchronization

608 Tessent® Scan and ATPG User's Manual, v2018.1

Slow Clock Pulses in Capture

procedure external_capture ext_fast_cap_proc =

Handling Slow Scan Enable Transitions

Tessent® Scan and ATPG User's Manual, v2018.1 609

load/unload operation. This requires additional cycles to be added to the external_capture

procedure external_capture ext_fast_cap_proc =

Fast Capture Commands

However, you will need to specify:

610 Tessent® Scan and ATPG User's Manual, v2018.1

Bypass Shift Path

OCC With Capture Enable

Figure 17-5. OCC with capture_en

Tessent® Scan and ATPG User's Manual, v2018.1 611

Clock Control Operation Modes

Figure 17-6. Functional Mode Operation

612 Tessent® Scan and ATPG User's Manual, v2018.1

Figure 17-7. Shift Mode Operation

Figure 17-8. OCC Shift Clocking

Tessent® Scan and ATPG User's Manual, v2018.1 613

Slow Capture Mode

Figure 17-9. Slow Capture Mode

Fast Capture Mode

Figure 17-10. Fast Capture Mode Operation

614 Tessent® Scan and ATPG User's Manual, v2018.1

Figure 17-12. Fast Capture Timing Diagram

Tessent® Scan and ATPG User's Manual, v2018.1 615

Standard OCC With IJTAG Interface

Figure 17-13. Standard OCC with IJTAG Interface

616 Tessent® Scan and ATPG User's Manual, v2018.1

The Parent OCC

Figure 17-15. Parent OCC in Standard Mode (Extest Mode)

Tessent® Scan and ATPG User's Manual, v2018.1 617

Figure 17-16. Parent OCC in Parent Mode (Intest Mode)

Figure 17-17. Parent On-Chip Controller Logic Schematic

618 Tessent® Scan and ATPG User's Manual, v2018.1

Table 17-2. Parent OCC I/O Signals

The Child OCC

Tessent® Scan and ATPG User's Manual, v2018.1 619