Int. J. Electron. Commun.

(AEÜ) 91 (2018) 37–43

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Int. J. Electron. Commun. (AEÜ)

journal homepage: www.elsevier.com/locate/aeue

Regular paper

A Ka-band low power consumption MMIC core chip for T/R modules T
⁎
Min Zhou , Jiongjiong Mo, Zhiyu Wang
School of Aeronautics and Astronautics, Zhejiang University, Hangzhou 310012, China

A R T I C LE I N FO A B S T R A C T

Keywords: This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs
Core chip pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit
Ka-band attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core
MMIC chip results in a gain of 9.0 dB and an output P1dB of –3 dBm. In the transmitting mode, the gain and output P1dB
Wide band
are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°.
Low power consumption
The power consumption is 150 mW in both work modes. The measured results show that the operating band-
width, power consumption, gain, rms attenuation error and phase error have been significantly improved
compared with the previous reports.

1. Introduction application requirements of satellite communications, data links, etc.

Compared with the traditional mechanically steerable antenna, ac-
tive phased array antenna has a series of advantages such as fast
scanning speed, various scanning modes, high reliability and easy
maintenance. Recent years, the Ka-band active phased array antenna
shows strong demand in the areas of satellite communications, data
links and military radars [1]. T/R modules are the core components of
the phased array antenna, they are usually composed of a number of
MMICs into a microwave circuit to achieve signal amplification,
transmitting and receiving mode conversion, amplitude and phase
control functions. In order to complete the above functions, a chipset
including the transmit and receive amplifiers, T/R switch, digital at-
tenuator, digital phase shifter is often required [2–4].
However, this integration method leads to several issues, such as
cost, size, reliability and consistency. As the size of the antenna array
continues to grow, the number of T/R modules installed is also greatly
increased. Therefore, core chip is emerging as a way to increase the
integration, improve reliability and consistency, reduce cost and size.
To date, core-chips below Ku-band have shown good performance.
Some of them have completed reliability tests [5–7]. But when applied
to Ka-band (above 26 GHz), the electromagnetic interference between
circuits becomes more serious, and the performance such as operating
bandwidth, phase shift and attenuation accuracy deteriorates sig-
nificantly [11–13]. The compact Ka-band core-chip presented in this
paper aims to solve the above problems and reduce power consumption
through circuit topology design and layout optimization. The larger
operating bandwidth and lower power consumption can well meet the
In the following, the circuit topology design, EM simulation results
of the Ka-band core-chip will be presented, together with the mea-
surement results and comparison to the previous reports.
2. Design and fabrication
The functional circuit of the core chip consists of five parts: trans-
mitting amplifier, receiving amplifier, 5-bit digital attenuator, 5-bit
phase shifter and SPDT switch. For most phased array antennas, the
transmitting channel does not need to adjust the power level through
the attenuator. Therefore, we place the attenuator before the SPDT
switch and after the receiving amplifier in order to increase the gain of
the transmitting channel. As a result, the noise figure of the receiving
channel will be improved. Amplifier and SPDT switch share +5 V
power supply. Attenuator and phase shifter are both controlled by 5 bit
parallel digital signal (0/−5 V). The functional block diagram of the
core chip is shown in Fig. 1.
2.1. Amplifier
The transmitting/receiving amplifier has three cascaded transistors,
ensuring that the amplifier provides at least a small signal gain of 21 dB
and output P1dB of 12 dBm (see Figs. 2 and 3). For the circuit design, a
self-bias structure is adopted at the source to cancel the negative power
supply requirement. While providing the easy power control, it also can
better improve the stability of the amplifier, and minimize the loss of
gain. The input, output and intermediate impedances matching are all

⁎
Corresponding author.
E-mail addresses: zhoumin@zju.edu.cn (M. Zhou), jiongjiongmo@zju.edu.cn (J. Mo), zywang@zju.edu.cn (Z. Wang).

https://doi.org/10.1016/j.aeue.2018.04.027
Received 19 December 2017; Accepted 25 April 2018
1434-8411/ © 2018 Elsevier GmbH. All rights reserved.
M. Zhou et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 37–43

+5V Tx Power Supply

-5/0V Logic Control

Tx Amp

SPDT
Tx_out

Com

Rx_in
Phase Shifter

Attenuator Rx Amp

+5V Rx Power Supply

Fig. 1. Functional block diagram of core chip.

0 30 finished by distributed components. The MIM capacitor is only used for

DC block. For Ka-band chip, the EM simulation accuracy of distributed
-5 25 components is obviously higher than that of lumped components, and
Return Loss (dB)

the insertion loss is also smaller. Therefore, other microwave circuits in

-10 20
Gain (dB)

this paper will refer to similar guidelines for design. The circuit to-
Output
-15 15 pology of the amplifier is shown in Fig. 4.
Input
-20 10 2.2. SPDT switch

-25 5 Commonly, we need at least a pair of control pad for channel

switching [8]. For the normal operation mode of the T/R module, the
-30 0
SPDT control signal must be switched when the power signal of
32 33 34 35 36 37 38
working status channel is turned on. Therefore, it is possible to replace
Freq (GHz)
the switch control signal with the power signal. Fig. 5 is the SPDT
Fig. 2. EM simulated gain & return loss of amplifier. circuit topology. It adopts the structure of three parallel switch tran-
sistors. The gate is connected to the ground through a 20 kΩ resistor.
22.0 16 Large resistance can guarantee the isolation of gate and source. We put
a DC block capacitor on both end of the path to ensure the stability of
21.5 14
the drain voltage. For instance, when the power signal is switched to
Output Power (dBm)

21.0 12 the transmitting path, the gate to drain voltage VGD = −5V. Then the
Power Gain (dB)

20.5 10 switch transistor is off and the path turns on. When the power signal is
switched to the receiving path, VGD = 0V means the parallel transistor
20.0 8
is on and the path turns off Figs. 6 and 7 show the EM simulated results.
19.5 38 GHz
6
35 GHz
19.0 32 GHz 4 2.3. Attenuator
18.5 2
18.0 0 The 5-bit attenuator is composed of 0.5 dB, 1 dB, 2 dB, 4 dB, and
-20 -15 -10 -5 8 dB attenuation cells. LSB is designed as simple switched-T config-
Input Power (dBm) uration. Other cells are designed as Lange coupler structures. The
switched-T and bridge-T configurations are common used for at-
Fig. 3. EM simulated power characteristic of amplifier. tenuator [9], significant phase modulation effect due to asymmetry will
seriously affect the performance of the attenuator in Ka-band. If mat-
+5V ched components are used for phase compensation, the band width of
the circuit will be significantly affected. Fig. 8 structure can be a good
method to avoid this problem. The area of Lange coupler will be greatly
reduced due to the frequency increase, which can be easily integrated.
When the two symmetrical transistors connected to the transmit and
coupled ports are turned off, the RF signal is completely reflected and
synthesized at the isolated port, only a small part of the energy is lost
through the transmission line. When the transistors are turned on, part
RF_IN RF_OUT
of the RF signal leaks to the ground, part of the signal is reflected to the
isolated port. This is how we control the signal to a specific amount of
attenuation. Adjusting the gate width of the transistor will precisely

Fig. 4. Schematic of 3 stage self-bias amplifier.

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M. Zhou et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 37–43

Com

+5V Rx +5V Tx

Rx_in Tx_out

Fig. 5. Schematic of power supply control SPDT.

-1.2 -28 0 0.5

Attenuation RMS error (dB)

-1.3 -29
-1 0.4

Insertion Loss (dB)

Insert Loss (dB)

-1.4 -30
-2 0.3
Isolation
-1.5 -31

-1.6 -32
-3 0.2
-1.7 -33

-1.8 -34 -4 0.1

-1.9 -35
-5 0.0
32 33 34 35 36 37 38
32 33 34 35 36 37 38
Freq (GHz)
Freq (GHz)
Fig. 6. EM simulated insert loss & isolation of SPDT switch.
Fig. 9. EM simulated insert loss & rms attenuation error of attenuator.

0
control the attenuation of every single bit. Because of the symmetrical
-5 Lange coupler, it is easy to control the phase of the input and output RF
signal by distributed components. Therefore, the relative phase error
-10
due to attenuator control will be small. Fig. 9 shows the simulated
Return Loss (dB)

-15 Output 2.5 dB insert loss and 0.25 dB rms attenuation error.
-20 Input

-25 2.4. Phase shifter

-30 The 5-bit phase shifter in the common path is composed of 11.25°,
-35 22.5°, 45°, 90°, 180°. The phase of the transmitting/receiving signal can
be modified from 0° to 348.75° with 11.25° LSB. The commonly used
-40 phase shifter circuit requires at least two control ports for different state
32 33 34 35 36 37 38 switching purpose. So the 5-bit phase shifter requires 10 control ports
Freq (GHz) [10]. In order to reduce them, the MIM capacitor is used to isolate the
Fig. 7. EM simulated return loss of SPDT switch. cells. The bit-N port provides –5 V to the gate of the switch transistor of
the reference state. At the same time, the corresponding control voltage
is applied to the source and drain of the reference state switch transistor
Bit1 Bit2 Bit0 Bit3 Bit4
RF_IN RF_OUT and the gate of the phase-shifted state switch transistor. In this case, the
VGD is still on. When VGS = 0 V, the switch transistor is turned on. When
VGD = VGS = −5 V, the switch transistor is off. Then we can see the
control pad has reduced from 10 to 6. 11.25°, 22.5°, 45° cells are de-
signed as bridge-T configuration. The low-pass network is composed of
transmission line and capacitors to provide different phase shift values.
The switch transistors in series and in parallel control the different
paths. 90° cell is designed similar as attenuator. We tuned the para-
meter of the Lange coupler to obtain a certain phase shifter value at the
expense of the insert loss. The paralleled inductor with switch transistor
regulates the parasitic capacitance so that the phase characteristics can
be preciously adjusted. 180° cell is designed as SPDT configuration. The

Fig. 8. Schematic of 5-bits attenuator.

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M. Zhou et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 37–43

Bit2 Bit3 Bit1 Bit4 Bit0 Bit-N

RF_OUT

Fig. 10. Schematic of 5-bits phase shifter.

-5 5

-7 4 Phase RMS error (deg)

Insert loss (dB)

-9 3

-11 2

-13 1

-15 0
32 33 34 35 36 37 38 Fig. 12. Core chip microphotograph (4.8 mm × 2.5 mm).
Freq (GHz)
Fig. 11. EM simulated insert loss & rms phase error of phase shifter. The core chip is fabricated by a 0.15 μm D-mode GaAs pHEMT
process with a total size of 4.8 mm × 2.5 mm. Fig. 12 shows the mi-
high-pass network formed by the lumped elements and the band-pass crophotograph of the fabricated core chip. The common port is located
network formed by the Lange coupler provide the specific phase shift. in the upper left corner of the chip, the transmitting/receiving ports are
In order to minimize phase error, we tune the value of the lumped in- located on the right side of the chip. The power port and the amplifier
ductors and capacitors and the length of the Lange coupler to get a are on the same side, the attenuator and phase shifter control port is
closer phase slope. Fig. 10 is the phase shifter circuit topology. Fig. 11 located on the lower left side of the chip.
shows the simulated 9 dB insert loss and 3° rms phase error.

Vector Network Analyzers

Probe

GSG-GSG Probe
GSG

GPIB

PC

SMU
Probe card
Power Supplier

Fig. 13. Core chip test block.

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M. Zhou et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 37–43

2.4 15 15
14

Tx_Output Power (dBm)

2.2
10 12

Tx_Power Gain(dB)
Input/Output VSWR

2.0 Input 10
5
1.8 8

1.6 0 6
38 GHz 4
1.4 -5 35 GHz
32 GHz 2
1.2
Output -10 0
1.0 -20 -15 -10 -5 0
32 33 34 35 36 37 38 Tx_Input Power (dBm)
Freq (GHz) Fig. 17. Tx output power & power gain.

Fig. 14. Input & output VSWR (all relative attenuation state.
10 12
2.4
10

Rx_Output Power (dBm)

5

Rx_Power Gain (dB)

2.2 8
Input/Output VSWR

2.0 Output 0 6

1.8 -5 4

1.6 2
38 GHz
-10 35 GHz
0
1.4 32 GHz

-15 -2
1.2
-20 -15 -10 -5 0
Input
1.0 Rx_Input Power (dBm)
32 33 34 35 36 37 38 Fig. 18. Rx output power & power gain.
Freq (GHz)
Fig. 15. Input & output VSWR (all relative phase shift state).
0 3.0

Attenuation RMS Error (dB)

15 -5 2.5
Attenuation (dB)

2.0
Tx Gain -10
1.5
10 -15
Rx Gain
1.0
Gain (dB)

-20 0.5
5 -25 0.0
32 33 34 35 36 37 38
Freq (GHz)

0 Fig. 19. All relative attenuation state & rms errors.

32 33 34 35 36 37 38
Freq (GHz) characteristic. The power and logic signals are provided through the on-
board programmable power supply and logic controller. These instru-
Fig. 16. Tx gain & Rx gain (reference state).
ments are all connected by GPIB interface for the automatic testing
program. Fig. 13 shows the test block diagram.
3. Measurement result We tested the sample under 25 °C. Figs. 14 and 15 show less than 2.2
of the input and output VSWR for all relative attenuation phase shift
For whole chip testing, a customized GSG-GSG RF probe and digital states. As showed in Fig. 16, the transmitting gain is greater than
probe are used. The complete electrical performance test can be done 11.5 dB and it is 9.0 dB over the 6 GHz bandwidth for receiving gain.
only with a vector network analyzer for both S-parameter and power Figs. 17 and 18 are the transmitting/receiving channel output power

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M. Zhou et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 37–43

20 20
5 1.0

Phase_RMS_vs_Freq (deg)

Attenuation RMS Error (dB)

Phase Shift (deg)

10 15

Attenuation Error (dB)

3

0 10 1
0.5
-10 5 -1

-3
-20 0
32 33 34 35 36 37 38 -5 0.0
Freq (GHz) 32 33 34 35 36 37 38
Fig. 20. Phase variation due to attenuator control & rms errors. Freq (GHz)
Fig. 22. Amplitude variation due to phase shifter control & rms errors.
0 10
-50

Phase Shift RMS Error (deg)

performance for all 32 states. The largest rms attenuation error is
-100 0.7 dB. In Fig. 20, the maximum rms phase error with 15.5 dB at-
Phase Shift (deg)

8
-150 tenuation range is depicted. Fig. 21 shows the excellent phase shifter
-200 characteristics with 3.8° rms error. Fig. 22 shows ± 0.6 dB amplitude
-250 6 variation due to 360° phase shifter control and 0.3 dB rms error.
-300 Finally, Table 1 shows the main measured performance of core chip.
-350 Table 2 summarizes the performance comparison of the Ka-band
4 core chips in this paper with other Ka-band core chips reported
-400
[11–13]. The measured results shows that the operating bandwidth,
-450
power consumption, gain, rms attenuation error and phase error have
-500 2
been significantly improved compared with the previous reports.
32 33 34 35 36 37 38
Freq (GHz)
4. Conclusions
Fig. 21. All relative phase shift state & rms errors.

The design and the fabrication of a wide band and low power
characteristics and rms error. From the power gain curves it can be consumption Ka-band core chip are successfully accomplished. With a
obtained that output P1dB are +0 dBm for transmitting channel and high level of functional integration, the MMIC is suitable for the Ka-
−3 dBm for receiving channel. Fig. 19 shows the attenuation band phased array application.

Table 1
Summary of core chip perfermance.
Parameter@32–38 GHz Min Typ Max Unit

Input & Output VSWR (All Attenuation State) 2.2 –

Input & Output VSWR (All Phase Shift State) 2.1 –
Tx Gain (Ref State) 11.5 dB
Rx Gain (Ref State) 9.0 dB
Tx P1dB (Ref State) 0 dBm
Rx P1dB (Ref State) –3 dBm
RMS Attenuation Error 0.6 0.7 dB
RMS Phase Variation with Amplitude Settings 2.5 4.3 °
RMS Phase Error 3 3.8 °
RMS Amplitude Variation with Phase Settings 0.3 dB
DC Power Consumption 0.15 W

Table 2
Performance comparison of Ka-band core chips.
Ref Device Tech Freq (GHz) Gain (dB) rms phase error (deg) rms att error (dB) Power consumption (mW)

[11] GaAs pHEMT 34–36 4.0(Tx), 4.8(Rx) <5 < 0.6 205
[12] SiGe BiCMOS 34–39 2(Tx), –1(Rx) < 12 < 0.9 171
[13] GaAs pHEMT 32–34 3(Tx) < 3.5 < 0.8 600
This work GaAs pHEMT 32–38 11.5(Tx), 9.0(Rx) < 3.8 < 0.7 150

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M. Zhou et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 37–43

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Min Zhou, received the Ph.D. degree from School of

Aeronautics and Astronautics, Zhejiang University,
Hangzhou, China in 2014. He joined the School of
Aeronautics and Astronautics, Zhejiang University, on
September 2014, as research assistant professor. His current
research interests include microwave, millimeter-wave cir-
cuits design and reliability, compound semiconductor de-
vice design and reliability.

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