ll,\ l \ ..

- CLK O
tH IN
'( )I l N'I 1m n AT I', O

H\ ti•FF I~
o _ ,. o UT O

~I-
F ......

VI -
t, P ~- M RF/\ 1)/ ;_, . - CL K I
\\' ~ "" rt1 ( 'OI JNTl'.I< UA'IE I
\
\\' I{ 1l'E ~ I
\ I OU lt' ~ ,,..-.- ~ l - --r- -~ OlJT l

-s- --
( , .-. .-- -,
('TRL.
CLK2
\\/ORD
GATE 2
REG
OU T2

Figure Arcltitecture of 8253/8254

,:hitecture:

e prog rammable timer device 8253 contains three independ

ent 16-b it
, each with a maximum count rate of 2.6Mhz. It is thus possible to gene
rate
cpendent delays or maintain three independent counters simultaneous
ly.
l!ee counters may he independently controlled by
programming the three
·ommand word registers.

1ta Bus Buffer): The 8-bit , bidirectional data bus buffer interfac
es internal
8253 to microprocessor system bus. Data is transmitted or received
by the
•n the execution of IN or OUT instruction.

(Re~d/Write Logic): Read/write logic controls the direction of the

data
inding upon whether it is a read or a write operation It ma b
. reads data whiie OUT instruction Writes
ion data to· ., __ _Y
. • e noted that
 in o . t)•1•2.· .I'
~ l) e r a tl o n . but th
h
e
e
y
th
a
re
rc
e
·
id
c o u n te rs a v ailable in sz 53
a r e .
in d c p e n d c n t r, f c--~...., .,
,-r e ~ a b l e i e n ti c a l to each other in o
, c o w n c rg ·
a n iz a ti. o n . T h
o u n te r s , a b le to e s e art: all\-, '' i
o p e ra te either in . a
C. oatt~l W ord c D o r ·
in h e x a d·cc im at- I, l"r,,
that can b e . e dRegister: The mode control word •
reg .
is te r c o n ta
u s for writin .
in s th e in fottt, ,
g o r re a d in g th Jue in to o r
e c o u n t va f r o m th
c rC1! ~
c o u n t register ~,.
U$ing the O U T a n d IN in structions.
Note-: T h e s p e c ia li ty o f the 8253
without dis tu
c o u n te rs is that the y c a n
rb in g th e clo c b e e a s il y r ead on .
k in p u t to the counter. T .
h is f a c il ty
ly~. reading o f c is c a ll e d as " u~ ,
oun ters.
1.8.3 Pin Description Of 8253/825 4:
D7 1 40 V ee
D6 2 39 WR
D5 3
38
-
RD
D4 4
37 cs
D3 5
36 Al
D2 6
8253 / 8254 35 AO
DI 7
34 CLK2
DO 8
CLKO 33 OCT2
9
ouro 10
32 GATE2
GATEO 31
lI CLK l
G\D 30
12 G.A.TE l
'"' Q
- ,J r\ 10 • .,. _
l I •
 1
,,,.,
, ;..,-, ·
• •
ed inte rna lly ror 8ddt ess ing
the ~u.i drc ss mp
~ , , , 111,, •·l t'<'
•
ut p111s and ure req utr ,
f l"'"~ '
~•
1 ,,,1 rd rl.·11isccrs nnd the thr ee cou nte r reg iste
. •CS ' tin e
~~
_,,,"if ' :. ~•~
rs. A low on
n.
tti<" ~- • •
Nl) opc rut ion wil l be pe rfo rm ed by
825 3 till it is ena ble d. Ta b e '
~ ~ 1 ...,..t~f c)p crn tion
for vnr iou s con tro l inp uts .
~--
,,,,... r • ~ '"'
Tab le Ba sic ope rat ion of 825 3/8 254

'
--- -
{""S RD
I
-WR
0
Al

0
AO Sel ect ed op era tio n
- I

tl 0 Write counter 0
1 0 0
I o 1 Write cou nte r 1
- 0 1 0 1 0 Write cou nte r 2
- -

-
0 1 0 I I Write con tro l wo rd
0 0 1 0 0 Re ad cou nte r 0
0 0 1 0 1 Re ad cou nte r 1
0 . 0 l 1 0 Re ad co un ter 2
0 0 l l 1 No op era tio n (tr ist ate d)
0 I 1 X X No op era tio n (tr ist ate d)
I X X X X Di sab led (tr ist ate d) •
I

A control wo rd reg ist er ac ce pts the

8-b it co ntr ol wo rd wr itt en by th e
nicroprocessor and sto res it for controlling
the con1plete op era tio n of the specific
>unter. It may be no ted tha t, the co ntr
ol word register can only be wdttcn
nnd
onot be read as it is obvious from Table.
The CLK, GATE. and ()\ rr pin s l\tT
ilable for each of the three timer ch an ne ls.
 " ~:\ - l - •ocon
~ ~.( j,·
+
}."'l;~' \ 't). ''\
'- "' ''' .\' ',,• \ \. '' ' \ \
""--
J N"OH1 ~l.U(I Fnn~
'~ ~"'••' it"t"' N'1 _a. . ,. . . . -'!i~.,_ _,,_ ti
_- o
-- --n-- -- - -- -- - -
• \~ .,, I •\ lli--d1
, , ,,~ \ \ : '~ ' \ .1
,,,nH1 C\1tod lP :sys
ru c ti
te
o
11
n
1
al
d
th re e s ta te data b
a ta b u s . Us ll ~
, '\ ( H'"- O : (" 'lo
\ t ~ \' ,, \ _,___.... ~. o k In p u t o f C ou t~ n
·,
~ )\ l'TP\ l' I' 0 .
' '·\ \ \' l
\,\ \ ' \
: O u tp u t o f C o unter o. ~
\
rl
, L·\ ~ (J
__ a te In p u t o f C o u nter 0. ~
\; ' I I I 1
1 \\ __..,--.
\RI )\JND : P o w er
\ :\ ' '
' \ \ 1
-, )\VBR : A SY. ----- S u pp ly Co nnection--.......,
\\ \ '
I
t
·" r -• -- ,
,
.,,
'
◄:
11
.WRITE coNT R
p
~
o
L
w e r su p ply co nnecti-;----,
. ; '\ \ : T h is inp u t is l o w ~
\\ '\ , cPU write op _er_a_u_ o_ n_ .-
=r= "''"-Rl - - - ---
l, P
~~~
. :~~~

I ,., I
i AD coN1'R
CPU rtlnd operttl
~ L
lo n
:T
.
h is inp ut is IOw during
K~ - -
Cl llP SELECT : A lo
l' ~ it \ w on th is in pu t enables
tilt' S25 4 to respo n d to R D an d W R signals.
JU) and W R nre ign o re d o th erwise.
A DDRFSS : Used
:\ t ~ r\ () I ! O· ,) I to s ele c t o ne of th e three
l'o11n1ers or the Con
tro l W ord R e gis te r for read