AI 302

Embedded Systems
SPRING 2023

Lecture 02 – Microcontroller
Instructor: Dr. Tarek Abdul Hamid
What is “Computer Architecture” ?

 Computer Architecture =
Instruction Set Architecture + Computer Organization
 Instruction Set Architecture (ISA)
 WHAT the computer does (logical view)

 Computer Organization
 HOW the ISA is implemented (physical view)

 In this course we will concentrate in the logical view.

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Some Important Questions to Ask

 What is Assembly Language?

 What is Machine Language?

 How is Assembly related to a high-level language?

 Why Learn Assembly Language?

 What is an Assembler, Linker, and Debugger?

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A Hierarchy of Languages
Application Programs

High-Level Languages
Machine independent High-Level Language
Machine specific Low-Level Language
Assembly Language

Machine Language

Hardware

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Assembly and Machine Language
 Machine language
 Native to a processor: executed directly by hardware
 Instructions consist of binary code: 1s and 0s

 Assembly language
 Slightly higher-level language
 Readability of instructions is better than machine language
 One-to-one correspondence with machine language instructions

 Assemblers translate assembly to machine code

 Compilers translate high-level programs to machine code

 Either directly, or
 Indirectly via an assembler

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Compiler and Assembler

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 Instructions and Machine Language

 Each command of a program is called an instruction (it instructs the

computer what to do).

 Computers only deal with binary data, hence the instructions must be
in binary format (0s and 1s).

 The set of all instructions (in binary form) makes up the computer's
machine language.This is also referred to as the instruction set.

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Instruction Fields

 Machine language instructions usually are made up of several fields. Each

field specifies different information for the computer. The major two fields
are:
 Opcode field which stands for operation code and it specifies the particular
operation that is to be performed.
 Each operation has its unique opcode.
 Operands fields which specify where to get the source and destination
operands for the operation specified by the opcode.
 The source/destination of operands can be a constant, the memory or
one of the general-purpose registers.

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Translating Languages
Program (C Language):
swap(int v[], int k) { A statement in a high-level
int temp; language is translated
temp = v[k]; typically into several
v[k] = v[k+1]; machine-level instructions
v[k+1] = temp;
}
Compiler
MIPS Assembly Language: MIPS Machine Language:
sll $2,$5, 2 00051080
Assembler
add $2,$4,$2 00821020
lw $15,0($2) 8C620000
lw $16,4($2) 8CF20004
sw $16,0($2) ACF20000
sw $15,4($2) AC620004
jr $31 03E00008
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Components of a Computer System
 Processor Computer
 Datapath
Memory
 Control
I/O Devices
 Memory & Storage
Control Input
 Main Memory B
Processor U Output
 Disk Storage S
Datapath Disk
 Input devices
 Output devices
Network
 Bus: Interconnects processor to memory and I/O
 Network: newly added component for communication

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Memory
 Ordered sequence of bytes
 The sequence number is called the memory address

 Byte addressable memory

 Each byte has a unique address
 Supported by almost all processors

 Physical address space

 Determined by the address bus width
 Pentium has a 32-bit address bus
 Physical address space = 4GB = 232 bytes

 Itanium with a 64-bit address bus can support

 Up to 264 bytes of physical address space

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Address Space

Address Space is
the set of memory
locations (bytes) that
can be addressed

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Address, Data, and Control Bus
 Address Bus
 Memory address is put on address bus
a
 If memory address = a bits then 2 locations are addressed
 Data Bus: bi-directional bus
 Data can be transferred in both directions on the data bus
 Control Bus
 Signals control Processor Memory
transfer of data Address Register
address bus
a bits 0
 Read request data bus
1
2
 Write request Data Register d bits 3

 Done transfer read

write ...
Bus Control
done a
2 –1

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Typical Memory Hierarchy
 Registers are at the top of the hierarchy
 Typical size < 1 KB
 Access time < 0.5 ns
Microprocessor
 Level 1 Cache (8 – 64 KB)
 Access time: 0.5 – 1 ns Registers

 L2 Cache (512KB – 8MB) L1 Cache

 Access time: 2 – 10 ns L2 Cache

Bigger
 Main Memory (1 – 2 GB) Faster Memory Bus
 Access time: 50 – 70 ns
Memory
 Disk Storage (> 200 GB)
I/O Bus
 Access time: milliseconds
Disk, Tape, etc

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Fetch - Execute Cycle
Fetch instruction
Infinite Cycle implemented in Hardware

Instruction Fetch
Compute address of next instruction

Generate control signals for instruction

Instruction Decode
Read operands from registers

Execute Compute result value

Memory Access Read or write memory (load/store)

Writeback Result Writeback result in a register

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 Microprocessors Building Blocks

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Microprocessor
Data
Cache
Memory
Bus Control Arithmetic
RAM Bus Unit & Logic
Interface Unit
I/O Unit
Instruction Registers
System Decoder
Bus
Floating
Point
Unit
Instruction
Cache Registers
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Bus Interface Unit

 Receives instructions & data from main memory

 Instructions are then sent to the instruction cache, data to the data
cache

 Also receives the processed data and sends it to the main memory

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Instruction Decoder

 This unit receives the programming instructions and decodes them into a
form that is understandable by the processing units, i.e. the ALU or FPU

 Then, it passes on the decoded instruction to the ALU or FPU

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Arithmetic & Logic Unit (ALU)
 Also known as the “Integer Unit”

 It performs whole-number math calculations (subtract, multiply, divide,

etc) comparisons (is greater than, is smaller than, etc.) and logical
operations (NOT, OR, AND, etc)

 The new breed of popular microprocessors have not one but two almost
identical ALU’s that can do calculations simultaneously, doubling the
capability

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Floating-Point Unit (FPU)
 Also known as the “Numeric Unit”

 It performs calculations that involve numbers represented in the

scientific notation (also known as floating-point numbers).

 This notation can represent extremely small and extremely large

numbers in a compact form

 Floating-point calculations are required for doing graphics, engineering

and scientific work

 The ALU can do these calculations as well, but will do them very slowly

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Registers
 Both ALU & FPU have a very small amount of super-fast private memory
placed right next to them for their exclusive use. These are called
registers

 The ALU & FPU store intermediate and final results from their
calculations in these registers

 Processed data goes back to the data cache and then to main memory
from these registers

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Control Unit

 The brain of the microprocessor

 Manages the whole microprocessor

 Tasks include fetching instructions & data, storing data, managing

input/output devices

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 That was the structure, now let’s
talk about the language of a
microprocessor

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Instruction Set

 The set of machine instructions that a microprocessor recognizes and can

execute – the only language microprocessor knows

 An instruction set includes low-level, a single step-at-a-time instructions,

such as add, subtract, multiply, and divide

 Each microprocessor family has its unique instruction set

 Bigger instruction-sets mean more complex chips (higher costs, reduced

efficiency), but shorter programs

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Instruction Set Architecture (ISA)

 Architecture is an interface between layers

 ISA is the interface between hardware and software
 ISA is what is visible to the programmer (and ISA might be different
for O.S. and applications)
 ISA consists of:
 instructions (operations and how they are encoded)
 information units (size, how they are addressed etc.)
 registers (or more generally processor state)
 input-output control

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Some Computer families

 Computers that have the same (or very similar) ISA

 Compatibility of software between various implementations
 IBM
 704, 709, 70xx etc.. From 1955 till 1965
 360, 370, 43xx, 33xx From 1965 to the present
 Power PC
 DEC
 PDP-11, VAX From 1970 till 1985
 Alpha (now Compaq, now HP) in 1990’s

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More computer families

 Intel
 Early micros 40xx in early 70’s
 x86 (086,…,486, Pentium, Pentium Pro, Pentium 3, Pentium 4) from
1980 on
 IA-64 (Itanium) in 2001
 SUN
 Sparc, Ultra Sparc 1985 0n
 MIPS-SGI
 Mips 2000, 3000, 4400, 10000 from 1985 on

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Information units

 Basic unit is the bit (has value 0 or 1)

 Bits are grouped together in information units:
 Byte = 8 bits
 Word = 4 bytes
 Double word = 2 words
 etc.

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Addressing words
 Although machines are byte-addressable, words are the most commonly
used I-units
 Every word starts at an address divisible by 4

Word at address 0
Word at address 4

Word at address 8

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Programmer’s View of a Computer
System

Application Programs
Level 5
Increased level
High-Level Language
of abstraction
Software Assembly Language Level 4

Operating System
Level 3

Interface Instruction Set

SW & HW Architecture Level 2

Microarchitecture Level 1 Each level hides

Hardware the details of the
Physical Design level below it
Level 0

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Programmer's View – 2
 Application Programs (Level 5)
 Written in high-level programming languages
 Such as Java, C++, Pascal, Visual Basic . . .
 Programs compile into assembly language level (Level 4)
 Assembly Language (Level 4)
 Instruction mnemonics are used
 Have one-to-one correspondence to machine language
 Calls functions written at the operating system level (Level 3)
 Programs are translated into machine language (Level 2)
 Operating System (Level 3)
 Provides services to level 4 and 5 programs
 Translated to run at the machine instruction level (Level 2)
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Programmer's View – 3
 Instruction Set Architecture (Level 2)
 Interface between software and hardware
 Specifies how a processor functions
 Machine instructions, registers, and memory are exposed
 Machine language is executed by Level 1 (microarchitecture)

 Microarchitecture (Level 1)
 Controls the execution of machine instructions (Level 2)
 Implemented by digital logic

 Physical Design (Level 0)

 Implements the microarchitecture
 Physical layout of circuits on a chip

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Microprocessor Vs Microcontroller
Microprocessor
 Collection of on/off SWI on Silicon
for computations
 CPU is stand-alone, RAM, ROM, I/O,
timer are separate
 designer can decide on the amount of
ROM, RAM and I/O ports.
 Expandable
 Expensive
 High Speed (1000 MIPS)
 General purpose and Versatile
 Large Architecture (32b, 64b)
 Lots of IO and Peripherals externally
connected
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Microcontroller
 Small and self-suffice SoC to control
devices
 CPU, RAM, ROM, I/O and timer are
all on a single chip
 fix amount of on-chip ROM, RAM,
I/O ports
 Not Expandable – no external bus
interface
 for applications in which cost, power
and space are critical
 Low speed, on the order of 10 KHz –
20 MHz
 single-purpose
 Small usually an 8b
 Limited IO, enough for intended app
Dr. Tarek Abdul Hamid
Microcontroller
 Device
 Integrates # of components of microprocessor system on to a single microchip
 Optimized to interact with ext world through on-board interfaces
 i.e. it is a little gadget that houses a microprocessor, ROM (Read Only Memory),
RAM (Random Access Memory), I/O (Input Output functions), and various other
specialized circuits all in one package.

 Microprocessor
 Optimised to coordinate flow of information b/w separate memory and
peripheral devices located outside itself
 System bus (AB / DB / CB) - up uses to select the peripheral for sx/rx data

 Microcontroller
 Processor and peripherals on single silicon
 Self-contained device – rarely bus structures extend outside package

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Microprocessor Vs Microcontroller
Microprocessor
 Collection of on/off SWI on Silicon
for computations
 CPU is stand-alone, RAM, ROM, I/O,
timer are separate
 designer can decide on the amount of
ROM, RAM and I/O ports.
 Expandable
 Expensive
 High Speed (1000 MIPS)
 General purpose and Versatile
 Large Architecture (32b, 64b)
 Lots of IO and Peripherals externally
connected
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Microcontroller
 Small and self-suffice SoC to control
devices
 CPU, RAM, ROM, I/O and timer are
all on a single chip
 fix amount of on-chip ROM, RAM,
I/O ports
 Not Expandable – no external bus
interface
 for applications in which cost, power
and space are critical
 Low speed, on the order of 10 KHz –
20 MHz
 single-purpose
 Small usually an 8b
 Limited IO, enough for intended app
Dr. Tarek Abdul Hamid