CMOS

Digital Integrated
Circuits
Analysis and Design

Chapter 3
MOS Transistor

1
The Metal Oxide Semiconductor (MOS) structure

• The structure consists of three • The basic properties of the

layer semiconductor
– The metal gate electrode The mass action law:n ⋅ p = ni2
– The insulating oxide (SiO2) Assume the substrate doping concentration N A
layer
ni2
– The p-type bulk then pn 0 ≅ , p p0 ≅ N A
semiconductor NA

2
Energy band diagram of a p-type silicon substrate

EF -Ei
The Fermi potential φF =
q
kT n
For a p-type semiconductor, φFp = ln i
q NA
kT N D
For a n-type semiconductor, φFn = ln
q ni
The energy required for an electron to move from the
Fermi level int o free space is called the work function
qφs = qχ + (Ec -EF ) 3
Energy diagram of the combined MOS system

• The equilibrium Fermi levels of the semiconductor (Si) substrate

and the metal gate are at the same potential
• The bulk Fermi level is not significantly affected by the bending
• The surface Fermi level moves closer to the intrinsic Fermi level

4
Example 1

5
The MOS System under External Bias - accumulation

• A negative voltage VG is applied to the gate electrode.

– The holes in the p-type substrate are attracted to the semiconductor-
oxide surface
– The majority carrier concentration > the equilibrium hole concentration
• The electron concentration (minority carrier) decreases as the negatively
charged electron are pushed deeper into the substrate
– The oxide electric field is directed towards the gate electrode
– Causing the energy bands bend up-ward near the surface

6
The MOS System under External Bias – depletion
• A small positive gate bias VG is applied to the gate
electrode
– The oxide electric field will be directed towards the substrate
– Causing the energy bands to bend downward near the surface
– The majority carrier (hole) will be repelled backed into the
substrate
• Leaving negatively charged fixed acceptor ions behind (depletion
region)
dQ = − q ⋅ N A ⋅ dx
dQ q ⋅ N A ⋅ x
dφ s = − x ⋅ = dx
dx ε Si
φs xd q⋅ NA ⋅ x
∫φ F
dφ s = ∫
0 ε Si
dx

q ⋅ N A ⋅ xd2
φs − φF =
ε Si
2ε Si ⋅ φs − φF
xd =
q⋅ NA
Q = − q ⋅ N A ⋅ xd = − 2q ⋅ N A ⋅ ε Si ⋅ φs − φ F

7
The MOS System under External Bias – inversion
• A further increase in the positive gate bias
– Increasing surface potential Bthe downward bending of the energy bands will increase
– The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface
• The substrate semiconductor in this region become n-type
• The electron density is larger than the majority hole density
• Inversion layer, surface inversion
• Can be utilized for conducting current between two terminal of the MOS transistor
– The surface is said to be inverted
• The density of mobile electrons on the surface becomes equal to the density of holes in the bulk
substrate
• Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi
potential φF
• Further increase gate voltage B electron concentration↑ B but not to an increase of the depletion
depth

2 ⋅ ε Si ⋅ 2φF
xdm =
q⋅ NA

8
The physical structure of a n-channel
enhancement-type MOSFET

• MOS structure
– polysilicon gate, thin oxide layer, semiconductor
• Source, drain n+-region
– The current conducting terminals of the device
• Conducting channel, channel length L, channel width W
– The device structure is completely symmetrical with respect to the drain and source
• The simple operation of this device
– Controlling the current conduction between the source and the drain, using the electric field
generated by the gate voltage as a control variable

9
Circuit symbols for enhancement-type MOSFET

• Enhancement-mode MOSFET
– No conducting region at zero gate bias
• Depletion-mode MOSFET
– A conducting channel already exists at zero gate bias
• The abbreviations used for device terminals are
– G for the gate, D for the drain, S for the source, and B for the substrate
• The small arrow always marks the source terminal

10
Formation of a depletion region
• For small gate voltage level
– The majority carriers (holes) are repelled back into
the substrate
– The surface of the p-type substrate is depleted
– Current conduction between S and D is not possible

11
Formation of an inversion layer

• As the gate-to-source voltage is further increased

– The surface potential reaches -φFp B surface inversion will be established B conducting
channel between S and D
– Allowing current flow, as log as there is a potential difference between S and D
– VGS<VT0 (threshold voltage)
• Not sufficient to establish an inversion layer
• No current between S and D
– VGS>VT0 (threshold voltage)
• Electrons are attracted to the surface
– Contributing to channel current conduction
– Further increase gate voltage
• Not affect the surface potential and the depletion region depth

12
The threshold voltage
• Four physical components of VT0 • Compared with the p-MOSFET
– The work function difference between – The substrate Fermi potential φF is
gate and the channel negative in NMOS, positive in
• φGC= φF(substrate)- φM for metal gate
• φGC= φF(substrate)- φF(gate) for
pMOS
polysilicon gate – The depletion region charge
– The gate voltage component to change densities QB0 and QB are negative
the surface potential in nMOS, positive in pMOS
• To change the surface potential by -2φF – The substrate bias coefficient γ is
– The gate voltage component to offset positive in nMOS, negative in
the depletion region charge pMOS
• -QB/Cox
•
QB = − 2q ⋅ N A ⋅ ε Si ⋅ − 2φ F + VSB
– The substrate bias voltage VSB is
positive in nMOS, negative in
ε ox
Cox =
tox
pMOS
– The voltage component to offset the
fixed charge in the gate oxide and in • Threshold voltage adjustment
the silicon-oxide interface – Implanting p-type impurity B VT
• -Qox/Cox increased
• V = Φ − 2φ − QB 0 − Qox (no body effect)
T0 GC F
Cox Cox – Implanting n-type impurity B VT
VT = VT 0 + γ ⋅ ( )
− 2φ F + VSB − 2φ F (with body effect)
decreased
– The amount of change in the
2q ⋅ N A ⋅ ε Si threshold voltage
where γ =
Cox • Shift qNI/Cox

13
Example 2

14
Circuit symbols for n-channel depletion-type MOSFETs
• Using selective ion implantation into the channel
– The threshold voltage for nMOSFET can be made
negative
– Having a conducting channel at VGS=0

15
Example 3

16
MOSFET operation: linear region
• The MOSFET consists
– A MOS capacitor, two pn junction adjacent to the channel
– The channel is controlled to the MOS gate
• The carrier (electron in nMOSFET)
– Entering through source, controlling by gate, leaving through drain
• To ensure that both p-n junctions are reverse-biased initially
– The substrate potential is kept lower than the other three terminal potentials
• When 0<VGS<VT0
– G-S region depleted, G-D region depleted
– No current flow
• When VGS>VT0
– Conduction channel formed
– Capable of carrying the drain current
– As VDS=0
• ID=0
– As VDS>0 and small
• ID proportional to VDS
• Flowing from S to D through the conducting channel
• The channel act as a voltage controlled resistor
• The electron velocity much lower than the drift velocity limit
• As VDS↑Bthe inversion layer charge and the channel depth at the drain end start to
decrease

17
MOSFET operation: saturation region
• For VDS=VDSAT
– The inversion charge at the drain is
reduced to zero
– Pitch off point
• For VDS>VDSAT
– A depleted surface region forms
adjacent to the drain
– As further increases VDS B this
depletion region grows toward the
source
– The channel-end remains essentially
constant and equal to VDSAT
– The pitch-off (depleted) section
• Absorbing most of the excess voltage
drop, VDS-VDSAT
• A high-field forms between the
channel-end of the drain boundary
– Accelerating electrons, usually
reaching the drift velocity limit

18
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(1)
• Considering linear mode operation
– VS=VB=0, the VGS and VDS are the external parameters controlling the drain
current ID
– VGS > VT0 (assume constant through the channel) to create a conducting inversion layer
– Defining
• X-direction: perpendicular to the surface, pointing down into the substrate
• Y-direction: parallel to the surface
– The y=0 is at the source end of the channel
– Channel voltage with respect to the source, Vc(y)
– Assume the electric field Ey is dominant compared with Ex
• This assumption reduced Bthe current flow in the channel to the y-direction only
– Let QI(y) be the total mobile electron charge in the surface inversion layer
• QI(y)=-Cox[VGS-Vc(y)-VT0]

19
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(2)
Assumeing that all mobile electrons in the inversion layer has a constant surfacr mobility μn
dy
dR = − (mimus sign is due to the negative polarity of the inversion layer charge QI )
W ⋅ μn ⋅ QI (y)
The electron surface mobility μn dependents on the doping concentration of the channel region,
and its magnitude is typically about one - half of that of the bulk electron mobility
ID
dVC = I D ⋅ dR = - ⋅ dy
W ⋅ μn ⋅ QI (y)
L VDS
∫
0
I D ⋅ dy = − W ⋅ μ n ∫
0
QI ( y ) ⋅ dVC

(VGS − VC − VT 0 ) ⋅ dVC
VDS
I D ⋅ L = W ⋅ μ n ⋅ Cox ∫
0

μ n ⋅ Cox W
ID =
2 L
⋅ [
⋅ 2 ⋅ (VGS − VT 0 )VDS − VDS
2
]
[ ]
'
k W
I D = ⋅ ⋅ 2 ⋅ (VGS − VT 0 )VDS − VDS2
where k ' = μnCox
2 L
k
[
I D = ⋅ 2 ⋅ (VGS − VT 0 )VDS − VDS
2
2
where k = k ' ⋅]W
L

20
Example 4

21
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)-saturation region

• For VDS≥VDSAT=VGS-VT0
[ ]
– μ n ⋅ Cox W
⋅ 2 ⋅ (VGS − VT 0 )⋅ (VGS − VT 0 ) − (VGS − VT 0 )
2
I D ( sat ) = ⋅
2 L
μ ⋅C W
⋅ ⋅ (VGS − VT 0 )
2
= n ox
2 L
– The drain current becomes a function only of VGS, beyond the saturation
boundary

22
 Channel length modulation
The inversion layer charge at the source end of the channel is
QI (y = 0 ) = -Cox ⋅ (VGS -VT 0 )
and the inversion layer charge at the drain end of the channel is
QI (y = L) = -Cox ⋅ (VGS -VT 0 − VDS )
Note that at the edge of saturation , VDS = VDSAT = VGS -VT 0
The inversion layer charge at the drain end become very small
QI (y = L) ≈ 0
The effective channel length L' = L-Δ-
where ΔΔ is the length of the channel segment wi th QI = 0
μn Cox W
⋅ ' ⋅ (VGS − VT 0 )
2
I D(sat) =
2 L
⎛ ⎞
⎜ 1 ⎟μC W
I D(sat) =⎜ ⎟ n ox ⋅ ' ⋅ (VGS − VT 0 )2
⎜ 1 − ΔL ⎟ 2 L
⎜ ⎟
⎝ L ⎠
ΔL ∝ VDS − VDSAT
ΔL
We use 1 − ≈ 1 − λ ⋅ VDS , λ channel length modulation coefficient
L
Assuming that λλ DS << 1
μn ⋅ Cox W
⋅ ⋅ (VGS − VT 0 ) ⋅ (1 + λVDS )
2
I D(sat) =
2 L

23
Substrate bias effect
• The discussion in the previous has been done under the assumption
– The substrate potential is equal to the source potential, i.e. VSB=0
• On the other hand
– the source potential of an nMOS transistor can be larger than the substrate
potential, i.e. VSB>0
(
– VT (VSB ) = VT 0 + γ ⋅ 2φF + VSB − 2φF )
μ n ⋅ Cox W
I D (lin ) =
2
⋅
L
[
⋅ 2 ⋅ (VGS − VT (VSB ) )VDS − VDS
2
]
μ ⋅C W
⋅ ⋅ (VGS − VT (VSB ) ) ⋅ (1 + λ ⋅ VDS )
2
I D ( sat ) = n ox
2 L

24
Current-voltage equation of n-, p-channel MOSFET

For n - channel MOSFET

I D = 0, for VGS < VT
μ n ⋅ Cox W
I D ( lin ) =
2
⋅
L
[
⋅ 2 ⋅ (VGS − VT )VDS − VDS
2
]for VGS ≥ VT

and VDS < VGS -VT

μ n ⋅ Cox W
⋅ (VGS − VT ) ⋅ (1 + λ ⋅VDS ) for VGS ≥ VT
2
I D ( sat ) = ⋅
2 L
and VDS ≥ VGS -VT
For p - channel MOSFET
I D = 0, for VGS > VT
μ n ⋅ Cox W
I D ( lin ) =
2
⋅
L
[
⋅ 2 ⋅ (VGS − VT )VDS − VDS
2
]for VGS ≤ VT

and VDS > VGS -VT

μ n ⋅ Cox W
⋅ (VGS − VT ) ⋅ (1 + λ ⋅VDS ) for VGS ≤ VT
2
I D ( sat ) = ⋅
2 L
and VDS ≤ VGS -VT
25
Measurement of parameters- kn, VT0, and γ
• The VSB is set at a constant value
– The drain current is measured for different values of VGS
– VDG=0
• VDS>VGS-VT is always satisfied B saturation mode
• Neglecting the channel length modulation effect
– kn kn
⋅ (V GS − V T 0 ) , I D = ⋅ (V GS − V T 0 )
2
I D ( sat ) =
2 2
– Obtaining the parameters kn, VT0, and γ
– VT (VSB ) − VT 0
γ=
2φF + VSB − 2φF

26
Measurement of parameters- λ
• The voltage VGS is set to VT0+1
• The voltage VDS is chosen sufficiently large (VDS>VGS-VT0) that the transistor
operates in the saturation mode, VDS1, VDS2
– ID(sat)-(kn/2)(VGS-VT0)2(1+λVDS)
• Since VGS=VT0+1BID2/ID1=(1+λVDS2)/ (1+λVDS1)
• Which can be used to calculate the channel length modulation coefficient λ
• This is in fact equivalent to calculating the slope of the drain current versus drain
voltage curve in the saturation region
– The slope is λkn/2

27
Example 5

28
MOSFET scaling and small-geometry effects
• High density chip
– The sizes of the transistors are as small as possible
– The operational characteristics of MOS transistor will change with the reduction of iys
dimensions
• There are two basic types of size-reduction strategies
– Full scaling (constant-field scaling)
– Constant-voltage scaling
• A new generation of manufacturing technology replaces the previous one about
– every two or three years
– The down-scaling factor S about 1.2 to1.5
• The scaling of all dimensions by a factor of S>1 leads to the reduction of the area
occupied by the transistor by a factor of S2

29
 Full scaling (constant-field scaling)
To achieve this goal, all potentials must be scaled down proportionally, by the same scaling factor
Assuming the surface mobility μn is not significantly affected by the scaled doping density
The gate oxide capacitance per unit area
ε ox ε ox
C 'ox = '
=S⋅ = S ⋅ Cox
t ox tox
The aspect ratio W/L unchanged ⇒ the k n will also scaled by a factor of S
The linear mode drain current
'
D
k n'
I (lin) = ⋅ 2 ⋅ VGS
2
[ (
'
− VT' ⋅ VDS
'
− VDS
'2
) ]
=
S ⋅ kn 1
2 S
[ (
⋅ 2 ⋅ 2 ⋅ VGS − VT ⋅ VDS − VDS
2
)
=
I D(lin)
S
]
The saturation mode drain current
S ⋅ kn 1 I D(sat)
k n'
I D' (sat) =
2
⋅ VGS
'
(
− VT' )2
=
2 S2
(
⋅ ⋅ VGS − VT )
2
=
S
The power dissipation
1 P
P' = I D' ⋅VDS
'
=2
⋅ I D ⋅VDS = 2
S S
The significant reduction of the power dissipation is one of the most attractive features of full scaling
The power density per unit area remaining virtually unchanged
C g is scaled down by a factor of S ⇒ the charge - up, and charge - down time improved
A reduction of various parasitic capacitances abd resistances

30
 Constant-voltage scaling
All dimensions of the MOSFETare reduced by a factor of S .
The power supply voltage and the terminal voltages remained unchanged.
The doping densities must be increased by a factor of S 2 in order to preserve the charge - field relations
The gate oxide capacitance per unit area Cox is increased by a factor of S
⇒ The transconductance parameter is also increased by S
The linear mode drain current
'
D
k n'
I (lin) = ⋅ 2 ⋅ VGS
2
[ ( '
)
− VT' ⋅ VDS
'
]
− VDS
'2

=
S ⋅ kn
2
[
⋅ 2 ⋅ (VGS − VT ) ⋅VDS − VDS
2
]= S ⋅ I D(lin)

The saturation mode drain current

S ⋅ kn
I (sat) =
'
D
2
(
k n' ' 2
VGS − VT' = )
2
⋅ (VGS − VT ) = S ⋅ I D(sat)
2

The drain current density increased by a factor of S 3

The power dissipation
P' = I D' ⋅VDS
'
= (S ⋅ I D ) ⋅VDS = S ⋅ P
The power density incresaed by a factor of S 3
To summarized, constant - voltage scaling may be preferred over full scaling in mamy practical cases
because of the external voltage - level constraints.
Disadv. ⇒ increasing current density, power density
⇒ electromigration, hot carrier degradation, oxide breakdown, and electrical over - stress
31
Short-channel effects
• A MOS transistor is called a short-channel device
– If its channel length is on the same order of magnitude as the
depletion region thickness of the S and D junction
– The effective channel length Leff ≈ S, D junction depth xj
– Two physical phenomena arise from short-channel effects
• The limitations imposed on electron drift characteristics in the
channel
– The lateral electric field Ey increased, vd reached saturation velocity
L
d ( sat ) ∫
– I = W ⋅ v ⋅
eff
q ⋅ n( x) ⋅ dx = W ⋅ vd ( sat ) ⋅ QI = W ⋅ vd ( sat ) ⋅ Cox ⋅ VDSAT
D ( sat )
0

» No longer a quadratic function of VGS, virtually independent of the

channel length
– The carrier velocity in the channel also a function of Ex
» Influence the scattering of carriers in the surface
» μ (eff ) = μ no = μ no
=
μ no
⋅ (VGS − Vc ( y ) ) 1 + η ⋅ (VGS − VT )
n
1 + Θ ⋅ Ex Θε ox
1+
toxε Si
• The modification of the threshold voltage due to the shortening
channel length

32
Short-channel effects-modification of VT
• The n+ drain and source diffusion regions in p-type substrate induce a
significant amount of depletion charge
– The long channel VT, overetimates the depletion charge support by the gate
voltage
– The bulk depletion region B asymmetric trapezoidal shape
• A significant portion of the total depletion region charge is due the S and D junction
depletion
VT 0(short channel) = VT0 - ΔVT0
⎛ ΔL + ΔLD ⎞
QB 0 = −⎜1 − S ⎟ ⋅ 2 ⋅ q ⋅ εSi ⋅ N A ⋅ 2φF
⎝ 2L ⎠
2 ⋅ εSi 2 ⋅ εSi kT ⎛ N D ⋅ N A ⎞
xdS = ⋅ φ0 , xdD = ⋅ (φ0 + VDS ), φ0 = ⋅ ln⎜⎜ ⎟⎟
q⋅ NA q ⋅ NA q ⎝ ni
2
⎠
(x j + xdD ) = xdm
2 2
+ (x j + ΔLD )
2

ΔL2D + 2 ⋅ x j ⋅ ΔLD + xdm

2
− xdD
2
− 2 ⋅ x j ⋅ xdD = 0
⎛ ⎞
ΔLD = − x j + x 2j − xdm (2
− xdD
2
) ⎜
2x
+ 2 x j xdD ≅ x j ⋅ ⎜ 1 + dD − 1⎟
xj ⎟
⎝ ⎠
⎛ 2x ⎞
ΔLS ≅ x j ⋅ ⎜ 1 + dS − 1⎟
⎜ xj ⎟
⎝ ⎠
1 x j ⎡⎛⎜ 2x ⎞ ⎛ 2x ⎞⎤
ΔVT 0 = ⋅ 2 ⋅ q ⋅ ε Si ⋅ N A ⋅ 2φF ⋅ ⋅ ⎢ 1 + dD − 1⎟ + ⎜ 1 + dS − 1⎟⎥
Cox 2 L ⎢⎜⎝ xj ⎟ ⎜
⎠ ⎝ xj ⎟⎥
⎠⎦
⎣
33
Example 6 (1)

34
Example 6 (2)

35
Example 6 (3)

36
Narrow-channel effect
• Channel width W on the same
order of magnitude as the
maximum depletion region
thickness xdm
• The actual threshold voltage of
such device is larger than that
predicted by the conventional
threshold voltage
• Fringe depletion region under
field oxide
– V (narrow channel) = V + ΔV
T0 T0 T0

1 κ ⋅ xdm
ΔVT0 = ⋅ 2qε Si N A 2φF ⋅
Cox W
π
κ= for depletion region modeled by quarter - circular arcs
2

37
Other limitations imposed by small-device geometries
• The current flow in the channel are controlled by two dimensional electric field vector
• Subthreshold conduction
– Drain-induced barrier lowering (DIBL)
– A nonzero drain current ID for VGS<VT0
– qφ q
qDnWxc n0 kTr kT ( A⋅VGS + B⋅VDS )
I D ( subthreshold ) ≅ ⋅e ⋅e
LB
• Punch-through
– The gate voltage loses its control upon the drain current, and the current rises sharply
• Gate oxide thickness tox scaled to tox/S, is restricted by processing difficulties
– Pinholes, oxide breakdown
• Hot-carrier effect

38
MOSFET capacitances
• L=LM-2LD
– L: the actual channel length
– LM: the mask length of the
gate
– LD: the gate-drain, the gate-
source overlap
• On the order of 0.1μm

39
Oxide related capacitance(1)
• The gate electrode overlap
capacitance
– CGD(overlap)=CoxWLD
– CGS(overlap)=CoxWLD
• With Cox=εox/tox
– Both capacitance do not depend
on the bias condition, they are
voltage-independent
• The capacitances result from the
interaction between the gate
voltage and the channel charge
– Cut-off mode
• Cgs=Cgd=0
• Cgb=CoxWL
– Linear mode
• Cgb=0
• Cgs≅Cgd ≅(1/2) CoxWL
– Saturation mode
• Cgb= Cgd =0
• Cgs≅ (2/3) CoxWL 40
Oxide related capacitance(2)
• The sum of all three voltage-dependent (distributed) gate oxide
capacitances (Cgb+Cgs+Cgd)
– A minimum value of 0.66CoxWL, in saturation mode
– A maximum value of CoxWL, in cut off and linear modes
– For simple hand calculation
• The three capacitances can be considered to be in parallel
• A constant worst-case value of CoxW(L+2LD) can be used for the sum of
MOSFET gate oxide capacitances

41
 Junction capacitance(1)

2 ⋅ ε Si N A + N D
The depletion region thickness xd = ⋅ (φ0 − V )
q N A ⋅ ND
kT ⎛ N A ⋅ N D ⎞
The built - in potential φ0 = ⋅ ln⎜⎜ 2
⎟⎟
q ⎝ ni ⎠
⎛ N ⋅N ⎞ N ⋅N
The depletion region charge Q j = A ⋅ q ⋅ ⎜⎜ A D ⎟⎟ ⋅ xd = A 2 ⋅ εSi ⋅ q ⋅ A D (φ0 − V )
⎝ N A + ND ⎠ N A + ND
dQ j ε Si ⋅ q ⎛ N A ⋅ N D ⎞ 1
The junction capacitance C j = = A⋅ ⋅ ⎜⎜ ⎟⎟ ⋅
dV 2 ⎝ N A + N D ⎠ φ0 − V
AC j 0
C j(V) = m
, the parameter m is grading coefficient
⎛ V ⎞
⎜⎜1 − ⎟⎟
⎝ φ0 ⎠
ε Si ⋅ q ⎛ N A ⋅ N D ⎞ 1
The zero bias junction capacitance per unit area C j 0 = ⋅⎜ ⎟⋅
2 ⎜⎝ N A + N D ⎟⎠ φ0
The equivalent large - signal capacitance can be defined as
ΔQ Q j(V2 ) −Q j (V1 ) 1 V2
Ceq =
ΔV
=
V2 − V1
= ∫
V2 − V1 V1
C j(V)dV

A ⋅ C j 0 ⋅ φ0 ⎡⎛ V ⎞1− m ⎛ V ⎞1− m ⎤
=− ⋅ ⎢⎜1 − 2 ⎟ − ⎜⎜1 − 1 ⎟⎟ ⎥
(V2 − V ) ⋅ (1 − m ) ⎢⎣⎜⎝ φ0 ⎟⎠ ⎝ φ0 ⎠ ⎥⎦
For the special case of abrupt pn - junctions
2 ⋅ A ⋅ C j 0 ⋅ φ0 ⎡ V V ⎤
Ceq = − ⋅ ⎢ 1− 2 − 1− 1 ⎥
(V2 − V ) ⎣ φ0 φ0 ⎦
Ceq = A ⋅ C j 0 ⋅ K eq

K eq = −
2 φ0
V2 − V1
(
⋅ φ0 − V2 − φ0 − V1 ) 42
Example 7

43
Junction capacitance(2)
The sidewalls of a typical MOSFET source or drain diffusion region
are surrounded by a p + channel - stop implant, with a higher doping density
than the substrate doping density N A
Assume the sidewall doping density is given by N A(sw) ,
the zero - bias capacitance per unit area can be found as

ε Si ⋅ q ⎛⎜ N A(sw) ⋅ N D ⎞⎟ 1
C j 0 sw = ⋅ ⋅
⎜ ⎟
2 ⎝ N A(sw) + N D ⎠ φ0 sw
C jsw = C j 0 sw ⋅ x j
The sidewall voltage equivalence factor

K eq ( sw) = −
2 φ0 sw
V2 − V1
(
⋅ φ0 sw − V2 − φ0 sw − V1 )
The equivalent large - signal junction capacitance Ceq(sw) for
a sidewall of length (perimeter) P can be
Ceq(sw) = P ⋅ C jsw ⋅ K eq(sw)
44
Example 8 (1)

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Example 8 (2)

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