Chapter 8 Logic Families and Semiconductor Memories

8.1 Practical TTL Logic Gates

Digital IC families
TTL (Transistor-Transistor Logic)
CMOS (Complementary Metal Oxide Semiconductor)
• Advantage: very low power consumption
• Disadvantage: easy to break

A popular type of IC
DIP (Dual In-line package) SOP (Small Out-line package)

Fig. 8-1 (a) (b) (c)

Pin diagram for Quad [Quadruple] 2-input TTL AND gate 7408

1A 1 14 VCC +5V
1B 2 13 4B

1Y 3 12 4A

2A 4 11 4Y
2B 5 10 3B

2Y 6 9 3A

0V GND 7 8 3Y

Fig. 8-2

- 1-
Wire diagram to implement the two-input AND function

1 1A V CC 14
OUTPUT
2 1B
+ A INPUTS B 3 1Y

(7408) LED

7 GND
150Ω

Fig. 8-3

Marking on a typical digital IC

14 13 12 11 10 9 8
4 4 4 4 4

DM7408N

1 2 3 4 5 6 7
Fig. 8-4

Decoding the part number on a typical IC

Core part number

DM 74 08 N

Manufacturer’s Manufacture’s code

code for dual-in-line
7400 series package
(commercial grade)
Function of digital IC
Manufacturer’s code Function of digital IC
DM National Semiconductor 08 AND
F Fairchild 32 OR
CD RCA 00 NAND
SN Texas Instruments 02 NOR
TC Toshiba Semiconductor 86 XOR
HD Renesas Electronics 04 NOT

- 2-
Marking on a Renesas Electronics digital IC
14 13 12 11 10 9 8
4 4 4 4 4

HD74LS08P

1 2 3 4 5 6 7
Fig. 8-5

Decoding the part number on a typical IC

Core part number

HD 74 LS 08 P

Manufacturer’s
code Plastic dual-in-line
7400 series package
(commercial grade)
Function of digital IC
Low power
Schottky type

Typical internal letters

ALS = advanced low-power Schottky TTL logic
AS = advanced Schottky TTL logic
H = high-speed TTL logic
L = low-power TTL logic a subfamily of TTL
LS = low-power Schottky TTL logic
S = Schottky TTL logic
C = CMOS logic an early family of CMOS
HC = high-speed CMOS logic a family of CMOS
HCT = high-speed CMOS logic a family of CMOS with TTL inputs

8.2 Practical CMOS Logic Gates

Caution for CMOS Logic Gates
• Do not touch the pins when inserting the CMOS IC in a socket or mounting board.
• When using CMOS, all unused inputs are tied to GND or V DD.

- 3-
Pin diagram for Quad [Quadruple] 2-input CMOS AND gate 4081

A 1 14 V DD positive voltage

B 2 13 H VDD = 3 8V
J 3 12 G

K 4 11 M

C 5 10 L

D 6 9 F

GND or VSS 7 8 E

negative voltage
Fig. 8-6
Wire diagram using the 4081 CMOS IC to implement the two-input AND function

150 
1 A VDD 14

2 B H 13
LED
+ A INPUTS B 3 J G 12

CMOS
(4081)
5 C
10k
6 D F 9
Q1
7 V SS E 8
2N3904

Fig. 8-7

Marking on a Toshiba Semiconductor digital IC

14 13 12 11 10 9 8
4 4 4 4 4

TC4081BP

1 2 3 4 5 6 7
Fig. 8-8

Decoding the part number on a typical IC

Core part number

TC 40 81 B P
Plastic dual-in-line
Manufacturer’s package
code
4000 CMOS series Buffered version
of 4000 series

Function of digital IC - 4 -
Function of digital IC
81 AND 01 NOR
71 OR 70 XOR
11 NAND 77 XNOR

8.3 Logic Levels and Noise Margin

• Integrated circuits within a logic family are design to interface easily with one another.
• The design of interconnections between two circuits to make them compatible is called
interfacing.

Logic Levels
Logic 0 (LOW) → 0 V Logic 1 (HIGH) → 5 V
However, LOW/HIGH input and LOW/HIGH output have the voltage range.

Input and output voltage levels from the TTL inverter

INPUT OUTPUT
VOLTAGE VOLTAGE
Maximum +5.5 V
+5 V +5 V

+4 V HIGH +4 V
HIGH Typical 3.5
V
+3 V +3 V
TTL
2.4 V
+2 V 2.0 V +2 V
Undefined Undefined
+1 V +1 V
0.8 V
LOW 0.4 V
Typical 0.1 LOW
GND GND
V
Fig. 8-9

- 5-
Input and output voltage levels from the 4000 and 74C00 series inverter

INPUT OUTPUT
VOLTAGE VOLTAGE
+10 V +10 V
4000 9.95 V
and
HIGH
+8 V 74C00 HIGH +8 V
series
7V
+6 V +6 V
Undefined Undefined
+4 V CMOS +4 V
3V
+2 V LOW +2 V
LOW
0.05 V
GND GND

Fig. 8-10

Input and output voltage levels from the 74HC00 series inverter

INPUT OUTPUT
VOLTAGE VOLTAGE
+5 V +5 V
4.9 V
HIGH
+4 V 74HC00 HIGH +4 V
series
3.5 V
+3 V +3 V
Undefined Undefined
+2 V CMOS +2 V

+1 V 1V LOW +1 V
LOW
0.1 V
GND GND

Fig. 8-11

- 6-
Input and output voltage levels from the 74HCT00 series inverter

INPUT OUTPUT
VOLTAGE VOLTAGE
+5 V +5 V
Typical 4.7
HIGH
V
4.3 V
+4 V 74HCT00 +4 V
series
HIGH
+3 V +3 V
Undefined
+2 V 2.0 V CMOS +2 V
Undefined
+1 V LOW +1 V
0.8 V
LOW 0.3 V
Typical 0.2
GND V GND

Fig. 8-12

Noise Margin
Noise in a digital system
=

Unwanted voltages induced in the connecting wires and printed circuit board

Noise Immunity
A circuit’s insentivity or resistance to undesired voltages or noise
Noise Margin in digital circuits

Advantages of CMOS
• Low power consumption
• Good noise immunity

Defining and comparing TTL and CMOS noise margins

- 7-
 INPUT OUTPUT
TTL
VOLTAGE VOLTAGE
+5 V +5 V

+4 V +4 V
HIGH
HIGH
Undefined
+3 V +3 V

Noise Margin (0.4 V)

+2 V +2 V
2.4 V
2.0 V
0.8 V
+1 V 0.4 V +1 V
Noise Margin (0.4 V)
LOW
LOW
GND GND

Fig. 8-13

INPUT OUTPUT
CMOS (74HC00)
VOLTAGE VOLTAGE
+5 V +5 V

HIGH Noise Margin (1.4 V)

4.9 V
+4 V +4 V
HIGH

+3 V 3.5 V +3 V

+2 V +2 V
1V

+1 V LOW +1 V
LOW Noise Margin (0.9 V) 0.1 V
GND GND

Fig. 8-14

Switching Threshold
• The input voltage at which the output logic level switches from HIGH-to-LOW or LOW-
to-HIGH.
• Occurs within the undefined region but varies widely because of manufacturer,
temperature, and the quality of the components.

- 8-
 TTL INPUT LOGIC LEVELS
+5 V

+4 V
HIGH
+3 V

+2 V
Undefined region 1.2 V
switching
actual noise +1 V threshold
0.8 V
margin (1 V)
0.2 V LOW
0 V (GND)
Actual input voltage (LOW)

Fig. 8-15

8.4 Other Digital IC Specifications

Drive Capacities
IC’s maximum wattage and current ratings

Standard TTL voltage and current profiles

Output Drive and Input Loading (worst-case conditions)

OUTPUT DRIVE INPUT LOADING

(STANDARD TTL) (STANDARD TTL)
+5 V +5 V

+4 V IOH IIH +4 V
HIGH
400 µA 40 µA HIGH
+3 V +3 V

+2 V +2 V

+1 V +1 V
IOL IIL
LOW
LOW 16 mA 1.6 mA
GND GND

Fig. 8-19

- 9-
Output drive and input loading characteristics for selected TTL and CMOS logic families
Device Family Output Drive Input Loading
Standard TTL IOH = 400 µA IIH = 40 µA
IOL = 16 mA IIL = 1.6 mA
Low-Power Schottky IOH = 400 µA IIH = 20 µA
IOL = 8 mA IIL = 400 µA
Advanced Low-power Schottky IOH = 1 mA IIH = 20 µA
TTL

IOL = 20 mA IIL = 100 µA

4000 Series IOH = 400 µA IIH = 1 µA
IOL = 400 µA IIL = 1 µA
CMOS

74HC00 Series IOH = 4 mA IIH = 1 µA

IOL = 4 mA IIL = 1 µA
Fig. 8-20

Fan-out
The number of “standard” input loads that can be driven by an IC
Fan-in
The number of inputs that can be handled by an IC

Interfacing LS-TTL to standard TTL problem

Logic diagram of interfacing problem
STANDARD TTL

LS-TTL

Fig. 8-21

Voltage and current profiles for visualizing the solution to the problem
- 10 -
 LS-TTL STANDARD TTL
OUTPUT INPUT
+5 V +5 V

+4 V IOH IIH +4 V
HIGH
400 µA 40 µA HIGH
+3 V +3 V

2.4 V +2 V
+2 V
2.0 V

+1 V 0.8 V +1 V
0.4 V IOL IIL
LOW
LOW 8 mA 1.6 mA
GND GND

Fig. 8-21

The fan-out of LS-TTL gates is 5. (8 mA/1.6 mA = 5)

Propagation Delay
The slight delay between the time the input changes and the time the output changes

Waveforms showing propagation delays for a standard TTL inverter

H
INPUT L
OUTPUT H
L

𝑡PLH ≈ 12 ns 𝑡PHL ≈ 7 ns
Fig. 8-22

Graph of propagation delays for selected TTL and CMOS families

30
Propagation Delay (ns)

20

10
5
0
4000
AS S ALS LS HC Standard C
series
TTL TTL TTL TTL CMOS TTL CMOS
CMOS

Fig. 8-23
- 11 -
8.5 MOS and CMOS ICs
MOS (Metal Oxide Semiconductor) ICs
Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) forms MOS ICs.
MOS devices use less space on a silicon chip than bipolar ICs, because of their simplicity.

Large-scale integration (LSI) and very large-scale integration (VLSI) devices make extensive
use of MOS technology.

Two types of MOS ICs

PMOS (P-channel MOS): Positively doped silicon, rich in holes
NMOS (N-channel MOS): Negatively doped silicon, rich in electrons

CMOS (Complementary symmetry Metal Oxide Semiconductor) ICs

Both PMOS and NMOS devices are connected end to end.
Advantage: low-power consumption

The VDD of the CMOS unit goes to the positive of the power supply.
The “D” in VDD stands for drain supply in MOSFET.
The VSS of the CMOS unit goes to the negative of the power supply.
The “S” in VSS stands for source supply in MOSFET.

8.6 Overview of Memory

Memory Devices in Computer

Fig. 8-24

- 12 -
 CPU Central Processing Unit
RAM Random-Access Memory
ROM Read-Only Memory
NV RAM Non-Volatile Random Access Memory

Semiconductor Storage Cells

Six categories of semiconductor storage devices
SRAM (Static Random-Access Memory)
high access speed, read or write, requires continuous power (volatile memory), low
density, high cost
DRAM (Dynamic Random-Access Memory)
good access speed, read or write, volatile memory plus a need for refresh circuitry, high
density, lower cost, RAM type used in most modern PCs
ROM (Read-Only Memory)
high density, nonvolatile (cannot be altered), reliable, low cost especially at high volumes
EPROM (Erasable Programmable Read-Only Memory)
high density, nonvolatile (can be updated although not easily), ultraviolet light erasable
before programming
EEPROM (Electrically Erasable Programmable Read-Only Memory)
nonvolatile but electrically erasable by bytes for reprogramming, lower density, high cost
Flash Memory
very high density, low power, nonvolatile but rewritable (bit-by-bit) within the digital
system, fairly new and developing technology holding great promise as a solid -state hard
drive, can be portable (like floppy disk) in memory card form

Three important semiconductor memory characteristics

HIGH
DENSITY

EPROM
DRAM
ROM
FLASH

ELECTRICALLY
NON- EEPROM UPDATABLE
VOLATILE SRAM +
BATTERY

- 13 -
 Fig. 8-25

8.7 Random-Access Memory (RAM)

RAM (Random Access Memory)
A semiconductor read/write random-access memory device
Writing into memory Copying information into a storage location
Reading from memory Copying information from a storage location

Called a read/write memory or a scratch-pad memory.

A 64-bit memory organized as a 16 × 4 bit RAM

Address Bit D Bit C Bit B Bit A
Word 0
Word 1
Word 2
Word 3 0 1 1 0
Word 4
Word 5
Word 6
Word 7
Word 8
Word 9
Word 10
Word 11
Word 12
Word 13
Word 14
Word 15
Fig. 8-26

Organized into 16 groups called words, and each word is 4 bits long.
A location in the memory, such as word 3, is referred to as address.
The address of word 3 is 00112 (310), and the data stored at this address is 0110.

A disadvantage of the RAM

volatile; it loses its data when the power is turned off.

PCs implement RAM using both SRAM and DRAM.

- 14 -
8.8 Static RAM ICs
7489 read/write TTL RAM
16 × 4 bit RAM
Output: the complement of the actual memory contents

(a) Logic Diagram

+5 V OUTPUTS
Data outputs

1 kΩ 𝐷 𝐶 𝐵 𝐴

𝐴 𝐷1 𝑄̅4
Data 𝐵 𝐷2 𝑄̅3
inputs 𝐶 𝐷3 𝑄̅2
𝐷 𝐷4 RAM 𝑄̅1

Memory enable ̅̅̅̅̅

𝑀𝐸
(7489)
INPUTS Write enable ̅̅̅̅̅
𝑊𝐸
(read = 1)
(write = 0) 𝐴3 𝐴2 𝐴1 𝐴0

𝐷
Address 𝐶
inputs 𝐵
𝐴
Fig. 8-27

(b) Pin diagram (c) Truth table

(TOP VIEW)
MODE INPUTS CONDITION
𝐴0 1 16 𝑉CC OF OF
̅̅̅̅̅ ̅̅̅̅̅
𝑀𝐸 ̅̅̅̅̅
𝑊𝐸
𝑀𝐸 2 15 𝐴1 OPERATION OUTPUTS
̅̅̅̅̅
𝑊𝐸 3 14 𝐴2 Write L L Complement of data inputs
𝐷1 4 13 𝐴3 Read L H Complement of selected word
𝑄̅1 5 12 𝐷4 Inhibit storage H L Complement of data inputs
𝐷2 6 11 𝑄̅4 Do nothing H H ALL outputs HIGH
𝑄̅2 7 10 𝐷3
GND 8 9 𝑄̅3

Fig. 8-28 Fig. 8-29

- 15 -
8.9 Using a SRAM
Conversion of Binary Number to Gray Code Number

Gray Code
Two successive values differ in only one bit.
Decimal Binary Gray Code
Number Number Number
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

Binary-to-Gray-Code Converter
(a) System Diagram

Binary Binary-to-Gray Gray

INPUT coded code converter coded OUTPUT
number number
(using RAM)

Fig. 8-30

(b) Wiring Diagram using RAM

- 16 -
 +5 V GRAY
CODE
OUTPUT
RAM
1 kΩ 0 1 0 0
(Gray code in memory)
𝑄̅4
Memory enable 0 ̅̅̅̅̅
𝑀𝐸
Write enable 1 ̅̅̅̅̅
𝑊𝐸 𝑄̅3
(read = 1)
𝑄̅2
(7489)
BINARY
𝑄̅1
INPUT
0 1 1 1 𝐴3 𝐴2 𝐴1 𝐴0

Address
inputs

Fig. 8-31

8.10 Data Transmission

Data Selector
Transfers one data from a given parallel data input to the output.

0
1
2
DATA 1 3
Data W 1 OUTPUT
INPUTS 4
Selector
5
6
7
C B A

DATA
SELECTOR 0 1 1
INPUTS
Fig. 8-32

Single-pole eight-position rotary switch works as a data selector.

- 17 -
 0
1
2
DATA 3
1 W
INPUTS 4 1 OUTPUT
5
6
7

Fig. 8-33

Data Transmission
Parallel data is sent over a single wire in serial form and reassembled into parallel data at
the receiving end.

Multiplexer (MUX)
Changes parallel data from one digital device into serial data.
Demultiplexer (DEMUX)
Reassembles the serial data into parallel data at the output.

INPUTS TRANSMISSION OUTPUTS

0 0
1 1
2 2
3 3
4 4
5 5
6 6
Parallel 7 Serial data 7 Parallel
Multiplexer Demultiplexer
data 8 8 data
9 9
10 10
11 11
12 12
13 13
14 14
15 15
Control

Fig. 8-34

- 18 -
Rotary switches act like multiplexer and demultiplexer

Multiplxer Demultiplxer
1 1
2 2
Parallel 3 SW-1 Serial data SW-2 3 Parallel
data 4 4 data
Control
5 5
6 6

Fig. 8-35

Wiring diagram for an experimental transmission system

74150 MUX IC
74154 DEMUX IC inverted outputs
7493 4-bit Binary Counter
7447 7-Segment Display Counter

- 19 -
 Multiplxer Demultiplexer Outputs

0 0 0
1 1 1
2 2
3 3
4 4
5 5
6 6
Parallel 7 Serial 7
W G1
inputs 8 data 8
9 9
10 10
(74150) (74154)
11 11
12 12
13 13
14 14
15 15
Enable 0 Strobe 0 G2 7404s LEDs
Data selects Data selects 150 Ω
D C B A D C B A

a
Decoder a
b +5 V
b
RO(1) QD D c
Reset c
RO(2) QC C d
d
Clock Input A QB B e
e
Input B QA A f
f
(7493) g
(7447) g
150 Ω
Bit being
Transmitted

Fig. 8-36

- 20 -
8.11 Detecting Errors in Data Transmissions
Error Detection
is the process of detecting the errors that are present in the data transmitted from
Multiplexer to Demultiplexer.

Errors occurring during data transmission can be detected using parity bit.
An extra parity bit is generated and transmitted.

INPUTS TRANSMISSION OUTPUTS

A A
Parallel Parallel
B B
data data
C C

A B C
Parity bit
Parity bit
generator
P C B A
Error
Error
alarm
detector

Fig. 8-37

Parity Bit Generator

even number of 1s in parallel data (A, B and C) Parity bit 0
odd number of 1s in parallel data (A, B and C) Parity bit 1

Truth Table and Logic Circuit for parity bit generator

Inputs Output
Parallel Data Parity Bit
C B A P
0 0 0 0
0 0 1 1
𝐴
0 1 0 1 Parity
𝐵 𝑃
0 1 1 0 bit
𝐶
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Fig. 8-38

- 21 -
Error Detector
even number of 1s in parallel data (A, B and C) and Parity bit 0 No Error (0)
odd number of 1s in parallel data (A, B and C) and Parity bit 1 No Error (0)
even number of 1s in parallel data (A, B and C) and Parity bit 1 Error (1)
odd number of 1s in parallel data (A, B and C) and Parity bit 0 Error (1)

Truth Table and Logic Circuit for error detector

Inputs Output
C B A P Error alarm
0 0 0 0 0
0 0 0 1 1
Error
0 0 1 0 1
𝐴 alarm
0 0 1 1 0
𝐵
0 1 0 0 1 𝐶
0 1 0 1 0 𝑃 Light = Error
0 1 1 0 0 No light = OK
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Fig. 8-39

- 22 -