V □ The o p erandi a re put into the stack and the

-----
All operations are performed on an It uses set of general purpose registers (RO, 0

~ ed accumulator (AC) register. R1, R2 ...), one-;fllie most widely accepted operations are carried out on \he top of the
stack. (TOS). The operand, are Implicitly
madel1 far machine ardiitecture taday
E,,/ With one operand i~ citly In the
- 1p eclried on TOS.
~

✓
accumulator register minimi%es the
internal complexity of themachine
and allow for-;~ ructions/
□ Specifies all operands explicit

Q._/"rhe instruction farmat needs or 3

~ • fields according to the operation
-
It does not u se an address field for the
instructions like ADD, MUL, etc. (I.e. zero•
address instruction format). V
The instructian farmat uses only ane (I.e. Two or three -address instruction PUSH and POP in1truction1 ore used to
address field (i.e. one-address - formal). - co.;;;;-unicate with stac~ hich require an
ins~ ction farmat). V □ For example:
address fieii"- -
'-""
□ For example:
,. . v ADD Rl, R2, R3
- - // R1 +- R...2 + R3
0 For example: PUSH A
B [
LOADX / / AC +- M [X]
= - - -
•
- -·~
This can be reduced from three to two
...
- -
ADDX //AC +- AC+ M [X] addresses If the destination register Is the
same as one of the source registers.
STOREY / /M [Y] +- AC

Most of the computers fall into one of the

. /ADD Rl, R2
MOV Rl , R2
-
//Rl +- Rl + R2

// Rl +- R2
.... - Here ADD con,i,h of onl
address field. It ha, th~
ode and no
f popp ing
above three types of organizations. Some the toptwo numbe rs from the sta ck, adding

computers combine features from more

than one organizational structure.
.. .,,
ADD Rl,X / / R1 +- R1 + M [X]
,- ~ ----- them, and pushing the 1um onto the stack.
Thus all the op erands a re implied t o b e in
□

- -
Each address field may specify a
~rocessor register ar a memory operand.
.,.
the stack.
 Three address instructions
• Destination Address Source Address 1 Source Address 2
Three-address instrudion format

Three-address instrudion format has three address fields. ~

One address field is used for destination and two a ddress fields for source.
,-- r -
Each address field may specify a processor register or a memory operand .
It is also called General register organization. ./
Example lnstrudion: ✓ADD R1, R2, R3 J
- . -
ADD R~ , ~ B
·
- - -.,,..,
/ / R1 +- + R3
R2
// R1 +- M[A] + M,.LBl
..-.;
/

Assembly Language Notation (ALN) Equivalent ReglsteJ Transfer Notation (RTN)

Advantage: Results in short programs when evaluating arithmetic expression

Disadvantage: Binary-coded instruction require too many bits to specify three addresses, complex
 Two address instructions
• Destination Address Source Address
Two-address instrudion format

► Two address instrudions are most common in commercial computers

>

► ----
It has two address fields

---
Each address field may specify a processor register or a memory operand.

✓ 't)l1 ~ ~
► Example lnstrudion: ADD R 1, R2
MOV RI , R2
II RI
-
II RI
~

~
RI + R2
.,,.
R2
--
 One address instructions
• Operand Address (S/ D)
One-address instrudion format

> It has only one address field. The operand specified in the instruction may be source
or destination, depending on instruction

> One address instrudions use a implied ACCUMULATOR (AC) register for all data
manipulation.
► Implied means that the CPU already know that one operand is in accumulator so there is no need to
specify it.

► All operations done between accumulator register and memory operand.

► It is also called Single Accumulator Organization

► Example lnstrudion: ADD X // AC ~ AC + M [X]

 Zero address instruction
•
Zero-address instruction format

► In zero address instrudions Stefk is used. Also called stack based organization

► A stack based computer does not use an address field in the instructions (like ADD,
MUL)
► PUSH and POP instructions, however, need an address field to specify the operand
that communicate with stack.

► To evaluate a arithmetic expression first it is converted to Revere Polish Notation i.e.

Post fix Notation.
► The name "zero-address" is given to this type of computer of the absence of an
address field in an instruction
 ✓ A - B + C * (D *E- F)
X -
G +H*K
using three-address instructions ?~
:lfflffitt:

■ -
SUB Rl, A, B //Rl ~M[A]-M[B] /
MUL R2, D, E
. - // !l2 ~ M[D] * M[E]
SUB R2, R2, F // R2 ~ R_2 -M[F]
-
MUL R2, R2, C
- -
// R2 ~ R2 * M[C]
-
✓ ADD&-1, ~1, ~2 //
- - -
Rl ~ Rl + R2
MUL
. R3, H,. K
~
// R3 ~ M[H] * M[K]

-
ADD R3, R3, G
- - -
// R3 ~ R3
-
+ M[G]
-
- -
DIV X, Rl, R3
,...
// M[X]~Rl /R3
XL * (D
~\ Qi ~' --B + C-11.-i- ~ E - _F}
____ ~e,))
using two-address instructions .~
:mffi1t!:
G +H*K
MOV .~ 1, A II Rl -- M[A]
\ SUB Rl,B II Rl -- Rl - M[B] V
"i) --s -
MOV ~2, D II R2 -- M[D]
MUL R2, E I I R2 -- RJ * M[E]
\
- -
SUB R2, F
. ""
MUL R2, C
.
- - -
II R2 -- R2 - M[F]
I I R2 -- R2 * M[C]
- ... ,, -
1''°:ADD1 ~, ~2 II R!-- Rl + R2
MOV R3, H I I R2_i -- M[H]

1)
.MUL R3, K
./
ADD ~3, ~
.
I I R3 ---
I I R3 -- R3 * M[K]
- -- R3 + M[G]
DIV Rl, R3 I I R1 -- R1 I R3
MOV X, Rl // M[X] -- Rl
 J . .
x =
~ A - B Q\ C * (D * E - F) ~c
~L ~ - 1 ; ' P. ::... using one-address instructions JL)
G +H * K ✓ ~l, lffl~l\'H-

■ J

\LOAD A II AC~ M[A] LOAD H IIAC~ H]

'Jc -
SUB B ll~ C ~ 'ic- M[B] MUL K II AC~ A~ * M[K]
STORE T II M[T] ~
~
ADD G 11 ~c~ ~
-
+~
LOAD D
-
II AC~ M[D]
~ ::>-

- - TORE Tl
-
·-
II M[Tl] ~ AC
- -
MUL E
SUB F II - -----
I I AC ~ AC * M[E]
AC~ A_s. - ,Mif]
-
r' LOAD T
DIV T1
,:,
-
II AC~ M[T]
AC~ AC I M[Tl]
II _.... -,..J -
MUL C II AC~ A.£.* M[_C] II M[X] ~ AC 1)
-
I I AC ~ AC + M[T]
STORE X
.,..
-
1\1 ADD T
,,.- - -
STORE T II M[T] ~ AC
~r
 X - ---
A - B + C * (D * E - F)
-
~ using zero-address instructions
-
•
~ ovorso Polish Notation (Postfix }: A B - C ~ E * F .;.
,
*✓,
+ G H K "' + I
- •

~
PUSH A //T'3S - A ')
PUSH G //TOS - G V
PUSH B //Tos - B ;v
SUB //Tos - (A-B) ~
PUSH H //TOS - H)
PUSH K //TOS - K
PUSH C // TOS - cV MUL // TOS - (H* K) ✓
PUSH D //Tos - D,
ADD //Tos - (G+ (H * K) r-=)
PUSH E //Tos - E •
DIV // TOS - ((A-B)+(C* ((D* E)-F))/(G+(H* K)
MUL //TOS - (D' POP X // M[XJ - ros
PUSH F //Tos - F
SUB // TOS - ((D* E) -F)) Y
MUL // TOS - (C* ((D* E)-f)) ✓
ADD // TOS - ((A-B)+(C* ((D* E)- f)) /