Te-Comps Sem5 Mp-Cbcgs Dec19

D 60 3B F 8D D6 A3 AD 3F 0
D9 960 3B1 1FF F8D D6 A3 AD 3F0 002 2979

3 8 D A A 3 9
96 603B B1F FF8 DD 6A 3A D3 F00 0297 79B B3B
03 1 F8 DD 6A 3A D3 F0 29 9B 3B 8D
03 B1 FF8 DD 6A 3A D3 F0 029 79B 3B 8D C5
F 0
3B B1F F8D DD 6A3 3AD D3F F00 297 79B 3B 8DC C5D D96
F 6
1 8 D A A 3 0 9 9B 3B 8D 5 9 032
1F FF8 DD 6A 3A D3F F00 0297 79B 3B 8D C5D D96 603 B1F
D 6 3 D 8 C B
FF F8D D6 A3 AD 3F0 002 2979 9B3 3B8 DC 5D 960 03B 1F F8D
8 D A A 3 0 9 B B D 5 9 3 1 F
F8 DD 6A 3A D3 F00 29 79B 3B 8D C5 D9 603 B1 FF 8DD D6A
DD 6A 3A D3 F0 29 79 3B 8D C5 D9 60 B1 FF 8D 6 3
76317
DD 6A 3A D3 F0 029 79 B3B 8D C5 D9 60 3B1 FF 8D D6 A3 AD
0 7 B 6 3 8 D A A 3
c)
D6 6A3 3AD D3F F002 297 9B 3B8 8DC C5D D96 03B B1F FF8 DD 6A 3A D3F F00
3 D
Q.1 a)
9 0 6 3 D
d)
b)
A 0 F 2
B)
6A A3A D3 3F0 029 979B B3B B8D DC5 5D9 9603 3B1 1FF 8D D6A A3A AD 3F0 002 979
F 0 7 D 6 8
3A D3 0 29 9 3B 8D C5 9 03 B1 FF D 6 3A D F0 02 79 B3 D 3 9
D3 F0 029 79 B3B 8D C5 D9 60 B1 FF 8D D6 A3 D 3F0 02 979 B3 B8
F0 029 79 B3 8D C5 D9 60 3B1 FF 8D D6 A3 AD 3F 02 979 B3 B8 DC
i)
i)
Draw
02 79 B3 B8 C D 60 3B FF 8D D6 A3 AD 3F 002 97 B B8 DC 5D
v)
ii)
ii)
iv)
iii)
iii)
97 B B8 DC 5D 96 3B 1F 8 D A A 3F 00 97 9B 3B D 5 96
9B 3B D 5 96 03 1 F8 DD 6A 3A D3 0 29 9B 3B 8D C5 D9 03
the
3B 8D C5 D9 03 B1 FF8 DD 6A 3A D3 F0 029 79 3B 8D C5 D9 60 B1
8D C5 D9 603 B1 FF D 6A 3A D F0 02 79 B3 8D C D9 60 3B FF
architecture
C5 D9 603 B1 FF 8D D6 3A D 3F0 02 979 B3 B8 C 5D 60 3B 1FF 8D
D9 60 B1 FF 8D D6 A3 D 3F0 02 979 B3 B8 DC 5D 960 3B 1F 8D D6
block
microprocessor
60 3B FF 8D D6 A3 AD 3F 02 979 B3 B8 DC 5D 960 3B 1F F8D D A3
3B 1F 8D D A3 AD 3F 00 97 B B DC 5D 96 3B 1F F8 D 6A A
1F F8 D 6A A 3F 00 297 9B 3B 8D 5D 96 03 1F F8 DD 6A 3A D3
F8 DD 6A 3A D3 00 29 9B 3B 8D C5 9 03 B1 F DD 6A 3A D3 F0
DD 6A 3A D3 F0 29 79 3B 8D C5 D9 60 B1 FF 8D 6 3 D F0 02
IN AL, DX
6A 3A D3 F0 029 79B B3B 8D C5 D9 603 3B1 FF 8D D6A A3A AD 3F0 02 979
JMP [BX+2]
3A D3 F0 029 79 3B 8D C5 D9 603 B1 FF 8D D6 3A D 3F0 02 979 B3
word and timing diagram

AND CL,[2000]
97 B B8 DC 5D 96 3B 1F 8 D A A 3F 00 97 9B 3B D 5 96
MOV AX, [BX+SI]
9B 3B D 5 96 03 1 F8 DD 6A 3A D3 0 29 9B 3B 8D C5 D9 03
Explain BSR mode of 8255 PPI
ADD AX,[BX+SI+5]
N.B. 1) Question No. 1 is compulsory.
Explain memory banking in 8086
if the given year is a leap year or not

(Time: 3 Hours)
D) Explain data transfer modes of DMAC 8257

Q.3 A) Draw and explain the block diagram of PIT 8253
********************
2) Attempt any Three questions out of remaining.
128 KB RAM using 64 KB * 8 devices

64 KB EROM using 32 KB * 8 devices
B) Write a short note on mixed language programming

Write addressing modes of the following instructions
97 B B8 DC 5D 96 3B 1F 8 D A A 3F 00 97 9B 3B D 5 96
9B 3B D 5 96 03 1 F8 DD 6A 3A D3 0 29 9B 3B 8D C5 D9 03
979B3B8DC5D9603B1FF8DD6A3AD3F002
B) Draw and explain demultiplexing of address bus in 8086
8086 working in minimum mode with 8MHz.
Q.2 A) Design 8086 based system for the following requirements
Paper / Subject Code: 31901 / Microprocessor
diagram of PIC8259 and discuss its operation
C) Explain the following instructions in 8086 : LAHF and XLAT

B) Draw and explain maximum mode configuration of 8086 system

Explain VM, RF, IOPL, NT and TF flags of 80386 microprocessor
Q.4 A) Explain how flushing of pipeline problem is minimized in Pentium

3) Assume suitable data wherever necessary and state them clearly.
Q.6 A) Differentiate real mode, protected mode and virtual mode of 80386
02 79 B3 B8 C D 60 3B FF 8D D6 A3 AD 3F 002 97 B B8 DC 5
97 B B8 DC 5D 96 3B 1F 8 D A A 3F 00 97 9B 3B D 5
Q.5 A) Write a 8086 assembly language program with appropriate comments, to find
B) Explain Strobed Bi-directional I/O Mode 2 operation of 8255 PPI with control
9B 3B D 5 96 03 1 F8 DD 6A 3A D3 0 29 9B 3B 8D C5 D
3B 8D C5 D9 03 B1 FF8 DD 6A 3A D3 F0 029 79 3B 8D C5 D9
8D C5 D9 603 B1 FF D 6A 3A D F0 02 79 B3 8D C D9 6
5
5
5
5
5
5
5
5
C5 D9 603 B1 FF 8D D6 3A D 3F0 02 979 B3 B8 C 5D 60

10
10
10
10
10
10
10
10
[80 Marks]
D9 60 B1 FF 8D D6 A3 D 3F0 02 979 B3 B8 DC 5D 960

60 3B FF 8D D6 A3 AD 3F 02 979 B3 B8 DC 5D 960 3
3B 1F 8D D A3 AD 3F 00 97 B B DC 5D 96 3B
1F F8 D 6A A 3F 00 297 9B 3B 8D 5D 96 03 1
F8 DD 6A 3A D3 00 29 9B 3B 8D C5 9 03 B1
DD 6A 3A D3 F0 29 79 3B 8D C5 D9 60 B1 F
6A 3A D3 F0 029 79B B3B 8D C5 D9 603 3B1 FF
3A D3 F0 029 79 3B 8D C5 D9 603 B1 FF 8
D3 F0 029 79 B3B 8D C5 D9 60 B1 FF 8D
F0 029 79 B3 8D C5 D9 60 3B1 FF 8D
02 79 B3 B8 C D 60 3B FF 8D D
97 B B8 DC 5D 96 3B 1F 8 D
3 D

Te-Comps Sem5 Mp-Cbcgs Dec19

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D 60 3B F 8D D6 A3 AD 3F 0

D9 960 3B1 1FF F8D D6 A3 AD 3F0 002 2979

word and timing diagram

Explain memory banking in 8086

if the given year is a leap year or not

D) Explain data transfer modes of DMAC 8257

Q.3 A) Draw and explain the block diagram of PIT 8253

128 KB RAM using 64 KB * 8 devices

F0 029 79 B3 8D C5 D9 60 3B1 FF 8D D6 A3 AD 3F 02 979 B3 B8 DC

B) Write a short note on mixed language programming

diagram of PIC8259 and discuss its operation

C) Explain the following instructions in 8086 : LAHF and XLAT

B) Draw and explain maximum mode configuration of 8086 system

Q.4 A) Explain how flushing of pipeline problem is minimized in Pentium

C5 D9 603 B1 FF 8D D6 3A D 3F0 02 979 B3 B8 C 5D 60

D9 60 B1 FF 8D D6 A3 D 3F0 02 979 B3 B8 DC 5D 960

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