1

 
ICEE 2020 1570693452
2  
3  
4  
5  
6  
7   Development of Low-Cost Silicon BJT Technology
8  
9  
10  
and Modeling
11  
12   S Pande1 , S Balanethiram2 , A K Singh3 , M Gupta3 , B Umapathi3 , H S Jatana3 , N Mohapatra4 , A Chakravorty1
1
13   Department of Electrical Engineering, Indian Institute of Technology Madras. Email: anjan@ee.iitm.ac.in
14   2
Dept. of ECE, Indian Institute of Information Technology, Tiruchirappalli. Email:sureshb@iiitt.ac.in
15   3
Semi-Conductor Laboratory, Chandigarh, Department of Space, Government of Inida. Email: hsj@scl.gov.in
16   4
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar. Email: nihar@iitgn.ac.in
17  
18  
2020 5th IEEE International Conference on Emerging Electronics (ICEE) | 978-1-7281-8660-3/20/$31.00 ©2020 IEEE | DOI: 10.1109/ICEE50728.2020.9776806

19   Abstract—BiCMOS technology enables VLSI circuits with high

20   current driving capability and optimized speed–power-density
21   performance when compared to standalone bipolar or CMOS
technologies. In this work, we present the device design, process
22   development and optimization of diffusion poly-emitter bipolar
23   junction transistor (BJT), for the first time in India, for analog
24   and RF applications. The baseline 180 nm CMOS process of
25   Semi-Conductor Lab at Chandigarh (India) is used to develop
26   the BiCMOS process. All the TCAD simulations are calibrated
with the measured data of baseline BJT from 180 nm CMOS
27  
process. Calibrated simulations of our proposed poly-emitter BJT
28   show current gain > 140 and current driving capacity > 10 mA.
29   The breakdown voltage of the transistor is above 5 V (BVCEO )
30   with cut-off frequency (fT ) and maximum oscillation frequency
31   (fmax ) more than 17 GHz and 40 GHz, respectively.
32   Index Terms—Calibration, TCAD simulation, BJT, process
simulation, current gain, breakdown voltage, cut-off frequency.
33  
34  
35   I. I NTRODUCTION Fig. 1. (a) Active region of the layout of a poly emitter BJT. (b) Complete
36   Although the evolution of CMOS technology, in no doubt,
layout of the device element up to the contacts. (c) Layout view including
the metal layers and (d) RF pads with GSG configuration. (e) The complete
37   has achieved most advancements in silicon technology, bipolar layout showing the DUTs along with its open and short test structures.
38   technology has always remained the first choice for applica-
39   tions where circuit speed is of paramount importance [1], [2]. are well calibrated against the measurements of baseline BJT
40   Highly ambitious projects like DOTFIVE [3] and DOTSEVEN of SCL’s 180 nm CMOS process. Section II elaborates the
41   proposed process flow and the test structure layout. Compact
[4], [5] launched by European commission have shown bipolar
42   model deployment and performance analysis of the proposed
devices demonstrating fmax close to 0.7 THz. It is well known
43   poly-emitter BJT are detailed in section III. Finally, we con-
that at any given technology node, the maximum speed and
44   clude in section IV.
operating frequency of the bipolar transistor is higher than
45  
CMOS [6]. Besides, due to the low noise and relatively higher
46   II. P ROPOSED PROCESS FLOW DEVELOPMENT
power handling capacity, BJTs are preferred over CMOS
47  
devices in certain analog and RF applications. Continuous The baseline BJT of SCL is actually a parasitic byproduct of
48  
efforts are being made to combine the advantage of both the CMOS process. We attempted to enhance the performance
49  
CMOS and Bipolar technology to achieve superior device of this parasitic BJT by introducing minimum additional mask
50  
51   and circuit level performance when compared to CMOS or in the existing CMOS process. Our proposed process flow for
52   Bipolar technology alone. Therefore, development of BiCMOS npn poly-Si emitter BJT begin with p-type wafer of required
53   technology within the existing 180 nm CMOS process of resistivity followed by active area definition. N-buried layer
54   Semi-Conductor Lab (SCL) in India is gaining attention. of the CMOS process forms the buried collector and p-well
55   In this work, we present device design, process development (n-well) acts as the base (collector reach through region). At
56   and optimization of silicon BiCMOS technology in SCL’s this stage, we introduce an additional mask to optimise the
57   180 nm CMOS process. Simulations performed in this work doping profile of the intrinsic BJT. This is followed by the n-
60  
61  
62   978-1-7281-8660-3/20/$31.00 ©2020 IEEE
63  
64  
65  
Authorized licensed use limited to: Univ degli Studi di Palermo - Univ of Palermo. Downloaded on July 11,2023 at 13:57:46 UTC from IEEE Xplore. Restrictions apply.
1
Fig. 2. (a) 2D cross-sectional view of the simulated Poly-emitter BJT half Fig. 3. 1D doping profile of the corresponding intrinsic transistor
structure with WE =0.5µm. (b) TCAD calibration with measured data

well annealing, gate oxidation step of the CMOS process and

poly-silicon deposition (which essentially acts as gate poly
for the MOS transistors). With the help of an additional mask,
earlier work [8]. Fig. 2(a) shows the simulated half structure
deposited poly-silicon is patterned to define poly-emitter area.
of poly-emitter BJT and Fig. 2(b) compares the Gummel char-
This is followed by the deposition and doping of emitter poly-
acteristics obtained from measurements (symbols) and TCAD
silicon. After etching the poly-emitter and gate oxide from
simulation data (lines). Device simulations are performed with
the base and collector region of BJT, the device is subjected
Drift-Diffusion transport model in Sentaurus for the structure
to source/drain implantation of CMOS process in order to
discussed above. All other appropriate models for the BJT such
form the emitter and extrinsic base contacts. In Fig. 1, masks
as band gap narrowing, recombination, etc., are included in the
corresponding to the steps mentioned in the above process are
simulation. The current components from the 2D simulations
shown in the RF test structures of single poly BJT layouts.
are multiplied by a corresponding length factor for comparison
Fig. 1(a) shows the active region of the layout of a stripe
with their respective experimental results. Unlike the baseline
geometry single finger poly-emitter BJT and Fig. 1(b) shows
BJT [8], the poly emitter BJT structure houses a single STI for
the layout up to the contacts. Fig. 1(c) shows the layout with
the base and collector isolation, while the gate poly-Si isolates
the addition of metal-1 and metal-2 layers. In Fig. 1(d), RF
emitter and extrinsic base as shown in Fig. 2(a). This results
pads (G-S-G configuration) are shown to be added to the
in the reduction of the effective foot-print area of the external
layout. In Fig. 1(e) we have shown the DUTs along with
transistor compared to the baseline BJT structures. We intend
the open and short test structures (OTS and STS) for de-
to reduce the base width and slightly increase the collector
embedding. Layouts of RF, DC and diode test structures of
doping. The former is useful to reduce the recombination
single poly device for different device configurations such
current in the base to enable a higher current gain (β) and
as square emitter, stripe geometry emitter, and multifinger
the latter improves the cut-off frequency (fT ) by pushing the
transistors are prepared. Test structures include variations in
Kirk-effect towards higher current density. Therefore, after the
the emitter area and poly overlap area in order to verify
n-well process step, we optimized the phosphorous implant
scalability of the compact model (discussed in the next section)
(BF2 implant) for internal collector (base) region in the p-
and to study the optimum poly overlap, respectively. The
well mask window. The phosphorous implant is done in three
proposed test structures based on the process flow described
steps. The dose and energy of each step are 1x1013 cm−2 and
above are fabricated in the 180nm CMOS technology of
700 keV, 1x1012 cm−2 and 250 keV, and 1x1012 cm−2 and
SCL, India. In addition, detailed calibrated TCAD process
50 keV. Similarly, BF2 implant is done in a single steps with
simulations are carried out using Synopsys Sentaurus [7] to
dose and energy as 5x1013 cm−2 and 5 keV, respectively.
analyze the performance of the device obtained by following
The 1D doping profile for the optimised split along the intrin-
the proposed process flow.
sic transistor is shown in Fig. 3. The peak doping concentra-
III. P OLY- EMITTER BJT tions in the emitter, base and collector regions are, respectively,
2x1020 cm−3 , 2x1018 cm−3 and 2x1017 cm−3 . Note that
A. Process Optimization the proposed BJT process requires only two additional mask
TCAD calibration with the measured data corresponding to the compared to the standard baseline process without affecting
baseline BJT of SCL’s 180 nm process flow is explained in our the CMOS performance.

Authorized licensed use limited to: Univ degli Studi di Palermo - Univ of Palermo. Downloaded on July 11,2023 at 13:57:46 UTC from IEEE Xplore. Restrictions apply.
2
B. Compact Modeling
For compact model development, parameters related to the
High Current Model (HICUM) are extracted following [9] to
enable SPICE simulation of the proposed device. The proce-
dure is a combination of several steps, each one corresponding
to specific bias regions of the device that allow simplifica-
tions of the model equations. The extraction procedure is
implemented in python that post-processes the measurement
and/or TCAD simulation data to generate the HICUM model
parameters. In this report, we used the parameter extraction
done on a TCAD simulated poly-emitter BJT with optimised
split. The extracted model parameters are validated using Fig. 5. Comparison of VBE driven output characteristics of the proposed
the circuit simulator, QucsStudio [10]. The BJT is modeled poly-emitter BJT obtained from TCAD simulations with compact model result
using HICUM verilog-A code and the extracted parameters for WE = 0.5 µm.
are plugged into the model. Comparison between the compact
model and TCAD simulation results is discussed in the next
section.
C. DC Performance
Figs. 4 and 5 show, respectively, the Gummel and the VBE
driven output characteristics of the proposed poly-silicon
emitter structure. The collector and base currents per unit
length obtained from the TCAD simulation are multiplied by
a length factor of 10 (equivalent to LE = 10 µm) to obtain
their absolute values. The compact modeling results show
excellent agreement with the corresponding TCAD simulation.
We observe a maximum β of 143 from the Gummel simulation
Fig. 6. Breakdown voltage analysis of the structure in Fig. 3(a) at a fixed
data while the Early voltage (VA ) of the proposed structure is value of VBE = 0.7 V. BVCEO and BVCBO obtained here are 5V and >
found to be around 19 V. 8 V, respectively.

fixed value of VBE equal to 0.7 V, we obtained output charac-

Fig. 4. Comparison of Gummel characteristics of the proposed poly-emitter
BJT obtained from TCAD simulations with compact model results for WE =
0.5 µm.
D. Breakdown Analysis
We performed the breakdown analysis to obtain the collector-
emitter breakdown voltage for open base (BVCEO ) and the
collector-base breakdown voltage for open emitter (BVCBO )
[11]. These two figures-of-merit are extracted as follows. For a
teristics of the device as shown in Fig. 6. Now for an increase
in the reverse bias of VCB , the generation current component
of the base due to the injection of holes from collector to
the base region increases leading to a reduction in the overall
base current. When this generation current component of the
base exactly balances the injection and recombination current
components in the base, IB → 0 resulting in an open base
condition. This condition is reflected as reversal of IB when
plotted in log scale (Fig. 6). VCB corresponding to that point
when added with VBE yields BVCEO [12]. Further increasing
the reverse bias results in the increase of IB in the reverse
direction. Therefore, at some VCB we eventually arrive at the
condition of open emitter where IE → 0. This condition is
identified when IB and IC show almost the same value in a log
scale which is orders of magnitude higher than IE , emulating
an open emitter condition. VCB value corresponding to this
condition is denoted as BVCBO [13]. This situation is not
explicitly shown in Fig. 6. With the given results, we observe
that our structure shows BVCEO of 5V and BVCBO more
than 8V.

Authorized licensed use limited to: Univ degli Studi di Palermo - Univ of Palermo. Downloaded on July 11,2023 at 13:57:46 UTC from IEEE Xplore. Restrictions apply.
3
E. RF Performance
The two popular figures-of-merit governing the RF perfor-
mance of the device are cut-off frequency (fT , when small sig-
nal current-gain is unity) and maximum oscillation frequency
(fmax , when small signal power gain is unity). One can obtain
fT and fmax from the y-parameters of the device [14]. The
cut-off frequency of a BJT is given as [9]
f f
fT =  =  
= 1
= Y11
βac Y21
and the maximum oscillation frequency can be obtained ana-
lytically as [15]
r ELE/17-18/176/ISRO/ANJA and in part by DST project
fT
fmax = (2)
8πRB CCB
where f is the frequency of simulation. RB and CCB are
Fig. 7. Collector current dependent cut-off frequency(ft ) and (b) maximum
oscillation frequency(fmax )
base resistance and collector-base capacitance, respectively.
Fig. 7 shows fT and fmax of the poly-emitter BJT. Since
fT is primarily affected by vertical scaling [1], we have
observed a significant increase in fT with reduced WB due
to the reduction in base transit time. Poly-emitter BJT with
smaller WE and larger LE (stripe emitter geometry) offers
low base resistance which eventually increases fmax (see (2))
compared to the square geometry BJTs. We performed y-
parameter simulation with VE = 0V, VC = 1.7V and VB swept
from 0.4 V to 1.0 V. For each value of bias point, a full
frequency sweep is performed starting at a frequency where
the gain is flat and ending beyond the unit gain point.The
presented results are obtained following the unity gain method
which essentially looks for the unity gain point at each bias
voltage.
IV. C ONCLUSION
We presented the design and optimization of a silicon BiC-
MOS process, developed for the first time in India, for analog
Authorized licensed use limited to: Univ degli Studi di Palermo - Univ of Palermo. Downloaded on July 11,2023 at 13:57:46 UTC from IEEE Xplore. Restrictions apply.
and RF applications. The 180 nm CMOS process of SCL,
India, is used as the baseline process. Calibrated process
and device simulations were carried to optimize the device
performance of poly-emitter BJT. Further, it is shown that our
proposed poly-emitter BJT which requires only two additional
masks, can achieve a current gain > 140, current driving
capacity > 10 mA, breakdown voltage BVCEO (BVCBO ) of
5V(> 8V ) along with a cut-off frequency (fT ) and maximum
oscillation frequency (fmax ) more than 17 GHz and 40 GHz,
(1)
respectively.
V. ACKNOWLEDGEMENT
This work is supported in part by ISRO project
EMR/2016/004726.
R EFERENCES
[1] J.-S. Rieh, D. Greenberg, Q. Liu, A. J. Joseph, G. Freeman, and
D. C. Ahlgren, “Structure optimization of trench-isolated SiGe HBTs
for simultaneous improvements in thermal and electrical performances,”
IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2744–2752, 2005.
[2] T. H. Ning, “History and future perspective of the modern silicon bipolar
transistor,” IEEE Trans. Electron Devices, vol. 48, no. 11, pp. 2485–
2491, 2001.
[3] DOTFIVE. (2008) Project supported by European commisssion.
[Online]. Available: http://www.dotfive.eu/
[4] R. Lachner, “Towards 0.7 THz Silicon Germanium Heterojunction Bipo-
lar Technology–The DOTSEVEN Project,” ECS Transactions, vol. 64,
no. 6, pp. 21–37, 2014.
[5] DOTSEVEN. (2012) Project supported by European commisssion.
[Online]. Available: http://www.dotseven.eu/
[6] J. D. Cressler and G. Niu, Silicon-Germanium Heterojunction Bipolar
Transistors. Artech house, 2002.
[7] T. Synopsys, “Sentaurus: Sentaurus device user guide, release H-
2013.03,” 2013.
[8] S. Balanethiram, S. Pande, A. K. Singh, B. Umapathi, H. S. Jatana,
N. Mohapatra, and A. Chakravorty, “Development of low-cost silicon
bicmos technology for rf applications,” in 2019 IEEE Conference on
Modeling of Systems Circuits and Devices (MOS-AK India), 2019, pp.
39–42.
[9] M. Schröter and A. Chakravorty, Compact Hierarchical Bipolar Tran-
sistor Modeling with HICUM. World Scientific, 2010.
[10] M. Margraf. Qucsstudio – a free and powerful circuit simulator.
[Online]. Available: http://qucsstudio.de
[11] T. Vanhoucke and G. Hurkx, “Unified electro-thermal stability criterion
for bipolar transistors,” in Proc. Bipolar/BiCMOS Circuits and Technol-
ogy Meeting (BCTM), 2005, pp. 37–40.
[12] M. Jaoul, C. Maneux, D. Céli, M. Schröter, and T. Zimmer, “A compact
formulation for avalanche multiplication in SiGe HBTs at high injection
levels,” IEEE Trans. Electron Devices, 2018.
[13] V. Jain, H. Ding, R. Camillo-Castillo, and A. Joseph, “DC and RF break-
down voltage characteristics of SiGe HBTs for WiFi PA applications,”
in Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM),
2016, pp. 29–32.
[14] G. Hurkx, “The relevance of fT and fmax for the speed of a bipolar
CE amplifier stage,” IEEE Trans. on Electron Devices, vol. 44, no. 5,
pp. 775–781, 1997.
[15] Y. Taur and T. H. Ning, Modern VLSI Devices. Cambridge, UK:
Cambridge Univ. Press, 2009.
4