Dokumen - Tips Clevo6 71 w24h0 D02aunlockedpdf

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E5120Q/E5120Q-C, E5125/E5125-C, E5128Q, E5128Q-C
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Preface
Notebook Computer
E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C
Service Manual
P
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Preface
Ab out t hi s Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the E5120Q/
E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists P

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Appendix B, Schematic Diagrams e
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Appendix C, Updating the FLASH ROM BIOS c
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III
Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A (65W) minimum AC/DC Adapter.
e
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f CAUTION
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This Comput er’s Optic al Device is a Laser Class 1 Produ ct
FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.
IV
Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and don ’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Don’t use or store the com- Do not place the computer on
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heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block e
ture may affect the system. the vents.
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3. Follow the proper working procedures for the comp uter . Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avo id i nt erf eren ce. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices .
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
e
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a
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e • Only use a power adapter approved for use with this computer.
P
r • Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
Power Safety • The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake • When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- • Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that • Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-

move your battery in
order to prevent acci-
dentally turning the
machine on.
VI
Preface
Related Document s
You may also need to consult the following manual for additional information:
User’s Manual on CD/DVD

This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
System Startup
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
e 5. Attach the AC/DC adapter to the DC-In jack on the left of the
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computer, then plug the AC power cord into an outlet, and connect
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the AC power cord to the AC/DC adapter.
P 6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 135 degrees); use the other hand (as illustrated in Figure
1) to support the base of the computer (Note: Never lift the computer
by the lid/LCD).
7. Press the power button to turn the computer “on”.
Shut Down
Note that you should al-

ways shut your com-
puter down by
choosing Shut Down
135
from the Start Menu.
Figure 1 This will help prevent

hard disk or system
Opening the Li d/LCD/Computer with AC/DC Adapter
problems.
Plugged-In
VIII
Preface
Contents
Introduction ..............................................1-1 Top (E5125) ................................................................................... A-4
Top (E5128Q) ................................................................................ A-5
Overview .........................................................................................1-1
Bottom ........................................................................................... A-6
Specifications ..................................................................................1-2
DVD Dual Drive ............................................................................ A-7
External Locator - Top View with LCD Panel Open ...................... 1-4 LCD ............................................................................................... A-8
External Locator - Front & Right Side Views ................................. 1-5
External Locator - Left Side & Rear View ..................................... 1-6 Schematic Diagrams.................................B-1
External Locator - Bottom View .....................................................1-7 System Block Diagram ...................................................................B-2
Mainboard Overview - Top (Key Parts) ......................................... 1-8 Clock Generator ..............................................................................B-3
Mainboard Overview - Bottom (Key Parts) ....................................1-9 CPU 1/7 (DMI, PEG, FDI) .............................................................B-4
Mainboard Overview - Top (Connectors) .....................................1-10 CPU 2/7 (CLK, MISC, JTAG) .......................................................B-5
Mainboard Overview - Bottom (Connectors) ............................... 1-11 CPU 3/7 (DDR3) ............................................................................ B-6
Disassembly ...............................................2-1 CPU 4/7 (Power) .............................................................................B-7 P
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CPU 5/7 (Graphics Power) .............................................................B-8 e
Overview .........................................................................................2-1 f
CPU 6/7 (GND) ..............................................................................B-9
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Maintenance Tools ..........................................................................2-2 CPU 7/7 (RESERVED) ................................................................B-10 e
Connections .....................................................................................2-2
DDR3 SO-DIMM_0 .....................................................................B-11
Maintenance Precautions .................................................................2-3
DDR3 SO-DIMM_1 .....................................................................B-12
Disassembly Steps ...........................................................................2-4
LVDS, Inverter .............................................................................B-13
Removing the Battery ......................................................................2-5
HDMI, CRT ..................................................................................B-14
Removing the Hard Disk Drive .......................................................2-6
IBEXPEAK- M 1/9 .......................................................................B-15
Removing the Optical (CD/DVD) Device ...................................... 2-8
IBEXPEAK - M 2/9 ......................................................................B-16
Removing the System Memory (RAM) ..........................................2-9
IBEXPEAK - M 3/9 ......................................................................B-17
Removing and Installing a Processor ............................................2-11
IBEXPEAK - M 4/9 ......................................................................B-18
Removing the 3G Module .............................................................2-14
IBEXPEAK - M 5/9 ......................................................................B-19
Removing the Wireless LAN Module ...........................................2-15
Removing the Bluetooth Module ..................................................2-16 IBEXPEAK - M 6/9 ......................................................................B-20
IBEXPEAK - M 7/9 ......................................................................B-21
Removing the Keyboard ................................................................2-17
IBEXPEAK - M 8/9 ......................................................................B-22
Part Lists ..................................................A-1 IBEXPEAK - M 9/9 ......................................................................B-23
Part List Illustration Location ........................................................ A-2 New Card, Mini PCIE ...................................................................B-24
Top (E5120Q) ................................................................................ A-3 3G, CCD, TPM .............................................................................B-25
IX
Preface
Card Reader/LAN JMB251C ....................................................... B-26

LAN (JMC251C), SATA HDD, ODD ......................................... B-27
Audio Codec VIA1812 ................................................................. B-28
KBC-ITE IT8502E ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
USB, 3VS,
5VS, Fan, TP,
1.5VS Multi-Conn ........................................................... B-32
.......................................................................... B-31
Power 3.3V/5V ............................................................................. B-33
Power 1.5V/0.75V, 1.8VS ............................................................ B-34
Power 1.1VS_VTT ....................................................................... B-35
Power VGFX_Core ...................................................................... B-36
V-Core .......................................................................................... B-37
AC_IN, Charger ........................................................................... B-38
e Click Board .................................................................................. B-39
c Audio Board/USB ........................................................................ B-40
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e Power Switch & LED Board ........................................................ B-41
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P External ODD Board .................................................................... B-42
Sequence ....................................................................................... B-43
Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ....................................................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive ................................................................................................ C-1
Set the computer to boot from the external drive ........................... C-1
Use the flash tools to update the BIOS .......................................... C-2
Restart the computer (booting from the HDD) .............................. C-2
Introduction
Chapter 1: Intro duct ion

Overview
This manual covers the information you need to service or upgrade the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/
E5128Q-C series notebook computer. Information about operating the computer (e.g. getting started, and the Setup util-
ity) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The
manual is shipped with the computer.
Operating systems (e.g. Windows Vista/ Window 7, etc.) have their own manuals as do application softwares (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
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The E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook is designed to be upgradeable. See Dis-
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assembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please take note
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of the warning and safety information indicated by the “ ” symbol.
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The balance of this chapter reviews the computer’s technical specifications and features. t
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Overview 1 - 1
Introduction
Specifications Processor Options BIOS
Intel® Core™ i7 Processor One 32Mb SPI Flash ROM

i7-640M (2.80GHz), i7-620M (2.66GHz) Phoenix™ BIOS
4MB L3 Cache & 1066MHz FSB
Storage
Intel® Core™ i5 Processor
Latest Specification Information
(Factory Option) One Changeable 12.7mm(h) Super Multi
The specifications listed here are correct at the i5-540M (2.53GHz), i5-520M (2.4GHz), Optical Device Drive
i5-450M (2.4GHz), i5-430M (2.26GHz)
time of sending them to the press. Certain items 3MB L3 Cache & 1066MHz FSB One Changeable 2.5" 9.5 mm (h) SATA HDD
(particularly processor types/speeds) may be
changed, delayed or updated due to the manu- Intel® Core™ i3 Processor Audi o
facturer's release schedule. Check with your i3-370M (2.4GHz), i3-350M (2.26GHz), i3-330M (2.13GHz)
service center for more details. High Definition Audio Compliant Interface
3MB L3 Cache & 1066MHz FSB
2 * Built-In Speakers
Intel® Pentium® Processor
Built-In Microphone
n P6000 (1.86GHz)
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Full-size “WinKey” keyboard (with numeric keypad)
u P4500 (1.86GHz)
d Pointing Device
o CPU 2MB L3 Cache & 1066MHz FSB
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n The CPU is not a user serviceable part. Ac- LCD Built-in Touchpad
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1 warranty. 15.6" (39.62) HD TFT LCD Security
Memory Security (Kensington® Type) Lock Slot

BIOS Password
Two 204 Pin SO-DIMM Sockets Supporting DDR3 1066/
1333 MHz Memory Interface
Memory Expandable up to 8GB
Three USB 2.0 Ports
Core Logic One HDMI-Out Port
One Headphone-Out Jack
Intel ® HM55 Chipset
One Microphone-In Jack
Video Adapter One RJ-45 LAN Jack
One DC-in Jack
Intel ® HM55 Integrated Video
One External Monitor Port
Shared Memory Architecture of up to 1748MB
MS DirectX® 10 compatible
1 - 2 Specifications
Introduction
Card Reader Environmental Spec
Embedded Multi-In-1 Card Reader Temperature

MMC (MultiMedia Card) / RS MMC Operating: 5°C - 35°C
SD (Secure Digital) / Mini SD / SDHC/ SDXC Non-Operating: -20°C - 60°C
Compatible Relative Humidity
MS (Memory Stick) / MS Pro / MS Duo Operating: 20% - 80%
Communication Non-Operating: 10% - 90%
Built-In Gigabit Ethernet LAN Dimensions & Weight

(Factory Option) 300K/ 1.3M Pixel USB PC Camera Mod- 374mm (w) * 250mm (d) * 14.3 - 34.1mm (h)
ule
2.3 kg (with 48.84WH Battery and ODD)
(Factory Option) Bluetooth 2.1 + EDR Module
(Factory Option) 3.75G/HSPA Half Mini-Card Module
(Factory Option) Combo WLAN (802.11b/g/n) and Blue-
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tooth 3.0 Module n
(Factory Option) Intel® WiFi Link 1000 (802.11b/g/n) Wire-
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less LAN Half Mini-Card Module
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(Factory Option) Third-Party 802.11b/g/n Wireless LAN Half u
Mini-Card Module
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Power o
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6 Cell Smart Lithium-Ion Battery Pack, 48.84WH
(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH
(Factory Option) 4 Cell Smart Lithium-Ion Battery Pack,
32.56WH
Full Range AC/DC Adapter

AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)
Energy Star 5.0 Compliant
Specifications 1 - 3
Introduction
Figure 1
External Loc ator - Top View wit h LCD Panel Open
Top View
1
1. PC Camera
(Optional)
2. LCD
3. Power Button
4. LED Status
Indicators
5. Keyboard 2
6. Built-In
Microphone
n 7. Touchpad &
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1 - 4 External Locator - Top View with LCD Panel Open
Introduction
External Locato r - Fron t & Right Side Views Figure 2

Front View
1. LED Indicators
FRONT VIEW

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Figure 3
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Right Side View n
1. Microphone-In
RIGHT
SIDE VIEW Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
4. Optical Device
1 2 3 Drive Bay
4 5 5. Emergency Eject
Hole
External Locator - Front & Right Side Views 1 - 5
Introduction
External Loc ator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor /
3. Port
RJ-45 LAN Jack LEFT SIDE VIEW
4. HDMI-Out Port
5. 2 * USB 2.0 Ports
6. Vent
7. Multi-in-1 Card 1 2 3 4 5 5 7
Reader 6
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Figure 5 REAR VIEW

Rear View
1. Security Lock Slot
2. Battery
1 2
1 - 6 External Locator - Left Side & Rear View
8/18/2019 clevo+6-71-w24h0-d02a.unlocked.pdf Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery
2. Component Bay
Cover
3. Vent
4. Hard Disk Bay
1 Cover
5. Speakers
6. USIM Card 1
Cover .I
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3 3
4

Overheating
5 5 To prevent your com-
puter from overhea-
ting, make sure no-
thing blocks any vent
while the computer is
in use.
External Locator - Bottom View 1 - 7
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Figure 7 Mainb oard Overvi ew - Top (Key Parts)

Mainboard Top
Key Parts
1. JMC251C
2. Clock Generator
3. KBC-ITE IT8502E
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1 - 8 Mainboard Overview - Top (Key Parts)
Mainbo ard Overview - Bottom (Key Parts) Figure 8

Mainboard Bottom
Key Parts
1. Memory Slots
DDR3 SO-DIMM
2. Mini-Card
Connector (3.5G
Module)
3. Audio Codec
4. USIM Card
5. Mini-Card
Connector (WLAN 1
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1 Module) n
8 6. Multi-in-1 Card
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Reader d
7. Platform Controller u
Hub
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8. CPU Socket (CPU
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installed)
7
2 4 6
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Mainboard Overview - Bott om (Key Parts) 1 - 9
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Figure 9 Mainb oard Overview - Top (Connector s)

Mainboard Top
Connectors
1. HDMI-Out Port
2. USB Ports
3. Speaker Cable
Connector
4. Microphone
Cable Connector
9
5. TouchPad Cable
Connector
n 6. Click Board
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u Connector
d 8
o 8. Keyboard Cable
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n Connector
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. 9. Switch Board
2
1 Cable Connector
4 6
5
1 - 10 Mainboard Overview - Top (Connectors)
Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Bottom
8 Connectors
1. Battery
10 9 7 Connector
2. ODD Connector
1
3. HDD Connector
4. Bluetooth Cable
6 Connector
5. CPU Fan Cable
Connector
6. RJ-45 LAN Jack 1
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7. External Monitor n
Port
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8. DC-In Jack d
9. CCD Cable u
Connector
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10.LCD Cable
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Connector
11. CMOS Battery
Connector
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Mainboard Overview - Bottom (Connectors) 1 - 11
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1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/

E5128Q-C series notebook’s parts and subsystems. When it comes to reassembly, reverse the procedures (unless other-
wise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
2
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repeated here for your convenience. i
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To make the disassembly process easier each section may have a box in the page margin. Information contained under
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the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a
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lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
b
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ- l
y
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a will also provide any possible helpful information. A box with a contains warnings.
An example of these types of boxes are shown in the sidebar.
Warning
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
• M3 Philips-head screwdriver
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver
• Small flat-head screwdriver
• Pair of needle-nose pliers
• Anti-static wrist-strap
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Connections
m Connections within the computer are one of four types:
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s Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
a
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s gently pry the locking collar away from its base. When replac-
D
. ing the connection, make sure the connector is oriented in the
2 same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the c onnection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.

Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to sta rt.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re-
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avo id in terf erenc e. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
nected all peripherals
the position of magnetized tools (i.e. screwdrivers).
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power . Avoid accidental shocks, discharges or explosions. move your battery in
2
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•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
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6. Peripherals – Turn off and detach any peripherals. machine on.
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7. Beware of static disc harge. ICs, such as the CPU and main support chips, are vulnerable to static electricity. s
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Before handling any part in the computer, discharge any static electricity inside the computer. When handling a m
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that b
you use an anti-static wrist strap instead.
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8. Beware of corrosi on. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environ ment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do
Do not
not apply cleaner
use volatile directly todistillates)
(petroleum the computer, use a soft
or abrasive clean cloth.
cleaners on any part of the computer.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the Bluetooth Module:

1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the Bluetooth Module page 2 - 16
To remove t he HDD:
1. Remove the battery page 2 - 5 To remove the Keyboard:
2. Remove the HDD page 2 - 6 1. Remove the battery page 2 - 5
2. Remove the keyboard page 2 - 17
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To remove the Optic al Device:
b 1. Remove the battery page 2 - 5
m 2. Remove the Optical device page 2 - 8
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s To remove the System Memory:
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i 1. Remove the battery page 2 - 5
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. 2. Remove the system memory page 2 - 9
2
To remove and install a Processor:
1. Remove the battery page 2 - 5
2. Remove the processor page 2 - 11
3. Install the processor page 2 - 13
To remove th e 3G Modul e:
2. Remove the 3G module page 2 - 14
To remove the Wireless LAN Module:

2. Remove the WLAN module page 2 - 15
2 - 4 Disassembly Steps
Disassembly
Removing the Battery Figure 1

1. Turn the computer of f , and turn it over. Battery Removal
2. Slide the latch 1 in the direction of the arrow (Figure 1a).
a. Slide latch at point 1 to-
3. Slide the latch 2 in the direction of the arrow, and hold it in place (Figure 1a).
wards the unlock symbol
4. Slide the battery 63 in the direction of the arrow 4 (Figure 1b ). and hold it in place.
b. Slide the battery in the di-
rection of the arrow.
a. b.
2
1 3
2
.D
i
s
4
a
s
s
e
m
b
l
y

3. Battery
Removing the Battery 2 - 5
Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the User’s Manual ) when setting up a new hard disk.
a. and
Locate the HDD
remove bay cover
the screws. Hard Disk Upgrade Process
1. Turn of f the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 (Figure 2a).
y
l
b
a.
HDD System Warning
m
e
s New HDD’s are blank. Before you
s begin make sure:
a
s
i
D
You have backed up any data
. you want to keep from your old
2 HDD.
You have all the CD-ROMs and

FDDs required to install your op-
1 2 erating system and programs.
If you have access to the internet,

download the latest application
and hardware driver updates for
the operating system you plan to
install. Copy these to a remov-
able medium.
• 2 Screws
2 - 6 Removing the Hard Disk Drive
Disassembly
3. Remove the hard disk bay cover 63 (Figure 3b ).
4. Grip the tab and slide the hard disk in the direction of arrow 4 (Figure 3c ). Figure 3
HDD Assembly
5. Lift the hard disk 5 out of the bay 6 (Figure 3d ).
Removal (cont’d.)
6. Remove the screw 7 - 10 and the mylar cover 11 from the hard disk 12 (Figure 3e).
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
b. d. c. Grip the tab and slide the

HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
6 5 e. Remove the screws and
mylar cover.
2
.D
e. i
s
a
s
s
e
m
b
l
y
3
c. e.
7

8 3. HDD Bay Cover
10 11. Adhesive Cover
11
4 9 12.HDD
• 4 Screws
12
Removing the Hard Disk Drive 2 - 7
Disassembly
Figure 4 Removing the Optical (CD/DVD) Device
Optical Device
1. Turn of f the computer, remove the battery (page 2 - 5) and hard disk (page 2 - 6).
Removal
2. Remove the screw at point 1 (Figure 4a).
a. Remove the screw at 3. Use a screwdriver to carefully push out the optical device 3 at point 2 (Figure 4b ).
point 1 . 4. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
b. Use a screwdriver to screw holes should line up).
carefully push out the 5. Restart the computer to allow it to automatically detect the new device.
optical device at point
2 .
a. b.
y
l 3
b
m
e
s
s 1
a
s
i
D
.
2
2 2

3. Optical Device
• 1 Screw
2 - 8 Removing the Optical (CD/DVD) Device
Disassembly
Removing the System Memory (RAM) Figure 5
RAM Module
The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
Removal
DDRIII (DDR3) Up to 1066/1333 MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules sup-
ported are 1024MB and 2048MB DDRIII Modules. The total memory size is automatically detected by the POST rou- a. Remove the screws
tine once you turn on your computer. from the component
bay cover.
Memory Upgrade Process b. The RAM modules will
1. Turn of f the computer, turn it over and remove the battery (page 2 - 5). be visible at point 5
2. Remove screws 1 - 4 from the component bay cover (Figure 5a). on the mainboard.
c. Pull the release lat-
3. The RAM modules will be visible at point 5 on the mainboard (Figure 5b).
ches.
4. Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the d. Remove the module.
arrows (Figure 5c). The RAM module 8 will pop-up (Figure 5d ), and you can then remove it. 2
.D
a. c. d.
1
i

s
2
a
Contact Warning
s
s
6 Be careful not to touch
e
m
the metal pins on the
3 b
module’s connecting l
y
8 edge. Even the cleanest
4 hands have oils which
can attract particles, and
7 degrade the module’s
b. performance.
5
8. RAM Module
• 4 Screws
Removing the System Memory (RAM) 2 - 9
Disassembly
5. Pull the latches to release the second module if necessary.
6. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
7. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot
as it will go. DO NOT FORCE IT; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
9. Replace the component bay cover and the screws (see page 2 - 8).
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
y
l
b
m
e
s
s
a
s
i
D
.
2
2 - 10 Removing the System Memory (RAM)
Disassembly
Removing and Installing a Processor Figure 6
Processor Removal Procedure Processor Removal
1. Turn of f the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8). a. Locate the heat sink.
2. Locate the heat sink. b. Remove the screws from
3. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure the CPU heatsink.
4. 6b).
c. sink.
Remove the CPU heat
Carefully lift up the heat sink 4 (Figure 6c) off the computer.
a. c.
4 2
.D
A i
s
a
s
s
e
m
b
l
y
b.

2 4. Heat Sink
• 3 Screws
Removing and Installing a Processor 2 - 11
Disassembly
8/18/2019
5. Turn the release latch 5 towardsclevo+6-71-w24h0-d02a.unlocked.pdf
the unlock symbol to release the CPU (Figure 7d).
Figure 7 6. Carefully (it may be hot) lift the CPU 6 up and out of the socket (Figure 7e).
Processor Removal 7. Reverse the process to install a new CPU.
(cont’d) 8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d. Turn the release latch to
unlock the CPU. d.
e. Lift the CPU out of the
socket.
5
5
y
l
b
m
e
s
s
a
s
i
D Unlock Lock
.
2
e.

Caution
6 The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Allow
the area time to cool before remov-
ing these parts.

6. CPU
2 - 12 Removing and Installing a Processor
Disassembly
Processor Installation Procedure Figure 8
1. Insert the CPU A (Figure 8a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE Processor
IT!), and turn the release latch B towards the lock symbol (Figure 8b). Installation
2. Remove the sticker C (Figure 8c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 8d. a. Insert the CPU.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 8d). b. Turn the release latch to-
wards the lock symbol.
5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws (page 2 - 9). c. Remove the sticker from
the heat sink and insert
a. c. the heat sink.
d. Tighten the screws.
A
C 2
.D
i
s
a
s
s
e
m
b
l
y
b. d.
3 D
B

2 Note:
A. CPU
Tighten the as
in the order screws
indi-
D. Heat Sink
cated on the label. • 3 Screws
Removing and Installing a Processor 2 - 13
Disassembly
Figure 9 Removing the 3G Module
3G Module Removal
1. Turn of f the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
2. The 3G module will be visible at point 1 on the mainboard (Figure 9a).
a. Locate the 3G module.
b. Disconnect the cable
3. Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 9b).
and remove the screw. 4. The 3G module 4 (Figure 9c) will pop-up, and you can remove it from the computer (Figure 9d).
c. Remove the 3G module.
a. c. d.
Note: Make sure you
reconnect the antenna
cable to socket ( Fig-
ure 9b).
y
l 4
b
m
e
s
s
a
s
i
D 1
.
2 no 3g
b.
4
2
4. 3G Module
• 1 Screw
3
2 - 14 Removing the 3G Module
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf Disassembly 38/96

8/18/2019
Removing the Wireless LAN Moduleclevo+6-71-w24h0-d02a.unlocked.pdf Figure 10
Wireless LAN
1. Turn of f the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Module Removal
2. The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a).
3. Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b).
a. Locate the WLAN.
4. The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer (Figure 10d). b. Disconnect the cables
and remove the screw.
c. c. The WLAN module will
a. pop up.
d. Remove the Wireless
LAN module.
Note: Make sure you 2

reconnect the antenna
.D
5
cable to the “1 + 2”
i
s
socket ( Figure 10b).
a
s
s
e
1
m
b
l
y
b. d.
4
5
3
5.Wireless LAN Module
2 • 1 Screw
Removing the Wireless LAN Module 2 - 15
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf
Disassembly 39/96
Figure 11 Removing the Bluetooth Module
Bluetooth Module 1. Turn of f the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
Removal 2. The Bluetooth module will be visible at point 1 on the mainboard (Figur e 11a).
3. Remove screw 2 (Figu re 11b) and turn the module over (Figur e 11c).
a. Locate the Bluetooth 4. Carefully disconnect the cable 3 and separate the connector 4 (Figur e 11c) from the Bluetooth Module.
module.
5. Lift the Bluetooth Module 5 (Figu re 11d) up and off the computer.
b. Remove the screw and
turn the module over.
c. Disconnect the cable a. c. d.
and the connector from
the Bluetooth module.
d. Lift the Bluetooth module
out. 3
y
l
b
m
e
s
s
a
s
i 4
D
. 1
2
b.

5. Bluetooth Module
2
• 1 Screw
2 - 16 Removing the Bluetooth Module
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf Disassembly 40/96

8/18/2019 Removing the Keyboard clevo+6-71-w24h0-d02a.unlocked.pdf Figure 12
Keyboard Removal
1. Turn of f the computer, and remove the battery (page 2 - 5).
2. Remove screws 1 - 2 from the bottom of the computer. Press at point 3 to unsnap the LED cover module (you a. Remove screws from the
may need to use a small screwdriver to do this Figure 12a). bottom of the computer.
b. Turn the computer over,
3. Turn the computer over, unsnap up the LED cover module 4 from point 5 on the left of the computer, towards the
unsnap up the LED cov-
right (Figure 12b). er module from point 5
4. Remove screws 6 - 10 from the keyboard (Figure 12c). towards the right .
5. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable 11 . Disconnect the keyboard c. Remove screws from
ribbon cable 11 from the locking collar socket 12 (Figure 12d) the keyboard.
6. Carefully lift up the keyboard 13 (Figure 12e) off the computer. d. Carefully lift the key-
board up and disconnect
a. d. the keyboard ribbon ca-
ble from the locking col-
11 2
lar socket. .D
e. Remove the keyboard.
12
i
s
1 3 2 a
s
b.
s

e
5
m
Re-Inserting the b
4 Keyboard
l
y
e.
When re-inserting the
keyboard firstly align the
four keyboard tabs at the
bottom (Figure 12c) at
the bottom of the key-
c. board with the slots in the
case.
6 7 8 9 10
13

4. LED Cover Module
13. Keyboard
• 7 Screws
Keyboard Tabs
Removing the Keyboard 2 - 17
Disassembly
y
l
b
m
e
s
s
a
s
i
D
.
2
2 - 18
8/18/2019 Appendix A:Part Lists clevo+6-71-w24h0-d02a.unlocked.pdf
This appendix breaks down the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook’s construc-

tion into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings.
Note: This section

to cross-check any indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the A
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers. .P
a
r
t
L
i
s
t
s
A - 1
8/18/2019 Part Lis t Illustration Location
clevo+6-71-w24h0-d02a.unlocked.pdf
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
E5120Q/E5120Q-C/E5125/
Location Part
E5125-C/E5128Q/E5128Q-C
Top (E5120Q) page A - 3

Top (E5125) page A - 4
Top (E5128Q) page A - 5
Bottom page A - 6
s
t
s
i
DVD Dual Drive page A - 7
L
t
r
LCD page A - 8
a
P
.
A
A - 2
8/18/2019 Top (E5120Q) clevo+6-71-w24h0-d02a.unlocked.pdf
Figure A - 1 A
Top (E5120Q) .P
a
r
t
L
i
t
s
s
非耐落
灰色
Top (E5120Q) A - 3
8/18/2019
Top (E5125) clevo+6-71-w24h0-d02a.unlocked.pdf
Figure A - 2
s
t Top (E5125)
s
i
L
t
r
a
P
.
A
非耐落
灰色
A - 4 Top (E5125)
8/18/2019
Top (E5128Q) clevo+6-71-w24h0-d02a.unlocked.pdf
Figure 3 A
Top (E5128Q) .P
a
r
非耐落
t
L
非耐落
非耐落
i
t
s
s
非耐落
非耐落
灰色
灰色
非耐落
灰色
Top (E5128Q) A - 5
8/18/2019
Bottom clevo+6-71-w24h0-d02a.unlocked.pdf
Figure A - 4
s
t Bottom
s
i
L
t
r
a
P
.
A
A - 6 Bott om
DVD Dual Driv e
Figure A - 5
DVD Dual Drive
A
.P
a
r
t
L
i
非耐落
t
s
s
志精
DVD Dual Drive A - 7
LCD
Figure A - 6
s
t LCD
s
i
頭厚
L
非耐落
t
r
非耐落
頭厚
a
P
.
A
A - 8 LCD
Schematic Diagrams
8/18/2019
Appendix B: Schematic Diagrams clevo+6-71-w24h0-d02a.unlocked.pdf
This appendix has circuit diagrams of the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C notebook’s PCB’s.

The following table indicates where to find the appropriate schematic diagram.
Table B - 1
SCHEMATIC
Diagram - Page Diagram - Page Diagram - Page
DIAGRAMS
System Block Diagram - Page B - 2 IBEXPEAK - M 2/9 - Page B - 16 LED, MDC, BT - Page B - 30 B
.
Clock Generator - Page B - 3 IBEXPEAK - M 3/9 - Page B - 17 USB, Fan, TP, Multi-Conn - Page B - 31 S
c
CPU 1/7 (DMI, PEG, FDI) - Page B - 4 IBEXPEAK - M 4/9 - Page B - 18 5VS, 3VS, 1.5VS - Page B - 32 h
e
CPU 2/7 (CLK, MISC, JTAG) - Page B - 5 IBEXPEAK - M 5/9 - Page B - 19 Power 3.3V/5V - Page B - 33 m
a
CPU 3/7 (DDR3) - Page B - 6 IBEXPEAK - M 6/9 - Page B - 20 Power 1.5V/0.75V, 1.8VS - Page B - 34 t
i
c

CPU 4/7 (Power) - Page B - 7 IBEXPEAK - M 7/9 - Page B - 21 Power 1.1VS_VTT - Page B - 35
D
CPU 5/7 (Graphics Power) - Page B - 8 IBEXPEAK - M 8/9 - Page B - 22 Power VGFX_Core - Page B - 36
a
i
Version Note g
CPU 6/7 (GND) - Page B - 9 IBEXPEAK - M 9/9 - Page B - 23 V-Core - Page B - 37 r
The schematic dia-
a
CPU 7/7 (RESERVED) - Page B - 10 New Card, Mini PCIE - Page B - 24 AC_IN, Charger - Page B - 38 m
grams in this chapter
DDR3 SO-DIMM_0 - Page B - 11 3G, CCD, TPM - Page B - 25 Click Board - Page B - 39
s
are based upon ver-
DDR3 SO-DIMM_1 - Page B - 12 Card Reader/LAN JMB251C - Page B - 26 Audio Board/USB - Page B - 40
sion 6-7P-E51Q5-003.
If your mainboard (or
LVDS, Inverter - Page B - 13 LAN (JMC251C), SATA HDD, ODD - Page B - 27 Power Switch & LED Board - Page B - 41 other boards) are a la-
HDMI, CRT - Page B - 14 Audio Codec VIA1812 - Page B - 28 External ODD Board - Page B - 42
ter version, please
check with the Service
IBEXPEAK- M 1/9 - Page B - 15 KBC-ITE IT8502E - Page B - 29 Center for updated di-
agrams (if required).
B - 1
Schematic Diagrams
System Block Diagram
CLICK BOARD
POWER
6-71-E51Q2-D01A Calpella System Bl ock Diagram VDD3,VDD5
SWITCH BOARD 14.318 MHz

POWER SWITCH+HOTKEY X 3 POWER GPU 1.8VS
6-71-E51QS-D01A Clock Generator
RTM875N-632-VB-GRT
Memory Termination
AUDIO BOARD Arrandale 800/1067 MHz 5V,3V,5VS,3VS,1.5VS,
USB+EARPHONE+EXT.MIC DDR3 / 1.5V
6-71-C4508-D02A
PROCESSOR DDRIII
SO-DIMM0
EXTERNAL ODD BOARD rPGA989/988 SYSTEM SMBUS 1.5V,0.75VS(VTT_MEM)
EXT. ODD
0.1"~13 DDRIII
6-71-E51QN-D01
SO-DIMM1
SHEET 11 VCORE 1.1VS_VTT
s FDI DMI*4
m HDMI
a 0.5"~6.5" <=8"
r
g <15" AUDIO BOARD
a
i Sheet 1 of 42
CLICK BOARD
TOUCH PAD CRT C ONNECTOR
CRT SWITCH
INTERNAL
GRAPHICS Ibex Peak-M
D System Block Synaptic
810602-1703 Platform RJ-11
MIC
IN
HP
OUT
c
i Diagram
LCD CONNECTOR, <8"
LVDS SWITCH
INTERNAL
Controller
t GRAPHICS
a Hub (PCH)

AZALIA INT SPK R
m 32.768 KHz

MDC AMP
MODULE N7101
e
EC SPI TPM Azalia Codec
h ITE 8502E VIA VT1812 INT SPK L
c
128pins LQFP
MDC CON
14*14*1.6mm 33 MHz
S
. LPC 27x27mm INT MIC
B 0.5"~11" BIOS

SPI
1071 Ball FCBGA AZALIA LINK 24 MHz
INT. K/B EC SMBUS
PCIE 100 MHz <12"
THERMAL SMART SMART
SENSOR FAN BATTERY
32.768KHz
W83L771AWG
New Card Mini PCIE
3G CARD JMICRO
SOCKET SOCKET
USB2.0 (USB9) JMC251 C
SATA I/II 3.0Gb/s <12"
480 Mbps
(USB3) (USB2)
LAN CARD READER 25
1"~16"
MHz
7IN1
RJ-45
USB0 USB1 USB4 Bluetooth CCD SOCKET
SATA HDD SATA ODD
(USB11) (USB5)
AUDIO
BOARD
B - 2 System Block Diagram
Schematic Diagrams
Clock Generator
CLKGEN POWER
CLOCK GENERATOR
CL K _ V CC 1 CL K_ V CC 2 3 .3 V S
CL K _ VCC1
U7
1 15 L1 5 * 15 m i _l s ho rt_ 0 6
5 VD D_ DO T V DD_ S R C_ I/O 18
17 VD D_ 2 7 V D D _ C P U _ I/O C2 0 5 C 19 7 C2 07
24 VD D_ S RC
29 VD D_ CPU 3 0 .1u _ 1 6V _ Y5 V_ 0 4 0 .1 u_ 1 6 V_Y 5V _ 0 4 1u _ 6.3 V _ X5R _0 4
VD D_ REF D OT _ 96 4 C LK _B U F _D OT 9 6_ P 1 5
DO T_ 9 6# C LK _B U F _D OT 9 6_ N 15
6
27M 7
XO UT 27 2 7 M_ SS
XIN 28 XT AL _O UT
XT AL _IN 0.1uF near the every power pin
10
S RC _1 /SA T A 1 1 C LK _S AT A 1 5
S RC_ 1 #/S ATA# 13 C LK _S AT A# 1 5
30 S RC _2 14 C LK _P C IE_ ICH 1 5
15 CL K_ BUF _ R E F 14 R 13 4 3 3_ 0 4 REF _ 0 /CP U_ S EL C LK _PC IE_ ICH# 1 5
R E F _ 0/C PU_ S E L S R C_ 2# B
CL K _ SDAT A 31
SD A
.
CL K _ SCL K 32 16 CP U _S T O P # R 14 8 2 .2 1 K _ 1% _ 0 4
SC L CP U_ S T OP# 3 .3 V S 1 .1 V S_V TT
S
2 20 C LK _V C C2
VS S _D OT CPU _1
8 19
c
9 VS S _2 7 CP U_ 1# 23 L 14 * 1 5 m i l _ s h o r t_ 06
VS S _SA T A CPU _0 2 2 C LK _B U F _B CL K _P 15
12
21 VS S _SR C CP U_ 0# C LK _B U F _B CL K _N 1 5
h
C2 06 C1 9 6
26 VS S _C PU 25 CL K _ P W RG D
VS S _R EF CK P W RGD /P D# VDD_I /O c an be e
Sheet 2 of 42
33 0.1 u _ 16 V_ Y5 V _ 04 1 u_ 6 .3 V _X 5 R_ 0 4
G ND ranging from m
SL G 8S P5 8 5 3 .3 V S 1.05V to 3.3V
Sle go SLG8SP585 6-02-08585-EQ0

R 14 9
Clock Generator a
Realte k RTM875N-632- VB- GRT 0.1uF near the every power pin t
1 0 K_1 % _ 04 i
c
D
Q1 2 R 14 6 D
G
SMBus 36 CL KE N #
S
MT N7 00 2 Z HS3 1 M_ 0 4
Q1 1A
MT DN 70 0 2Z H S6 R EMI a
i
2
D S g
CL K _ SCL K
15 SMB _ CL K CL K _ S CL K 1 0 ,11
6-22-1 4R31- 1B7
6 1
6-22-1 4R31- 1B6
r
G 3 .3V S a
X1 HS X5 30G_ 1 4.31 818M Hz
5 VS 1 4 2 1
m
RN 15 XIN X OUT
2 3 2 .2K _ 4 P 2 R_ 04 R E F _ 0/C P U_ S EL C 19 4 * 1 0 p _5 0 V _ N P O _ 0 6
G
C1 99 C 20 2 s
3 4
CL K _ SDAT A
15 SMB _ DAT A CL K _ S DA TA 1 0 ,11
33 p _5 0V_ NP O_ 0 4 3 3 p_ 5 0 V _N PO_ 0 4 EMI Capactior
D S
5
Q1 1B
MT DN 70 0 2Z H S6 R
CPU_SEL_During CK_PEWGD Latch Pinl
3 .3V S
PIN _3 0 CPU_0 CP U_ 1
R 13 6 * 4. 7 K _0 4 RE F _0 /CP U _ S EL
0(default) 133MHz 133MHz
R 13 7 1 0K _ 0 4
1(0.7V-1.5V) 100MHz 100MHz 5VS 1 3 ,17 ,2 0,2 1 ,2 6,2 7 ,30,3 1,35 ,36
3.3 V 3 ,4 ,12 ,1 4,1 5 ,1 6,1 8,1 9,2 0 ,21 ,2 3 ,24,2 5 ,29 ,3 0, 31 ,3 3,3 4,3 5
3.3 VS 1 0 ,11 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 ,18 ,1 9 ,20 ,2 1 ,23 ,2 4,2 5 ,2 6,2 7 ,2 8,2 9 ,30 ,3 1 ,35,3 6
1.1 VS _ VT T 4 ,6 ,7 ,14 ,1 5 , 16 ,1 9, 20 ,2 1,3 4 ,3 5,3 6
Clock Generator B - 3
Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI)
PROCESSOR 1/7 ( DMI,PEG,FDI )

U 16 A
B2 6 20 mil PEG_ IR CO MP_ R R 20 9 4 9 .9 _ 1 % _ 04
P E G _ IC O M P I A2 6
A2 4 P E G _ IC O M P O B2 7
16 DM I_T XN0 C2 3 DM I_ RX# [0 ] PEG_ R CO MPO A2 5 EXP _R BIAS R 20 8 7 50 _ 1 % _0 4
16 DM I_T XN1 B2 2 DM I_ RX# [1 ] PE G _ RBI AS
16 DM I_T XN2 A2 1 DM I_ RX# [2 ] K3 5
16 DM I_T XN3 DM I_ RX# [3 ] PE G_ RX# [0 ] J34
B2 4 PE G_ RX# [1 ] J33
16 DM I_T XP0 D2 3 DM I_ RX[0 ] PE G_ RX# [2 ] G 35
16 DM I_T XP1 B2 3 DM I_ RX[1 ] D PE G_ RX# [3 ] G 32
16 DM I_T XP2 A2 2 DM I_ RX[2 ] M PE G_ RX# [4 ] F34
16 DM I_T XP3 DM I_ RX[3 ] I PE G_ RX# [5 ] F31
D2 4 PE G_ RX# [6 ] D 35
16 D MI_ R XN 0 G2 4 DM I_ T X# [0 ] PE G_ RX# [7 ] E3 3
16 D MI_ R XN 1 F23 DM I_ T X# [1 ] PE G_ RX# [8 ] C 33
16 D MI_ R XN 2 H2 3 DM I_ T X# [2 ] PE G_ RX# [9 ] D 32
16 D MI_ R XN 3 DM I_ T X# [3 ] PEG_ R X# [1 0 ] B3 2
s
D2 5 PEG_ R X# [1 1 ] C 31
16 D MI_ R XP 0 F24 DM I_ T X[0 ] PEG_ R X# [1 2 ] B2 8
16 D MI_ R XP 1 DM I_ T X[1 ] PEG_ R X# [1 3 ] B3 0
E2 3
16 D MI_ R XP 2 G2 3 DM I_ T X[2 ] PEG_ R X# [1 4 ] A3 1
m 16 D MI_ R XP 3 DM I_ T X[3 ] PEG_ R X# [1 5 ]
a
J35
P E G _ R X [0 ] H 34
r
P E G _ R X [1 ] H 33
E2 2 P E G _ R X [2 ] F35
g
16 F D I_ T XN 0 F D I_T X# [0 ] P E G _ R X [3 ] G 33
D2 1
16 F D I_ T XN 1 D1 9 F D I_T X# [1 ] P E G _ R X [4 ] E3 4
a
16 F D I_ T XN 2 D1 8 F D I_T X# [2 ] P E G _ R X [5 ] F32
i
16 F D I_ T XN 3 G2 1 F D I_T X# [3 ] P E G _ R X [6 ] D 34
16 F D I_ T XN 4 E1 9 F D I_T X# [4 ] P E G _ R X [7 ] F33
16 F D I_ T XN 5 F21 F D I_T X# [5 ]
S P E G _ R X [8 ] B3 3
D C
16 F D I_ T XN 6 G1 8 F D I_T X# [6 ] I P E G _ R X [9 ] D 31
Sheet 3 of 42 16 F D I_ T XN 7 F D I_T X# [7 ] n
I
H
PE G_ RX[1 0 ] A3 2
PE G_ RX[1 1 ] C 30
c
t
PE G_ RX[1 2 ]
D2 2
P A2 8
i
16 F D I_ T XP0
e
CPU 1/7 C2 1 F D I_T X[0 ]
A
PE G_ RX[1 3 ] B2 9
t
16 F D I_ T XP1 F D I_T X[1 ]
l PE G_ RX[1 4 ]
D2 0 A3 0
16 F D I_ T XP2
R
C1 8 F D I_T X[2 ]
( PE G_ RX[1 5 ]
G
a
16 F D I_ T XP3 F D I_T X[3 ]
G2 2
R L33
(DMI, PEG, FDI) 16

16
F D I_ T
F D I_ T
XP4
XP5
E2 0
F20
F D I_T X[4 ]
F D I_T X[5 ]
)
-
PEG _ TX# [0 ]
PEG _ TX# [1 ]
M 35
M 33
16 F D I_ T XP6 F D I_T X[6 ]
- PEG _ TX# [2 ] M 30
m
G1 9
F
16 F D I_ T XP7 F D I_T X[7 ] D PEG _ TX# [3 ] L31
I S
It applies to Auburnd
ale and Cl arksfi eld discrete graphic designs. F17 PEG _ TX# [4 ] K3 2
16 F DI_ F SY NC 0 E1 7 F D I_F SYN C[0 ] PEG _ TX# [5 ] M 29
16 F DI_ F SY NC 1 F D I_F SYN C[1 ] PEG _ TX# [6 ]
S
e
If discrete graphic chip is used for Auburndale, VAXG(GFX core) rail can beconnected J31
E
h
to GNDif motherboardonly supports discrete graphics andal soi na com mon C1 7 PEG _ TX# [7 ] K2 9
motherboarddesign if GFXVRis notst uff ed. Onthe otherhand , if the VR is stuff ed, 16 F DI_ IN T F D I_IN T R PEG _ TX# [8 ] H 30
c VAX G canbe l eft fl oati ngi n a comm

on m
otherboard design( Gfx VRkeeps VAXGfrom F18 P PEG _ TX# [9 ] H 29
fl oating).
16 F DI_ L SYN C0 D1 7 F D I_L SY NC [0 ]
X PE G_ T X# [1 0 ] F 2 9
E
S
16 F DI_ L SYN C1 F D I_L SY NC [1 ] PE G_ T X# [1 1 ] E2 8
In addition, FDI_RXN_[7: 0] andFDI_RXP_ [7: 0] canbe left fl oatingon the PCH
.
.
PE G_ T X# [1 2 ] D 29
FDI_TX[7:0] andFDI_ TX#[7:0] canbe left fl oati ng on the Auburndale.
TheGFX _I MO
N, FDI_ FSYNC[0], FD
I_ FSYNC[1], FDI_ LSYNC[0], FDI_LSYNC[1], and I PE G_ T X# [1 3 ] D 27
C PE G_ T X# [1 4 ] C 26
B
FDI_INTsi gnals should bet i edt o GND(thr ough 1 K ? %resistors) in t hecommon PE G_ T X# [1 5 ]
motherboarddesign case. Please not that if these signals are lef t fl oati ng, the
re are no P L34
PEG _T X[0 ] M 34
f uncti onal i mpacts but a small amount of po w
er (~15 m
W) maybe wasted. VAXG_SENSE PEG _T X[1 ] M 32
andVSSAXG_SENSEon Auburndale can be left as noconnect. PEG _T X[2 ] L 3 0
DPLL_REF_SSC LK andDPLL_REF_SSCLK#can be c onnected to GND on Auburndale PEG _T X[3 ] M 31
directly i f motherboard only supports dis crete graphics. I n a comm
on motherboard PEG _T X[4 ] K3 1
PEG _T X[5 ] M 28
design, t hese pins are driven via PCH(even if G
raphics is disabled by BIOS) thus no
PEG _T X[6 ] H 31
external terminati oni s required. PEG _T X[7 ] K2 8
PEG _T X[8 ] G 30
PEG _T X[9 ] G 29
PEG _ TX[1 0 ] F28
PEG _ TX[1 1 ] E2 7
Thermal Sensor near U16 PEG _ TX[1 2 ] D 28
PEG _ TX[1 3 ] C 27
PEG _ TX[1 4 ] C 25
PEG _ TX[1 5 ]
PZ 9 8 9 2 7-3 6 4 1 -01 F
3 .3 V
Analog Thermal Sensor

3 .3 V
C 35 7 R 2 28 * 1 0 m i l _s ho rt _ 04 C RIT _ TE MP_ RE P# 19
Q 14
* 0.1 u _ 16 V_ Y 5V _0 4 2 1 1:2 (4mils:8mils)
VCC OU T T HER M_ VO L T 2 8
T HER M_ AL ER T # 2 8 4 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9 ,20 ,2 1 , 2 3,2 4 ,2 5 ,2 9,3 0 ,3 1 ,33 ,3 4 ,3 5 3.3 V
U1 8
1 4 C A C359 3 C3 6 0
2 VDD T HE RM 6 P M _ E X T T S #_ E C 4 GN D
C D+ AL ER T D1 6 * C D B U 0 03 4 0 0 .1 u _ 16 V_ Y 5V _0 4 0. 1u _ 1 6V _Y 5 V_ 04
B G7 1 1 ST9 U
1
Q 10 3
*2 N3 9 0 4 3 7
E 5 D- SDA TA 8 S M D _ C P U _ T H E R M 1 5 ,2 8
GN D SC LK S M C _ C P U _ T H E R M 1 5 ,2 8
*W 8 3 L 7 71 AW G PLACE NEAR U16 2
B - 4 CPU 1/7 (DMI, PEG, FDI)
Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
PROCESSOR 2/7 ( CLK,MISC,JTAG )
1.5 V
Processor Compensation
R 2 03
Signals * 1 K_ 1% _ 0 4
R 23 8 4 9 . 9 _ 1% _ 0 4 H_ CO MP 0 R 20 6 * 10 m il_ s h ort_ 0 4
R 21 3 4 9 . 9 _ 1% _ 0 4 H_ CO MP 1 DDR3 Compensation Signals BSS138( VGS 1.5V )
SM _R CO MP_ 0 R 22 9 1 0 0 _ 1% _ 0 4 Q1 3
*R J U0 0 3N 0 3T 1 0 6
SM _R CO MP_ 1 R 23 0 2 4 . 9 _ 1% _ 0 4 SM_ DR AMR ST # S D
DD R3 _ DR AM RST # 1 0,1 1
R 2 37 2 0 _ 1% _ 0 4 H_ CO MP 2 SM _R CO MP_ 2 R 23 1 1 3 0 _ 1% _ 0 4
R 2 36 2 0 _ 1% _ 0 4 H_ CO MP 3 R2 0 7
*1 0 0K _1 % G
_ 04
DR AMR ST _C T RL 9 ,1 9
TRACE WIDTH 10MIL, LENGTH <500MILS
C3 1 1 ? ? IBEXCONTR
OL
*4 7 n _5 0 V_ 0 4
U 1 6B B
H_ C OM P3 A T2 3
C OM P3 A1 6
M BC L K BCL K_ CP U_ P 1 9
H_ C OM P2 A T2 4 B1 6
Processor Pullups C OM P2 I BCL K# BCL K_ CP U_ N 1 9
.
S
H_ C OM P1 G1 6 S AR 30
C OM P1 BCL K_ IT P AT 3 0
1 .1 VS_ VT T H_ C OM P0 A T2 6
C S BCL K_ IT P#
c
R 21 9 4 9 . 9 _ 1% _ 0 4 H_ CA TER R# AH2 4
C OM P0
K
C
PEG _C L K
PEG _ CL K#
E1 6
D 16 CL K_ EXP_ P 1 5
CL K_ EXP_ N 1 5 Sheet 4 of 42 h
O
SKT O CC # A1 8
CPU 2/7
DPL L _ REF _ SSC L K CL K_ DP_P 15
e
T L
R 2 39 6 8 _ 04 H_ PR OC HO T# _ D A1 7
AK1 4 DP LL _ RE F _S SCL K # CL K _ DP _ N 1 5
H_ C AT ERR #
m
R 2 47 * 68 _ 0 4 H_ CP UR ST# C ATE RR #
H C
A T1 5
E SM_ D RAM RST #
F6 S M_ DR AMR ST #
1.1 VS_ VT T
(CLK, MISC, JTAG) a
19 ,2 8 H_ PEC I PEC I R AL 1 S M_ RC OM P_ 0 t
M SM_ RC OM P[0 ] AM 1 S M_ RC OM P_ 1 R 23 3 10 K _ 0 4
SM_ RC OM P[1 ] AN 1
A S M_ RC OM P_ 2 R5 4 10 K _0 4
i
c
SM_ RC OM P[2 ]
3 6 H_ PRO CH OT #
R 24 8 * 10 m i _l s h ort_ 0 4 H_ PRO CH OT # _ D AN2 6
PR OC HO T# L 3 C AN 15 P M_ EXTT S# [0 ]
I f PROCHOT# is not used, then it must be terminated R S P M_ EXT_ T S# [0 ] AP1 5 P M_ EXTT S# [1 ]
R5 3
R 23 2
*0 _0 4
* 0_0 4
PM _EXT T S# _E C 3
D I T S# _D IMM 0 _1 1 0 ,1 1
witha 50-O pull -up resistor to VTT
_ 1.1 rail.
P M_ EXT_ T S# [1 ]
D
1 9 H_ T HR MT R IP#
AK1 5 D M R 23 4 * 1 2 . 4 K_ 1 % _ 0 4
T HER MT R IP#
AT 2 8 a
i
P RD Y # AP2 7 XD P_ PREQ # g
P RE Q #
AN 28 XD P_ TC L K
T C K AP 2 8
H_ C PUR ST # AP2 6 XD P_ TM S
r
R ESET _O BS# P T M S AT 2 7
XD P_ TR ST #
W T RST #
a
A L1 5 AT 2 9
M
XD P_ TD I_ R
1 6 H_ PM _ SYN C PM _S YN C
R T D I AR 27 XD P_ TD O_ R
m
P T DO
T DI _M
AR 29 XD P_ TD I_ M 1.1 VS_ VT T
B
R 24 9 * 0 _0 4 SY S_ AGEN T_ PW RO K AN1 4 AP2 9 XD P_ TD O_ M
1 6,3 6 D ELA Y_ PW R GD VC CPW R GO OD _ 1
M
A T DO _M XD P_ T MS R 25 2 * 51_ 0 4
s
R 25 0 * 10 m il_ s ho rt_ 0 4 AN 25 XD P_ T DO _M R 24 4 51 _ 0 4
&
AN2 7
N DB R# XD P_ T DI_ R R 25 1 * 51_ 0 4
19 H _C PU PW RG D VC CPW R GO OD _ 0 XD P_ PRE Q#
A R 24 2 * 51_ 0 4
AJ 2 2 XD P_ T DO _R R 24 1 * 51_ 0 4
G
AK1 3
G B PM# [0 ] AK2 2
1 6 PM_ D RAM _ PW RG D R 52 * 10 m il_ s ho rt_ 0 4 VD DPW R GO OD _ R
SM _D RA MPW R OK B PM# [1 ]
A
E AK2 4
B PM# [2 ] AJ 2 4
T B PM# [3 ]
AM1 5
M AJ 2 5
16 H _V TT PW R GD
J
VT T PW R GOO D E B PM# [4 ] AH 22
B PM# [5 ] AK2 3 XD P_ T CL K
Connect to the P rocessor (VTTPWRGOOD) VTT_1.1 VR pow er N R 24 5 * 51_ 0 4
goodsi gnal to processor. Si gnal vol tage level is 1.1 V. H_ P W RG D_ X DP AM2 6 B PM# [6 ] AH 23 XD P_ T RST # R 24 0 51 _ 0 4
T APPW R GO OD T B PM# [7 ]
R 60 1 . 5 K _ 1 % _ 04 PL T _R ST # _R A L1 4
1 8 ,23 ,2 5 ,2 8 B UF _ PL T _R ST # R STI N#
Signal fromPCHt oPr ocessor
Connect to PCH( PLT_RST#) R 61
(need s to be level translated 7 5 0 _1 % _ 04 PZ 98 9 2 7-3 6 4 1 -01 F
fr o m3 . 3 V t o 1 . 1 V ) .
XD P_ T DO _M R 24 3 * 10 m il_ s h ort_ 0 4XDP_ T DI_ M

1 .5 VS_ CPU
3.3 V
R5 0
1 .1 K_1 % _ 0 4 R 2 35 * 8. 2 K _ 04
3 .3V 3 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9,2 0 ,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3 ,3 4,3 5
VD DPW R GO OD _ R
5 1 .5V 9 ,1 0,11 ,2 1 ,23 ,2 7 ,2 9,3 1 ,3 3 ,36
U17 1 .5V S_C PU 7,3 1
1 IN 3 .3V
4 1 .1V S_V TT 2 ,6 ,7 ,1 4,1 5 ,1 6, 19 ,2 0 ,2 1,3 4 ,3 5, 36
R6 2 R 24 6 * 1 . 5 K _ 1 % _ 04 DRA MPW R GD _ CPU
2
1 .1 VS_ VT T _P W RG D 1 6 ,3 3 ,34
3 K_ 1% _ 0 4
3
* MC 7 4VH C1 G 08 D F T 1G
Intel change
4.75K -->1.1K
12K -->3K
CPU 2/7 (CLK, MISC, JTA G) B - 5
Schematic Diagrams
CPU 3/7 (DDR3)
8/18/2019
PROCESSOR
clevo+6-71-w24h0-d02a.unlocked.pdf 3/7 ( DDR3 )
U16C
U16D
AA6
SA_CK[0] AA7 M_CLK_DDR0 10 W8
10 M_A_DQ[63:0] SA_CK#[0] M_CLK_DDR#0 10 11 M_B_DQ
[ 63
: 0] SB_CK[0] M_CLK_DDR2 11
P7 W9
SA_CKE[0] M_CKE0 10 SB_CK#[0] M_CLK_DDR#2 11
M_A_DQ0 A1
0 M_B_DQ0 B5 M3
SA_DQ[0] SB_DQ[0] SB_CKE[ 0] M_CKE2 11
M_A_DQ1 C1
0 M_B_DQ1 A5
M_A_DQ2 C7 SA_DQ[1] M_B_DQ2 C3 SB_DQ[1]
M_A_DQ3 A7 SA_DQ[2] Y6 M_B_DQ3 B3 SB_DQ[2] V7
B1 0 SA_DQ[3] SA_CK[1] Y5 M_CLK_DDR1 10 E4 SB_DQ[3] SB_CK[1] V6 M_CLK_DDR3 11
M_A_DQ4 M_B_DQ4
D1 0 SA_DQ[4] SA_CK#[1] P6 M_CLK_DDR#1 10 A6 SB_DQ[4] SB_CK#[1] M2 M_CLK_DDR#3 11
M_A_DQ5 M_B_DQ5
M_A_DQ6 E1 0 SA_DQ[5] SA_CKE[1] M_CKE1 10 M_B_DQ6 A4 SB_DQ[5] SB_CKE[ 1] M_CKE3 11
M_A_DQ7 A8 SA_DQ[6] M_B_DQ7 C4 SB_DQ[6]
M_A_DQ8 D8 SA_DQ[7] M_B_DQ8 D1 SB_DQ[7]
M_A_DQ9 F1 0 SA_DQ[8] AE2 M_B_DQ9 D2 SB_DQ[8]
SA_DQ[9] SA_C
S#[0] M_CS#0 10 SB_DQ[9]
M_A_DQ10 E6 AE8 M_B_DQ10 F2 AB8
F7 SA_DQ[10] SA_C
S#[1] M_CS#1 10 F1 SB_DQ[10] SB_CS#[0] AD6 M_CS#2 11
M_A_DQ11 M_B_DQ11
s
E9 SA_DQ[11] C2 SB_DQ[11] SB_CS#[1] M_CS#3 11
M_A_DQ12 M_B_DQ12
B7 SA_DQ[12] F5 SB_DQ[12]
M_A_DQ13 M_B_DQ13
M_A_DQ14 E7 SA_DQ[13] AD8 M_B_DQ14 F3 SB_DQ[13]
M_ODT
0 10
m
M_A_DQ15 C6 SA_DQ[14] SA_ODT[0] AF9 M_B_DQ15 G4 SB_DQ[14] AC7
SA_DQ[15] SA_ODT[1] M_ODT
1 10 SB_DQ[15] SB_ODT[0] M_ODT2 11
M_A_DQ16 H1 0 M_B_DQ16 H6 AD1
M_ODT3 11
a
M_A_DQ17 G 8 SA_DQ[16] M_B_DQ17 G2 SB_DQ[16] SB_ODT[1]
K7 SA_DQ[17] J6 SB_DQ[17]
r
M_A_DQ18 M_B_DQ18
M_A_DQ19 J8 SA_DQ[18] M_B_DQ19 J3 SB_DQ[18]
G 7 SA_DQ[19] G1 SB_DQ[19]
g
M_A_DQ20 M_B_DQ20 M_
B_DM[7:0] 11
M_A_DQ21 G1 0 SA_DQ[20] M_B_DQ21 G5 SB_DQ[20] D4 M_B_DM0
SA_DQ[21] M_A
_DM[7
: 0] 10 SB_DQ[21] SB_DM[0]
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ22 J2 E1 M_B_DM1
a M_A_DQ23 J1 0 SA_DQ[22] SA_DM[0] D7 M_A_DM1 M_B_DQ23 J1 SB_DQ[22] SB_DM[1] H3 M_B_DM2
i Sheet 5 of 42 M_A_DQ24 L7 SA_DQ[23] SA_DM[1] H7 M_A_DM2 M_B_DQ24 J5 SB_DQ[23] SB_DM[2] K1 M_B_DM3
M_A_DQ25 M 6 SA_DQ[24] SA_DM[2] M7 M_A_DM3 M_B_DQ25 K2 SB_DQ[24] SB_DM[3] AH1 M_B_DM4
D
M_A_DQ26 M 8 SA_DQ[25] SA_DM[3] AG6 M_A_DM4 M_B_DQ26 L3 SB_DQ[25] SB_DM[4] AL
2 M_B_DM5
CPU 3/7 L9 SA_DQ[26] SA_DM[4] AM7 M1 SB_DQ[26] SB_DM[5] AR4

M_A_DQ27 M_A_DM5 M_B_DQ27 M_B_DM6
M_A_DQ28 L6 SA_DQ[27] SA_DM[5] AN10 M_A_DM6 M_B_DQ28 K5 SB_DQ[27] SB_DM[6] AT
8 M_B_DM7
SA_DQ[28] SA_DM[6] SB_DQ[28] SB_DM[7]
c
M_A_DQ29 K8 AN13 M_A_DM7 M_B_DQ29 K4
i
SA_DQ[29] SA_DM[7] SB_DQ[29]
(DDR3)
M_A_DQ30 N8 M_B_DQ30 M4
SA_DQ[30] SB_DQ[30]
t
M_A_DQ31 P9 M_B_DQ31 N5
M_A_DQ32 AH 5 SA_DQ[31] M_B_DQ32 AF3 SB_DQ[31]
AF5 SA_DQ[32] A G1 SB_DQ[32]
a
M_A_DQ33 M_B_DQ33
AK6 SA_DQ[33] C9 M_A
_DQS#[7:0] 10 AJ3 SB_DQ[33] D5 M
_B_DQS
#[7:0] 11
M_A_DQ34 M_A_DQS#0 M_B_DQ34 M_B_DQS#0
AK7 SA_DQ[34] SA_DQS#[0] F8 AK1 SB_DQ[34] SB_DQS#[0] F4
M_A_DQ35 M_A_DQS#1 M_B_DQ35 M_B_DQS#1
M_A_DQ36 AF6 SA_DQ[35] A SA_DQS#[1] J9 M_A_DQS#2 M_B_DQ36 AG4 SB_DQ[35] SB_DQS#[1] J4 M_B_DQS#2
m
M_A_DQ37 AG 5 SA_DQ[36] SA_DQS#[2] N9 M_A_DQS#3 M_B_DQ37 AG3 SB_DQ[36] SB_DQS#[2] L4 M_B_DQS#3
M_A_DQ38 AJ7 SA_DQ[37]
Y SA_DQS#[3] AH7 M_A_DQS#4 M_B_DQ38 AJ4 SB_DQ[37] SB_DQS#[3] AH2 M_B_DQS#4
M_A_DQ39 AJ6 SA_DQ[38]
R SA_DQS#[4] AK9 M_A_DQS#5 M_B_DQ39 AH4 SB_DQ[38] SB_DQS#[4] AL4 M_B_DQS#5
e
O B
M_A_DQ40 AJ1 0 SA_DQ[39] SA_DQS#[5] AP11 M_A_DQS#6 M_B_DQ40 AK3 SB_DQ[39] SB_DQS#[5] AR5 M_B_DQS#6
h M
M_A_DQ41 AJ9 SA_DQ[40] SA_DQS#[6] AT13 M_A_DQS#7 M_B_DQ41 AK4 SB_DQ[40] SB_DQS#[6] AR8 M_B_DQS#7
M_A_DQ42 AL1 0 SA_DQ[41]
E
SA_DQS#[7]
M_B_DQ42 AM6 SB_DQ[41]
- SB_DQS#[7]
c
M_A_DQ43 AK1 2 SA_DQ[42] M_B_DQ43 AN2 SB_DQ[42]
SA_DQ[43] M SB_DQ[43]
M_A_DQ44 AK8 M_B_DQ44 AK5
Y
S
SA_DQ[44] SB_DQ[44]
M_A_DQ45 AL 7
M M_A
_DQS[7:0] 10
M_B_DQ45 AK2
R
.
SA_DQ[45] SB_DQ[45]
M_A_DQ46 AK1
AL
1
8 SA_DQ[46] E SA_DQS[0]
C8
F9
M_A_DQS0 M_B_DQ46 AM4
AM3 SB_DQ[46] O
M_A_DQ47
M_A_DQ48 AN 8 SA_DQ[47] T SA_DQS[1] H9
M_A_DQS1
M_A_DQS2
M_B_DQ47
M_B_DQ48 AP3 SB_DQ[47] M C5 M_B_DQS0
M
_B_DQS
[7: 0] 11
B M_A_DQ49 AM1 0 SA_DQ[48]

S SA_DQS[2] M9 M_A_DQS3 M_B_DQ49 AN5 SB_DQ[48] E SB_DQS[0] E3 M_B_DQS1
M_A_DQ50 AR1 1 SA_DQ[49]
Y SA_DQS[3] AH8 M_A_DQS4 M_B_DQ50 AT4 SB_DQ[49] M SB_DQS[1] H4 M_B_DQS2
SA_DQ[50] SA_DQS[4] SB_DQ[50] SB_DQS[2]
M_A_DQ51
M_A_DQ52
AL1
AM
1
9 SA_DQ[51] S SA_DQS[5]
AK10
AN11
M_A_DQS5
M_A_DQS6
M_B_DQ51
M_B_DQ52
AN6
AN4 SB_DQ[51] M SB_DQS[3]
M5
AG2
M_B_DQS3
M_B_DQS4
M_A_DQ53 AN 9 SA_DQ[52]
R
SA_DQS[6] AR13 M_A_DQS7 M_B_DQ53 AN3 SB_DQ[52]
E SB_DQS[4] AL
5 M_B_DQS5
M_A_DQ54 AT1 1 SA_DQ[53]
D
SA_DQS[7] M_B_DQ54 AT5 SB_DQ[53]
T SB_DQS[5] AP5 M_B_DQS6
M_A_DQ55 AP1 2 SA_DQ[54]
SA_DQ[55] D
M_B_DQ55 AT6 SB_DQ[54]
SB_DQ[55] S SB_DQS[6]
SB_DQS[7]
AR7 M_B_DQS7
M_A_DQ56
M_A_DQ57
AM1
AN1
2
2 SA_DQ[56]
M_B_DQ56
M_B_DQ57
AN7
AP6 SB_DQ[56] Y
M_A_DQ58 AM1 3 SA_DQ[57] Y3 M_A_A0
M_A
_A[15:0] 10
M_B_DQ58 AP8 SB_DQ[57] S
M_A_DQ59 AT1 4 SA_DQ[58] SA_MA[0] W1 M_A_A1 M_B_DQ59 AT9 SB_DQ[58]
M_A_DQ60 AT1 2 SA_DQ[59] SA_MA[1] AA8 M_A_A2 M_B_DQ60 AT7 SB_DQ[59] R
M_A_DQ61 AL1 3 SA_DQ[60] SA_MA[2] AA3 M_A_A3 M_B_DQ61 AP9 SB_DQ[60] D
M_A_DQ62 AR1 4 SA_DQ[61] SA_MA[3] V1 M_A_A4 M_B_DQ62 AR 10 SB_DQ[61] D M_
B_A[15:0] 1
1
M_A_DQ63 AP1 4 SA_DQ[62] SA_MA[4] AA9 M_A_A5 M_B_DQ63 AT1 0 SB_DQ[62] U5 M_B_A0
SA_DQ[63] SA_MA[5] V8 SB_DQ[63] SB_MA[0] V2
M_A_A6 M_B_A1
SA_MA[6] T1 M_A_A7 SB_MA[1] T5 M_B_A2
SA_MA[7] Y9 M_A_A8 SB_MA[2] V3 M_B_A3
AC 3 SA_MA[8] U6 M_A_A9 SB_MA[3] R1 M_B_A4
10 M_A_BS0 SA_BS[0] SA_MA[9] SB_MA[4]
AB2 AD 4 M_A_A10 AB1 T8 M_B_A5
10 M_A_BS1 U7 SA_BS[1] SA_MA[10] T2 11 M_B_BS0 W5 SB_BS[0] SB_MA[5] R2
M_A_A11 M_B_A6
10 M_A_BS2 SA_BS[2] SA_MA[11] U3 11 M_B_BS1 R7 SB_BS[1] SB_MA[6] R6
M_A_A12 M_B_A7
SA_MA[12] AG 8 11 M_B_BS2 SB_BS[2] SB_MA[7] R4
M_A_A13 M_B_A8
SA_MA[13] T3 M_A_A14 SB_MA[8] R5 M_B_A9
AE1 SA_MA[14] V9 M_A_A15 AC5 SB_MA[9] AB5 M_B_A10
10 M_A_CAS# SA_CAS# SA_MA[15] 11 M_B_CAS# SB_CAS# SB_MA[ 10]
AB3 Y7 P3 M_B_A11
10 M_A_RAS# SA_RAS# 11 M_B_RAS# SB_RAS# SB_MA[ 11]
AE9 AC6 R3 M_B_A12
10 M_A_WE# SA_WE# 11 M_B_WE# SB_WE# SB_MA[ 12] AF7 M_B_A13
SB_MA[ 13] P5 M_B_A14
SB_MA[ 14] N1 M_B_A15
SB_MA[ 15]
PZ98927-3641-0 1F
PZ98927-3641-0 1F
B - 6 CPU 3/7 (DDR3)
Schematic Diagrams
CPU 4/7 (Power)

CPU 4/7 (Power)
8/18/2019
PROCESSOR 4/7 ( POWER )
U 1 6F
PROCESSOR CORE POWER PROCESSOR UNCORE POWER

VC O RE 1 .1 V S_ V TT
48A AG 3 5 A H1 4 V TT TOTAL 2 1A
AG 3 4 V C C1 VT T 0_1 A H1 2
ICCMAX M
aximum Processor SV 48 V C C2 VT T 0_2
AG 3 3 A H1 1 C29 C3 0 C 3 24 C3 5 C 33 C301 C334
AG 3 2 V C C3 VT T 0_3 A H1 0
AG 3 1 V C C4 VT T 0_4 J14 1 0 u _ 6. 3V _X5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6 .3 V_ X5 R_ 0 6 2 2 u _ 6 .3V _ X5 R _ 0 8 2 2 u _ 6 .3 V_ X 5 R_ 0 8
V CO RE AG 3 0 V C C5 VT T 0_5 J13
AG 2 9 V C C6 VT T 0_6 H14
C3 2 3 C331 C335 C337 AG 2 8 V C C7 VT T 0 _ 7 H12
AG 2 7 V C C8 VT T 0 _ 8 G14
8 8 8 V C C9 VT T 0 _ 9
8
0 0
0
0
AG 2 6 G13
_ _ V C C1 0 V TT 0 _ 1 0
_ _ AF35 G12
R R R
R 5 AF34 V C C1 1 V TT 0 _ 1 1 G11
5 5 5
X X X V C C1 2 V TT 0 _ 1 2
X
_
_
V
_
V
_
V
AF33 F 14 C36 C303 C3 4 C3 2 8
ICCMAX_VTT Max Current
V 3 3 3 AF32 V C C1 3 V TT 0 _ 1 3 F 13
for VTT Rail
3
. . . .
6
6 6 6 AF31 V C C1 4 V TT 0 _ 1 4 F 12 1 0 u _ 6. 3V _X5 R _ 0 6 1 0 u _ 6 .3 V_ X5R _ 0 6 10 u _ 6 .3 V _ X5 R_ 0 6 *1 0 u _ 6 .3 V_ X 5R _ 0 6
_ _ _
_ u AF30 V C C1 5 V TT 0 _ 1 5 F 11
u u
u 2
2
2
2
2
AF29 V C C1 6 V TT 0 _ 1 6 E 14 SV 18
2 2 2
*
AF28 V C C1 7 V TT 0 _ 1 7 E 12
AF27 V C C1 8 V TT 0 _ 1 8 D14
AF26 V C C1 9 V TT 0 _ 1 9 D13 B
AD 3 5 V C C2 0 V TT 0 _ 2 0 D12
C3 4 2 C352 C329 C318 AD 3 4 V C C2 1 R V TT 0 _ 2 1 D11
AD 3 3 V C C2 2 E V TT 0 _ 2 2 C14 .
8 8 8 AD 3 2 V C C2 3 W V TT 0 _ 2 3 C13
O
8
0
_
0
_
0
_
0
_ AD 3 1 V C C2 4
P
V TT 0 _ 2 4 C12
S
R R
R R V C C2 5 V TT 0 _ 2 5
5 5 5 AD 3 0 C11
5 X
X
X
AD 2 9 V C C2 6 L V TT 0 _ 2 6 B 14 The decoupling capacitors, filter
I
X
_
_
V
_
_
V V C C2 7 V TT 0 _ 2 7
c
V AD 2 8 A B 12 recommendations and sense resistors on the
Sheet 6 of 42
V
3 3 3 3
. .
.
6
6 .
6
6 AD 2 7 V C C2 8 R V TT 0 _ 2 8 A 14
CPU/PCH Rails are specific to the CRB
_
_
u
_
u
_
u AD 2 6 V C C2 9 V TT 0 _ 2 9 A 13
h
u
2 2 2 2
AC 3 5 V C C3 0 V V TT 0 _ 3 0 A 12
2
*
2 2
*
2
V C C3 1 1 V TT 0 _ 3 1 Implementation. Customers need to follow the
.
CPU 4/7
AC 3 4 A 11
e
AC 3 3 V C C3 2 1 V TT 0 _ 3 2 recommendations in the Calpella Platform
AC 3 2 V C C3 3 1. 1V S_ V T T m
AC 3 1 V C C3 4 Design Guide
(Power)
AC 3 0 V C C3 5 AF10
C3 3 2 C356 C355 C354
AC 2 9 V C C3 6 V TT 0_33 A E1 0
8
0
_
8
0
_
8
0
_
8
0
_
AC 2 8 V C C3 7
V C C3 8 C
V TT
V TT
0_34
0_35
A C1 0 C304 C3 0 5 C3 1 2
a
R
AC 2 7 P A B1 0
R
5
R
5
R
AC 2 6 V C C3 9 U V TT 0_36 Y10
5
X X
_
X
5
X V C C4 0 V TT 0_37
2 2 u _ 6 .3 V_ X5R _ 0 8 22 u _ 6 .3 V_ X 5 R _ 0 8 2 2 u_ 6 .3 V_ X5 R _0 8
t
_ _ _ A A3 5 W 10
C
V
V
V V A A3 4 V C C4 1 V TT 0_38 U10
i
3
3
. 3 3 O
1.1VS_VTT
.
6
_
6
_
.
6
_
.
6
_
A A3 3 V C C4 2
R
V TT 0_39 T10
c
u
u
2
u
2
u
2
A A3 2 V C C4 3 E V TT 0_40 J12
2
2 2 2 2 A A3 1 V C C4 4 V TT 0_41 J11
* *
A A3 0 V C C4 5 S V TT 0_42 J16
Please note that the D
V C C4 6 U V TT 0_43
+ VT T_ 4 3 R 216 * 15 m li _ s h o rt_ 0 6
A A2 9 P J15 + VT T_ 4 4 R 215 * 15 m il _ s h o rt_ 0 6 VTT Rail Values are
A A2 8 V C C4 7 P V TT 0_44
A A2 7 V C C4 8 L
A A2 6 V C C4 9 Y
V C C5 0
Auburndale VTT=1.05V
Y3 5
Y3 4 V C C5 1
a
i
g
Y3 3 V C C5 2 1 .1 V S_ VT T
V CO RE Y3 2 V C C5 3
V C C5 4
Y3 1
Y3 0 V C C5 5
1K PU to VTT and 1K P D to GND
r
a
Y2 9 V C C5 6 for POC
C3 4 8 C346 C345 C344 R 2 25
Y2 8 V C C5 7
6
6
0
0
_
6
0
6
0
Y2 7 V C C5 8 VCORE * 1 K_ 1% _ 0 4
m
_ _ _ Y2 6 V C C5 9
R R R R V C C6 0
5 V3 5 A N3 3 PSI #
5 5 5
X X X V C C6 1 P SI# P SI # 36
X _ V3 4
_ _ _
V
3
V
3
.
V
3
.
V
3
.
V3 3 V C C6 2 1 .1 V S_ VT T
s
. V3 2 V C C6 3 A K3 5
6 6
_ 6 6 R 2 26
R
_ u _ _ V C C6 4 VID [0 ] H _V ID0 3 6
u
0
u u V3 1 A K3 3
0 0 0 V C C6 5 VID [1 ] H _V ID1 3 6
1 V3 0 A K3 4 1 K_ 1 % _ 0 4
1 1 1
E
* * H _V ID2 3 6
V2 9 V C C6 6 VID [2 ] A L3 5 R2 2 3
V2 8 V C C6 7 VID [3 ] A L3 3 H _V ID3 3 6
V2 7 V C C6 8
V C C6 9 W D
S
I
VID [4 ]
VID [5 ]
A M3 3 H
H
_V
_V
ID4
ID5
3
3
6
6
1 K_ 1 % _0 4
O V
V2 6 A M3 5
U35 V C C7 0 VID [6 ] A M3 4 H _V ID6 3 6
C3 2 6 C325 C327 C347
V C C7 1 PR O C_ D PR S L PVR PM _ DP RS LP V R 3 6
P U
U34
6 6 V C C7 2
6 U33
6
0
0
_
0
_
0
V C C7 3 P
_
R
R
5
R
5
_
R
U32
U31 V C C7 4
C G15
R2 2 2
5 H _ VT T V ID1
5
X X X V C C7 5 VT T _ SE L EC T
X _ U30
_ _ *1 K_ 1 % _ 0 4
_ V V V
V
3 3 3 U29 V C C7 6
3 . . .
. V C C7 7
6 6 6 U28
6 _
_ _ V C C7 8
_ u u u U27
u 0 0
0 V C C7 9
0 1 1 U26
1 1
* *
R35 V C C8 0
R34 V C C8 1 TO V
CORE POW
ER CONT
ROL
R33 V C C8 2
R32 V C C8 3 A N3 5
V C C8 4 ISE N S E IM O N 36
C3 4 0 C339 C338 C333 R31
4 R30 V C C8 5
0
4
6 _ 6 R29 V C C8 6
0 0 R 0
_ V C C8 7
_ 7 _ R28 A J3 4
R X R VC C _ S EN SE 3 6
S
R V C C8 8 VC C_ SE NS E
5 _ 5 R27 A J3 5
7
E
X V X VS S _ SEN S E 36
X R26 V C C8 9 VSS_ SE NS E
_ 0 _
_
V V 5 V
P3 5 V C C9 0 N
I
3 _ 3
0 . .
u V C C9 1
1
_
6
_
1
0
6
_
P3 4
P3 3 V C C9 2
L V T T _SE NS E
B 15
A 15 V T T_ S E N S E 3 4
u
1 u . u
E
0 0 0 V C C9 3 VSS _S E N SE_ V T T
. P3 2
0 1 1
P3 1 V C C9 4
V C C9 5 S
N
P3 0 E
P2 9 V C C9 6
V C C9 7
S VCOR E 36
P2 8
V C C9 8 1 .1V S_ V T T 2 ,4 ,7 ,1 4 ,1 5 ,1 6,1 9 ,2 0 ,2 1 ,3 4 , 3 5 ,3 6
P2 7
P2 6 V C C9 9
V C C1 0 0
PZ 98 9 2 7 -3 6 4 1- 01 F
CPU 4/7 (Power) B - 7
Schematic Diagrams
CPU 5/7 (Graphics Power)
PROCESSOR 5/7 ( GRAPHICS POWER )
VG F X_ CO RE U 1 6G
AT 2 1
AT 1 9 VAXG 1 AR2 2
C364 C 34 9 AT 1 8 VAXG 2 VAXG _ SEN SE AT 2 2 G P UVC C SEN SE 3 5
VAXG 3 VSSAXG _ SEN SE G P UVS SSEN SE 35
9 AT 1 6
. E S
5
* 1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _6 .3 V_ X5 R _0 6 AR 2 1 VAXG 4 S E
6
. AR 1 9 VAXG 5 N N
6
* VAXG 6 E I
6
AR 1 8 S L
. VAXG 7
6 AR 1 6 AM2 2
_ DF GT _ VID _ 0 3 5
V
A P2 1 VAXG 8 GF X_ VI D[0 ] AP2 2
5 VAXG 9 GF X_ VI D[1 ] DF GT _ VID _ 1 3 5
. A P1 9 AN2 2
2
_ A P1 8 VAXG 10 s GF X_ VI D[2 ] AP2 3
DF GT _ VID _ 2 3 5
u
A P1 6 VAXG 11 D GF X_ VI D[3 ] AM2 3 DF GT _ VID _ 3 3 5
s
0 C 3 50 C3 6 2
6
AN 2 1 VAXG 12 I GF X_ VI D[4 ] AP2 4 DF GT _ VID _ 4 3 5
5 +
AN 1 9 VAXG 13 G V GF X_ VI D[5 ] AN2 4
DF GT _ VID _ 5 3 5
2 2 u _ 6. 3V _X5 R _ 08 2 2 u_ 6 .3 V_ X5 R_ 0 8
VAXG 14 R GF X_ VI D[6 ] DF GT _ VID _ 6 3 5
m
AN 1 8
1 AN 1 6 VAXG 15 A S
7
3 AM 2 1 VAXG 16 P C AR2 5 1 .1 VS_ VT T
a
C
AM 1 9 VAXG 17 H I G F X_ VR _E N AT 2 5 GF XVR _ D PRS LP VR R 36 1 * 1K _ 0 4
D F GT _VR _ EN 35
I H
r
AM 1 8 VAXG 18 G F X_ DP RSL PV R AM2 4 T P_ GF X_ IM ON R 45 1 00 _ 1 % _ 0 4
AM 1 6 VAXG 19 C P GF X_ IM O N GF X_ IM O N 3 5
S A
g
AL 2 1 VAXG 20
AL 1 9 VAXG 21 R
G
a
AL 1 8 VAXG 22 1. 5V S_ CP U
i Sheet 7 of 42 AL 1 6 VAXG 23

VAXG 24 VDDQ 6A
A K2 1 AJ 1
A K1 9 VAXG 25 V DD Q1 AF 1
D
VAXG 26 V DD Q2
CPU 5/7
A K1 8 AE7 C5 5 C3 3 6 C330 C6 1 C5 8
VAXG 27
S
A K1 6 V DD Q3 AE4
AJ 2 1 VAXG 28
L
V DD Q4 AC1
c
1u _ 6 .3 V_ X5 R_ 0 4 2 2 u_ 6 .3 V_ X5 R_ 0 8 2 2 u _ 6. 3V _ X5 R _ 08 10 u _ 6 .3 V_ X5 R_ 0 6 1 0 u_ 6 .3 V_ X5 R_ 0 6
Please note that the AJ 1 9 VAXG 29 V DD Q5
I
AB7
i (Graphics Power) VAXG 30

A
V DD Q6
VTT Rail Values are AJ 1 8 AB4
t
VAXG 31
R
AJ 1 6 V DD Q7 Y1
AH 2 1 VAXG 32 V DD Q8 W7
a AH 1 9 VAXG 33 V DD Q9
V
W4
Auburndale VTT=1.05V VAXG 34 VDD Q1 0
Clarksfield VTT=1.1V
AH 1 8
AH 1 6 VAXG 35
5 U1 C3 4 1 C3 4 3 C39 C6 0 + C5 3
.
VDD Q1 1 T7
R
m
VAXG 36 VDD Q1 2
1
T4 1u _ 6 .3 V_ X5 R_ 0 4 1 u _6 .3 V_ X5 R _0 4 1 u _ 6 .3 V_ X5R _ 0 4 1u _ 6 .3 V_ X5 R_ 0 4 10 0 u _ 6 .3 V_ B_ A
VDD Q1 3
E
P1
-
VDD Q1 4 N7
VDD Q1 5
N4
h
e W
VDD Q1 6 L1
O 3
J24 VDD Q1 7 H1
F
c
1 .1 VS_ VT T J23 VT T 1 _ 45 VDD Q1 8 1 .1 VS _V TT
D R
P
VT T 1 _ 46
H25 I
C3 1 4 C3 0 8
D
D
VT T 1 _ 47
S
.
22 u _ 6 .3 V_ X5 R_ 0 8 22 u _ 6 .3 V_ X5 R_ 0 8
VT T 0 _5 9
P1 0
N1 0
C3 2 0 C6 4
B
VT T 0 _6 0 L1 0 10 u _ 6 .3 V_ X5 R_ 0 6 1 0 u_ 6 .3 V_ X5 R_ 0 6
VT T 0 _6 1 K1 0
VT T 0 _6 2
1 .1 VS_ VT T
J2 2
K2 6
V
VT T 1 _6 3 J2 0
1 .1 VS_ VT T J27 VT T 1 _ 48 VT T 1 _6 4
1
J1 8 C3 1 5 C3 1 3
J26 VT T 1 _ 49 P VT T 1 _6 5
.
C3 0 6 C3 0 7 E H2 1
VT T 1 _ 50
1
VT T 1 _6 6
J25 G H2 0 22 u _ 6 .3 V_ X5 R_ 0 8 2 2 u_ 6 .3 V_ X5 R_ 0 8
22 u _ 6 .3 V_ X5 R_ 0 8 22 u _ 6 .3 V_ X5 R_ 0 8 H27 VT T 1 _ 51 VT T 1 _6 7 H1 9
1 .1 VS _V T T G28 VT T 1 _ 52 & VT T 1 _6 8
G27 VT T 1 _ 53
D
G26 VT T 1 _ 54 M 1 .8 VS
VT T 1 _ 55
F26 I VCCPLL 0.6A
E2 6 VT T 1 _ 56 L2 6
C3 0 9 C3 0 2 E2 5 VT T 1 _ 57 VC CP LL 1 L2 7
VT T 1 _ 58
V
C3 9 6 C3 5 1 VC CP LL 2 M2 6 C4 1 C3 7 C38 C52 C56 C5 4
VC CP LL 3
0 .0 1u _ 5 0 V_ X7 R_ 0 4 0. 01 u _ 5 0 V_ X7R _ 0 4 22 u _ 6 .3 V_ X5 R_ 0 8 22 u _ 6 .3 V_ X5 R_ 0 8
8
.
1u _ 6 .3 V_ X5 R_ 0 4 1 u _6 .3 V_ X5 R _0 4 2 .2 u _ 1 6V _ X5 R _ 06 4 .7 u _ 6 .3 V_ X5 R _ 0 6 1 0 u _ 6 .3V _ X5 R _ 0 6 10 u _ 6 .3 V_ X5 R_ 0 6
1
PZ 98 9 2 7 -3 6 41-0 1 F
1 .5 V S _ C P U 4 ,3 1
1 . 8V S 2 0 , 33
V G F X_ C O R E 3 5
1 .1 VS _ VT T 2 ,4, 6, 14 ,1 5 ,1 6 ,1 9 ,2 0 ,21 ,3 4 ,3 5 ,3 6
1 .5 V 4 ,9 ,10 ,1 1,2 1 ,23 ,2 7,2 9 ,31 , 33 ,3 6
B - 8 CPU 5/7 (Graphic s Power)
Schematic Diagrams
CPU 6/7 (GND)
PROCESSOR 6/7 ( GND )
U16H U16I
AT20 AE34
AT17 VSS1 VSS81 AE33
AR31 VSS2 VSS82 AE32 K27
AR28 VSS3 VSS83 AE31 K9 VSS161
AR23 VSS6 VSS86 AE28 J32 VSS164
AR12 VSS10 VSS90 AD10 H35 VSS168
AR9 VSS11 VSS91 AC8 H32 VSS169
AR6 VSS12 VSS92 AC4 H28 VSS170
AR3 VSS13 VSS93 AC2 H26 VSS171 B
AP20 VSS14 VSS94 AB35 H24 VSS172
AP17 VSS15 VSS95 AB34 H22 VSS173 .
AP13 VSS16 VSS96 AB33 H18 VSS174 S
AP7 VSS18 VSS98 AB31 H13 VSS176 c
AP2 VSS20 VSS100 AB29 H8 VSS178 h
AN34 VSS21 VSS101 AB28 H5 VSS179
AN31 VSS22 VSS102 AB27 H2 VSS180 e
VSS23 VSS103 VSS181
AN23
AN20
AN17
VSS24
VSS25
VSS104
VSS105
AB26
AB6
AA10
G34
G31
G20
VSS182
VSS183
Sheet 8 of 42 m
AM29
AM27
AM25
VSS26
VSS27
VSS28
VSS106
VSS107
VSS108
Y8
Y4
Y2
G9
G6
G3
VSS184
VSS185
VSS186
CPU 6/7 (GND) a
AM20 VSS29 VSS109 W35 F30 VSS187 t
AM17 VSS30 VSS110 W34 F27 VSS188 i
AM14 VSS31 VSS111 W33 F25 VSS189
c
VSS34 VSS114 VSS192
AM5 W30 F16
D
AM2 VSS35 VSS115 W29 E35 VSS193
AL34 VSS36 VSS116 W28 E32 VSS194
AL31 VSS37 VSS117 W27 E29 VSS195
VSS38 VSS118 VSS196
V SS VS S
AL23
AL20 VSS39 VSS119 W26
W6
E24
E21 VSS197
a
i
g
AL17 VSS40 VSS120 V10 E18 VSS198
VSS41 VSS121 VSS199
AL12 U8 E13
r
AL9 VSS42 VSS122 U4 E11 VSS200 a
AL6 VSS43 VSS123 U2 E8 VSS201
AL3 VSS44 VSS124 T35 E5 VSS202 m
AK29 VSS45 VSS125 T34 E2 VSS203 AT35
AK27 VSS46 VSS126 T33 D33 VSS204 VSS_NC TF1 AT1
VSS47 VSS127 VSS205 VSS_NC TF2
AK25 T32 D30 AR34
s
AK20 VSS48 VSS128 T31 D26 VSS206 VSS_NC TF3 B34
AK17 VSS49 VSS129 T30 D9 VSS207 VSS_NC TF4 B2
AJ31 VSS50 VSS130 T29 D6 VSS208 VSS_NC TF5 B1
VSS51 VSS131 VSS209 F VSS_NC TF6
AJ23 T28 D3 T A35
AJ20 VSS52 VSS132 T27 C34 VSS210 C VSS_NC TF7
AJ17 VSS53 VSS133 T26 C32 VSS211 N
AJ14 VSS54 VSS134 T6 C29 VSS212
AJ11 VSS55 VSS135 R10 C28 VSS213
AJ8 VSS56 VSS136 P8 C24 VSS214
AH35 VSS59 VSS139 N35 C19 VSS217
AH34 VSS60 VSS140 N34 C16 VSS218
AH33 VSS61 VSS141 N33 B31 VSS219
AH17 VSS70 VSS150 M1 0 B4 VSS228
AH13 VSS71 VSS151 L35 A29 VSS229
AH9 VSS72 VSS152 L32 A27 VSS230
AH6 VSS73
VSS74 VSS153
VSS154 L29 A23 VSS231
VSS232
AH3 L8 A9
AG10 VSS75 VSS155 L5 VSS233
AF8 VSS76 VSS156 L2
AF4 VSS77 VSS157 K34
AF2 VSS78 VSS158 K33
AE35 VSS79 VSS159 K30
VSS80 VSS160
PZ98927-3641-01F PZ98927-3641-01F
CPU 6/7 (GND) B - 9
Schematic Diagrams
CPU 7/7 (RESERVED)
PROCESSOR 7/7 ( RESERVED )

1 .5 V
U1 6 E
AP2302GN
A J1 3 R36
RS V D3 2 A J1 2
RS V D3 3
PCI- Express Configurat i on Sel ect A P2 5
Q8 * 1 K_ 1% _ 0 4
*A O3 4 0 2L
A L2 5 R S VD 1 A H2 5 V R E F _ CH _ A_ DIM M S D MV R EF _ D Q_ DIM 0
A L2 4 R S VD 2 RS V D3 4 A K 26
1 : Single PEG
CFG0 0 : Bif urcati on enable
A L2 2
A J3 3
R
R
S
S
VD
VD
3
4
RS V D3 5
A L2 6 R 2 12 R37
A G9 R S VD 5 RS V D3 6 AR 2 G
* 1 00 K _ 1 % _ 0 4
M2 7 R S VD 6 R SV D _ NC TF _3 7
* 1 K_ 1% _ 0 4
L2 8 R S VD 7 A J2 6
J1 7 R S VD 8 RS V D3 8 A J2 7 DR A MR ST _ CT R L 4,1 9
CFG0 R 22 7 * 3.0 1K _ 04 R 35 *0 _ 04 VR EF _ C H_ A _ DI MM
s
1 0 MVR EF _ D Q_ DI M0 VR EF _ C H_ B _ DI MM H1 7 R S VD 9 RS V D3 9
1 1 MVR EF _ D Q_ DI M1 R 39 *0 _ 04
G2 5 R S VD 1 0 ? ? IBEXCONTROL
G1 7 R S VD 1 1
m
R S VD 1 2
CFG3 - PCI - Express Stat i c Lane Reversal E3 1
E3 0 R S VD 1 3 R SV D _ NC TF _4 0
AP1
A T2
R S VD 1 4 R SV D _ NC TF _4 1
a
1 .5 V
1 : Normal Operati on
CFG3 A T3
r 0 : Lane Numbers Revers ed R SV D _ NC TF _4 2 AR 1

R SV D _ NC TF _4 3
g Sheet 9 of 42 15 - > 0 , 14 - > 1 , . . . AP23 02GN R38
a
A L2 8 Q9 * 1 K_ 1% _ 0 4
i CPU 7/7 CFG3 R 22 1 * 3.0 1K _ 04 C F G0 A M3 0

A M2 8
A P3 1
C F G [0]
C F G [1]
RS V D4 5
RS V D4 6
RS V D4 7
A L2 9
A P 30
A P 32
V R E F _ CH _ B _ DIM M S
*A O3 4 0 2L
D MV R E F _ D Q_ D IM 1
D
A L3 2 C F G [2] RS V D4 8 A L2 7
(RESERVED) CFG4 - Di spl ay Port Pres ence

C F G3
C F G4 A L3 0
A M3 1
C F G [3]
C F G [4]
RS V D4 9 A T3 1
RS V D5 0 A T3 2
R 2 14
* 1 00 K _ 1 % _ 0 4 G
R40
c
A N2 9 C F G [5] RS V D5 1 A P 33 * 1 K_ 1% _ 0 4
i
C F G7 A M3 2 C F G [6] RS V D5 2 A R3 3
1 : Dis a blle d; No phys i ca l Dis pla y Port A K3 2 C F G [7] RS V D5 3 A T3 3 DR A MR ST _ CT R L 4,1 9
t attached to Embedded Displ ay Port A K3 1 C F G [8] R SV D _ NC TF _5 4 A T3 4

C F G [9] R SV D _ NC TF _5 5 A P 35 ? ? IBEXCONTROL
a CFG4 A K2 8
A J2 8 C F G [10 ] D R SV D _ NC TF _5 6 A R3 5
0 : Enable d; An e xt e rna l Dis pl ay Po rt A N3 0 C F G [11 ]
E R SV D _ NC TF _5 7 A R3 2
devi ce i s connected to the Embedded A N3 2 C F G [12 ]
V RS V D5 8
m R
A J3 2 C F G [13 ]
is pl ay Po rt
A J2 9 C F G [14 ]
E E 15
A J3 0
A K3 0
C F G [15 ]
C F G [16 ] S R S VD _ TP _5 9
R S VD _ TP _6 0
F 15
A2
C F G [17 ] K EY
h
e
E
R
CFG4 R 22 0 * 3.0 1K _ 04 R 21 1 *0 _ 0 4 R SVD8 6 H1 6 D15
R S VD _ TP _8 6 RS V D6 2 C15
RS V D6 3
c
RSVD86 A J1 5 RSV D 6 4 _R R 2 17 * 15 m i _l s h o rt _ 06
Connect t o GND RS V D6 4 A H1 5 RSV D 6 5 _R R 2 18 * 15 m i _l s h o rt _ 06
RS V D6 5
S
B1 9
.
A1 9 R S VD 15
R S VD 1 6
CFG7 R 22 4 * 3.0 1K _ 04
R 20 5 * 15 m li_ s h ort _0 6 H _R S VD 1 7_ R A2 0
B
B2 0 R S VD 1 7
CFG7 R 20 4 * 15 m il_ s h ort _0 6 H _R S VD 1 8_ R
R S VD 1 8 AA5
Cl arksfi eld (onl y f or early samples U9 R S VD _ TP _6 6 AA4
T 9 R S VD 19 R S VD _ TP _6 7 R8
pre- ES1) - Connect to GND wit h 3.01K Ohm/ 5% R S VD 2 0 R S VD _ TP _6 8 AD 3
AC 9 R S VD _ TP _6 9 A D 2
r esi s t or AB 9 R S VD 21 R S VD _ TP _7 0 AA2
R S VD 2 2 R S VD _ TP _7 1 AA1
R S VD _ TP _7 2 R9
R S VD _ TP _7 3 A G7
C1 R S VD _ TP _7 4 AE3
A3 R S VD _ NC TF _2 3 R S VD _ TP _7 5
R S VD _ NC TF _2 4
V4
R S VD _ TP _7 6 V5
R S VD _ TP _7 7 N2
J2 9 R S VD _ TP _7 8 AD 5
J2 8 R S VD 26 R S VD _ TP _7 9 AD 7
R S VD 2 7 R S VD _ TP _8 0 W 3
A3 4 R S VD _ TP _8 1 W 2
A3 3 R S VD _ NC TF _2 8 R S VD _ TP _8 2 N3
R S VD _ NC TF _2 9 R S VD _ TP _8 3 AE5
C3 5 R S VD _ TP _8 4 AD 9
B3 5 R S VD _ NC TF _3 0 R S VD _ TP _8 5
R S VD _ NC TF _3 1
A P 34 TP _R S VD 8 6
VSS VSS (AP34) can be left NC is
CRB implementation ; EDS/DG
recommendation to GND
PZ 9 89 2 7 -3 6 41 -0 1 F
1.5 V 4 ,1 0, 11 ,21 ,2 3,2 7,29 ,3 1,3 3, 36
B - 10 CPU 7/7 (RESERVED)
Schematic Diagrams
DDR3 SO-DIMM_0
SO-DIMM A CHANGE TO STANDARD
J DIM M2 A
5 M_ A_ A[1 5 :0 ] M _A_ A0 98 5 M _A _D Q0 M_ A_ DQ [6 3:0] 5
J DIM M2 B
M _A_ A1 97 A0 DQ 0 7 M _A _D Q1
M _A_ A2 96 A1 DQ 1 15 M _A _D Q2
M _A_ A3 95 A2 DQ 2 17 M _A _D Q3 1 .5V
M _A_ A4 92 A3 DQ 3 4 M _A _D Q4
M _A_ A5 91 A4 DQ 4 6 M _A _D Q5 75 44
M _A_ A6 90 A5 DQ 5 16 M _A _D Q6 76 VDD 1 VS S1 6 48
Layout Note: M _A_ A9 85 A8 DQ 8 23 M _A _D Q9 87 VDD 4 VS S1 9 55
M _A_ A1 0 107 A9 DQ 9 33 M _A _D Q1 0 88 VDD 5 VS S2 0 60
signal/space/signa l: M _A_ A1 1 84 A 1 0 /A P D Q1 0 35 M _A _D Q1 1 93 VDD 6 VS S2 1 61
M _A_ A1 2 83 A1 1 D Q1 1 22 M _A _D Q1 2 94 VDD 7 VS S2 2 65
8 / 4/ 8 M _A_ A1 3 119 A 1 2 /B C # D Q1 2 24 M _A _D Q1 3 3 .3 V S 99 VDD 8 VS S2 3 66
M _A_ A1 4 80 A1 3 D Q1 3 34 M _A _D Q1 4 1 00 VDD 9 VS S2 4 71
M _A_ A1 5 78 A1 4 D Q1 4 36 M _A _D Q1 5 20mils 1 05 VDD 1 0 VS S2 5 72
A1 5 D Q1 5 39 M _A _D Q1 6 1 06 VDD 1 1 VS S2 6 12 7 B
109 D Q1 6 41 M _A _D Q1 7 1 11 VDD 1 2 VS S2 7 12 8
5 M_ A_ BS0 C96 C9 7
108 BA0 D Q1 7 51 M _A _D Q1 8 1 12 VDD 1 3 VS S2 8 13 3
5 M_ A_ BS1 79 BA1 D Q1 8 53 M _A _D Q1 9 1 17 VDD 1 4 VS S2 9 13 4
.
1 u _ 6 .3V _X5 R_ 0 4 0.1 u _ 1 0V _X7 R_ 0 4
5 M_ A_ BS2 BA2 D Q1 9 V D D 15 VS S3 0
5 M_ C S# 0
114 40 M _A _D Q2 0 1 18 13 8
S
121 S0 # D Q2 0 42 M _A _D Q2 1 1 23 VDD 1 6 VS S3 1 13 9
5 M_ C S# 1 101 S1 # D Q2 1 50 M _A _D Q2 2 1 24 VDD 1 7 VS S3 2 14 4 c
5 M _ CL K_ DD R0 103 CK 0 D Q2 2 52 VDD 1 8 VS S3 3 14 5
M _A _D Q2 3
5
5
5
M _ CL K_ DD R# 0
M _ CL K_ DD R1
M _ CL K_ DD R# 1
102
104
73
CK 0#
CK 1
CK 1#
D Q2 3
D Q2 4
D Q2 5
57
59
67
M _A _D Q2 4
M _A _D Q2 5
M _A _D Q2 6 3 .3 VS
1 99
77
VDD SPD
VS
VS
VS
S3
S3
S3
4
5
6
15 0
15 1
15 5
Sheet 10 of 42 h
5 M_ C KE0 74 CK E0 D Q2 6 69 M _A _D Q2 7 1 22 NC 1 VS S3 7 15 6
DDR3 SO-DIMM_0
5 M_ C KE1
e
115 CK E1 D Q2 7 56 M _A _D Q2 8 R 72 1 0 K _ 1% _ 0 4 1 25 NC 2 VS S3 8 16 1
5 M _A _C AS# 110 CA S# D Q2 8 58 M _A _D Q2 9 NC TE ST VS S3 9 16 2
m
5 M _A _R AS# RA S# D Q2 9 VS S4 0
113 68 M _A _D Q3 0 1 98 16 7
5 M _A _W E# SA0 _ DIM 0 197 W E# D Q3 0 70 M _A _D Q3 1 4,1 1 T S# _ DIM M0 _ 1 30 E V E N T# VS S4 1 16 8
SA1 _ DIM 0 2 0 1 SA0 D Q3 1 129 M _A _D Q3 2 4,1 1 D DR 3_ D RAM RS T# R E S E T# VS S4 2 17 2
20mils
2 0 2 SA1 D Q3 2 131 M _A _D Q3 3 C 1 8 2 .2u _6 .3 V _ X 5R _ 06 VS S4 3 17 3
a
2 ,1 1 C L K_ SCL K
2 0 0 SC L D Q3 3 141 M _A _D Q3 4 C 1 9 0 .1u _1 0V _ X 7R _ 04 1 VS S4 4 17 8
2,1 1 C LK _S DAT A SD A D Q3 4 143 M _A _D Q3 5 1 26 VREF _D Q VS S4 5 17 9
t
D Q3 5 VREF _C A VS S4 6
3 .3 VS 116 130 M _A _D Q3 6 18 4
i
5 M_ O DT 0 OD T 0 D Q3 6 VS S4 7
5 M_ O DT 1
120
OD T 1 D Q3 7
132 M _A _D Q3 7
9 M VR EF _ DQ _D IM 0
R2 0 *0 _ 0 4 R 19 * 15 m il _ sh o r t _ 0 6
VS S4 8
18 5
c
140 M _A _D Q3 8 2 18 9
5 M_ A_ D M[7 :0 ] M _A_ D M0 11 D Q3 8 142 M _A _D Q3 9 M VREF _D IM0 3 VSS1 VS S4 9 19 0
RN 3
1 0 K_ 8 P4R _ 0 4 M _A_ D M1 28 DM 0 D Q3 9 147 M _A _D Q4 0 C8 2 2 .2u _6 .3V _ X5 R _ 06 8 VSS2 VS S5 0 19 5 D
1 8 SA1 _ DIM 1 M _A_ D M2 46 DM 1 D Q4 0 149 M _A _D Q4 1 9 VSS3 VS S5 1 19 6
SA1 _D IM 1 1 1 C8 1 0 .1u _1 0V _ X7 R _ 04
2 7 SA0 _ DIM 1 M _A_ D M3 63 DM 2 D Q4 1 157 M _A _D Q4 2 13 VSS4 VS S5 2
3 6 SA0 _D IM 1 1 1 136 DM 3 D Q4 2 159 14 VSS5
SA1 _ DIM 0 M _A_ D M4 M _A _D Q4 3
4 5 SA0 _ DIM 0 M _A_ D M5 153 DM 4 D Q4 3 146 M _A _D Q4 4 19 VSS6
170 DM 5 D Q4 4 148 20 VSS7 VTT _ M EM
M _A_
_A_ D
D M7
M6 DM 6 D Q4 5 M
M _A _D Q4 56 VSS8
M 187 158 _A _D Q4 25
a
i
g
DM 7 D Q4 6 160 M _A _D Q4 7 26 VSS9 20 3
5 M_ A_ D QS[7 :0 ] M _A_ D QS0 12 D Q4 7 163 M _A _D Q4 8 31 VSS1 0 VT T 1 20 4 r
M _A_ D QS1 29 DQ S0 D Q4 8 165 M _A _D Q4 9 32 VSS1 1 VT T 2
47 DQ S1 D Q4 9 175 37 VSS1 2 GN D1
M _A_ D QS2 M _A _D Q5 0
a
M _A_ D QS3 64 DQ S2 D Q5 0 177 M _A _D Q5 1 38 VSS1 3 G1 GN D2
137 DQ S3 D Q5 1 164 43 VSS1 4 G2
M _A_ D QS4
DQ S4 D Q5 2
M _A _D Q5 2
VSS1 5
m
M _A_ D QS5 154 166 M _A _D Q5 3
M _A_ D QS6 171 DQ S5 D Q5 3 174 M _A _D Q5 4 AS0 A6 2 1-U 2 SN- 7 F
188 DQ S6 D Q5 4 176
M _A_ D QS7 M _A _D Q5 5 s
DQ S7 D Q5 5 181 M _A _D Q5 6
5 M_ A_ D QS# [7 : 0 ] 10 D Q5 6 183
M _A_ D QS# 0 M _A _D Q5 7
M _A_ D QS# 1 27 DQ S0 # D Q5 7 191 M _A _D Q5 8
M _A_ D QS# 2 45 DQ S1 # D Q5 8 193 M _A _D Q5 9
M _A_ D QS# 3 62 DQ S2 # D Q5 9 180 M _A _D Q6 0
M _A_ D QS# 4 135 DQ S3 # D Q6 0 182 M _A _D Q6 1
M _A_ D QS# 5 152 DQ S4 # D Q6 1 192 M _A _D Q6 2
M _A_ D QS# 6 169 DQ S5 # D Q6 2 194 M _A _D Q6 3
M _A_ D QS# 7 186 DQ S6 # D Q6 3
DQ S7 # CLOSE TO SO-DIMM_0
1 .5 V AS0 A6 2 1 -U2 SN -7 F
R 63 1K _1 % _ 0 4 M VR EF _ DIM 0
1.5 V
C3 5 3 + C 3 2 1 C57 C6 2 C7 8 C 47 C68 C70 + C 3 16
+ 5 60 u _ 2 .5V _6 .6 * 6.6 * 5.9 R65 C8 6
*2 2 0 u_ 2 .5 V_ B_ A 1 0 u _ 6.3 V_ X5 R_ 0 6 10 u _ 6 .3V _X5 R_ 0 6 *1 0 u _6 .3 V_ X5 R_ 0 6 1 u _6 .3 V_ X5 R_ 0 4 1 u _ 6. 3V_ X5 R_ 0 4 * 1 u_ 6 .3 V_ X5R _ 0 4 * 5 60 u _ 2. 5V_ 6 .6 *6 .6 *5 .9
1 K_ 1 % _0 4 0 .1 u_ 1 0 V _ X7 R _ 04
1.5 V
C7 3 C4 8 C 44 C67 C4 6 C7 5 C 43
4 ,9 ,1 1, 21 ,2 3 , 2 7,2 9 ,3 1 ,3 3,3 6 1 .5 V
1 1,3 3 VT T _ MEM
0 .1u _ 1 0 V _ X7 R _0 4 0 .1 u_ 1 0 V_ X7R _ 04 * 0.1 u _ 1 0V _X7 R_ 0 4 0 .1 u _ 10 V_ X7 R_ 0 4 0.1 u _ 1 0V _X7 R_ 0 4 0 .1u _ 1 0 V _ X7 R _0 4 *0 .1 u _ 1 0V_ X7 R_ 0 4
2 ,1 1,1 2 ,1 3 ,14 ,1 5 ,1 6 , 17 ,1 8 ,1 9 ,20 ,2 1 ,2 3 ,24 ,2 5 , 2 6, 27 ,2 8 ,2 9,3 0 ,3 1 , 3 5,3 6 3 .3 VS
VT T _M EM
C1 0 1 C1 0 5 C 10 4 C106
1 0u _ 6 .3 V _ X5 R _0 6 *1 u _ 6 .3V _X5 R_ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 1 u _ 6 .3V _X5 R_ 0 4
DDR3 SO-DIMM_0 B - 11
Schematic Diagrams
DDR3 SO-DIMM_1
8/18/2019
SO-DIMM
B CHANGE TO STANDARD
J DIM M1 A
5 M_ B_ A[1 5 :0] M _B _A 0 98 5 M_ B_ DQ 0 M_ B _ D Q[6 3 :0 ] 5 J DIM M1 B
97 A0 DQ 0 7
M _B _A 1 M_ B_ DQ 1
M _B _A 2 96 A1 DQ 1 15 M_ B_ DQ 2 1 .5V
M _B _A 3 95 A2 DQ 2 17 M_ B_ DQ 3
M _B _A 4 92 A3 DQ 3 4 M_ B_ DQ 4
M _B _A 5 91 A4 DQ 4 6 M_ B_ DQ 5 75 44
M _B _A 6 90 A5 DQ 5 16 M_ B_ DQ 6 76 VD D1 VSS1 6 48
Lay out N ot e: M _B _A 9 85 A8 DQ 8 23 M_ B_ DQ 9 87 VD D4 VSS1 9 55
M _B _A 10 107 A9 DQ 9 33 M_ B_ DQ 1 0 88 VD D5 VSS2 0 60
signal/spac e/signal: M _B _A 11 84 A1 0 /AP DQ 1 0 35 M_ B_ DQ 1 1 93 VD D6 VSS2 1 61
M _B _A 12 83 A1 1 DQ 1 1 22 M_ B_ DQ 1 2 94 VD D7 VSS2 2 65
8/4/8 M _B _A 13 119 A1 2 /BC# DQ 1 2 24 M_ B_ DQ 1 3 99 VD D8 VSS2 3 66
M _B _A 14 80 A1 3 DQ 1 3 34 M_ B_ DQ 1 4 100 VD D9 VSS2 4 71
M _B _A 15 78 A1 4 DQ 1 4 36 M_ B_ DQ 1 5 105 VD D1 0 VSS2 5 72
A1 5 DQ 1 5 39 M_ B_ DQ 1 6 106 VD D1 1 VSS2 6 1 27
109 DQ 1 6 41 M_ B_ DQ 1 7 111 VD D1 2 VSS2 7 1 28
5 M _ B_ BS0 108 BA0 DQ 1 7 51 M_ B_ DQ 1 8 112 VD D1 3 VSS2 8 1 33
5 M _ B_ BS1 79 BA1 DQ 1 8 53 117 VD D1 4 VSS2 9 1 34
M_ B_ DQ 1 9
5 M _ B_ BS2 114 BA2 DQ 1 9 40 M_ B_ DQ 2 0 1 1 8 VD D15 VSS3 0 1 38
5 M _ CS# 2
s
121 S0 # DQ 2 0 42 M_ B_ DQ 2 1 123 VD D1 6 VSS3 1 1 39
5 M _ CS# 3 101 S1 # DQ 2 1 50 M_ B_ DQ 2 2 124 VD D1 7 VSS3 2 1 44
3.3 VS
5 M_ C LK_ D DR 2 103 CK 0 DQ 2 2 52 M_ B_ DQ 2 3 VD D1 8 VSS3 3 1 45
5 M_ C LK_ D DR # 2 102 CK 0# DQ 2 3 57 20mils 199 VSS3 4 1 50
m
M_ B_ DQ 2 4
5 M_ C LK_ D DR 3 104 CK 1 DQ 2 4 59 M_ B_ DQ 2 5 VD DSPD VSS3 5 1 51
5 M_ C LK_ D DR # 3 73 CK 1# DQ 2 5 67 77 VSS3 6 1 55
a
M_ B_ DQ 2 6 C9 8 C99
5 M _ CKE2 74 CK E0 DQ 2 6 69 M_ B_ DQ 2 7 122 NC 1 VSS3 7 1 56
5 M _ CKE3
r
115 CK E1 DQ 2 7 56 M_ B_ DQ 2 8 1 u_ 6 .3 V_ X5 R _0 4 0 .1 u _ 10 V_ X7 R_ 0 4 125 NC 2 VSS3 8 1 61
5 M_ B_ CAS # 110 CA S# DQ 2 8 58 M_ B_ DQ 2 9 NC T EST VSS3 9 1 62
g Sheet 11 of 42 5
5
M_ B_ RAS #
M_ B_ W E#
10 SA0 _D IM 1
SA0 _ D IM1
113
197
RA S#
W E#
2 0 1 SA0
DQ 2 9
DQ 3 0
DQ 3 1
68
70
M_ B_ DQ 3 0
M_ B_ DQ 3 1
4 ,1 0 TS# _ DI MM 0_ 1
4 ,1 0 DDR 3 _ DR AMR ST #
198
3 0 EVEN T #
RE SET #
VSS4
VSS4
VSS4
0
1
2
1 67
1 68
a
SA1 _ D IM1 1 29 M_ B_ DQ 3 2 1 72
10 SA1 _D IM 1
DDR3 SO-DIMM_1
2 0 2 SA1 DQ 3 2 1 31 VSS4 3 1 73
i
M_ B_ DQ 3 3 C2 2 2 .2u _6 .3V _ X5 R _ 06
2,1 0 CL K_ SC LK 200 SC L DQ 3 3 1 41 M_ B_ DQ 3 4 1 VSS4 4 1 78
2 ,1 0 CL K_ SDA TA C2 3 0 .1u _ 10 V _ X 7 R _0 4
SD A DQ 3 4 1 43 M_ B_ DQ 3 5 126 VR EF _ DQ VSS4 5 1 79
D
116 DQ 3 5 1 30 M_ B_ DQ 3 6 VR EF _ CA VSS4 6 1 84
5 M _ OD T2 120 OD T 0 DQ 3 6 1 32 M_ B_ DQ 3 7 R23 * 0_ 0 4 R 22 *1 5 m il_ s h ort_ 0 6 VSS4 7 1 85
5 M _ OD T3 OD T 1 DQ 3 7 1 40 9 M VREF _D Q_ D IM1 2 VSS4 8 1 89
M_ B_ DQ 3 8
c
5 M _B _D M[7 :0 ] M _B _D M0 11 DQ 3 8 1 42 M_ B_ DQ 3 9 MV REF _ D IM1 3 VSS1 VSS4 9 1 90
i
M _B _D M1 28 DM 0 DQ 3 9 1 47 M_ B_ DQ 4 0 C8 4 2 .2u _6 .3V _ X5 R _ 06 8 VSS2 VSS5 0 1 95
DM 1 DQ 4 0 VSS3 VSS5 1
t
M _B _D M2 46 1 49 M_ B_ DQ 4 1 C8 3 0 .1u _ 10 V _ X 7 R _0 4 9 1 96
M _B _D M3 63 DM 2 DQ 4 1 1 57 M_ B_ DQ 4 2 13 VSS4 VSS5 2
M _B _D M4 136 DM 3 DQ 4 2 1 59 M_ B_ DQ 4 3 14 VSS5
a
2010/01/08
M _B _D M6 170 DM 5 DQ 4 4 1 48 M_ B_ DQ 4 5 20 VSS7 VT T_ M EM
m
DM 7 DQ 4 6 1 60 M_ B_ DQ 4 7 26 VSS9 2 03
5 M _B _D QS [7:0 ] M _B _D QS 0 12 DQ 4 7 1 63 M_ B_ DQ 4 8 31 VSS1 0 VT T 1 2 04
M _B _D QS 1 29 DQ S0 DQ 4 8 1 65 M_ B_ DQ 4 9 32 VSS1 1 VT T 2
M _B _D QS 2 47 DQ S1 DQ 4 9 1 75 M_ B_ DQ 5 0 37 VSS1 2 GN D1
DQ S2 DQ 5 0 VSS1 3 G1
h
e
M _B _D QS 3 64 1 77 M_ B_ DQ 5 1 38 GN D2
M _B _D QS 4 137 DQ S3 DQ 5 1 1 64 M_ B_ DQ 5 2 43 VSS1 4 G2
c
M _B _D QS 5 154 DQ S4 DQ 5 2 1 66 M_ B_ DQ 5 3 VSS1 5
M _B _D QS 6 171 DQ S5 DQ 5 3 1 74 M_ B_ DQ 5 4 AS0 A6 2 1 -UAS N-7 F
M _B _D QS 7 188 DQ S6 DQ 5 4 1 76 M_ B_ DQ 5 5
S
DQ S7 DQ 5 5 1 81 M_ B_ DQ 5 6
.
5 M _ B_ DQ S # [7:0 ] M _B _D QS #0 10 DQ 5 6 1 83 M_ B_ DQ 5 7
M _B _D QS #1 27 DQ S0 # DQ 5 7 1 91 M_ B_ DQ 5 8
DQ S1 # DQ 5 8
B
M _B _D QS #2 45 1 93 M_ B_ DQ 5 9
M _B _D QS #3 62 DQ S2 # DQ 5 9 1 80 M_ B_ DQ 6 0
M _B _D QS #4 135 DQ S3 # DQ 6 0 1 82 M_ B_ DQ 6 1
M _B _D QS #5 152 DQ S4 # DQ 6 1 1 92 M_ B_ DQ 6 2
M _B _D QS #6 169 DQ S5 # DQ 6 2 1 94 M_ B_ DQ 6 3
M _B _D QS #7 186 DQ S6 # DQ 6 3
DQ S7 #
AS0 A6 2 1 -UASN -7 F
CLOSE TO SO-DIMM_1
Lay out N ot e:
R 64 1 K _ 1% _ 0 4 MVR EF _ DIM 1
1 .5 V SO-DIMM_1 is place d farther from t he GMCH than SO-DIMM_0 1.5 V
R66 C8 7
C8 5 C 63 C 42 C 51 C 71 C76 C79 1 K_ 1 % _0 4 0 .1 u_ 1 0 V_ X7 R _0 4
*1 0 u _ 6.3 V_ X5 R_ 0 6 1 0 u_ 6 .3 V_ X5 R _ 06 1 0 u_ 6 .3 V_ X5R _ 06 1 u _6 .3 V_ X5 R _ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 * 1u _ 6 .3 V_ X5 R _0 4
1 .5V
C1 0 9 C 25 C 66 C 22 8 C 49 C69 C72 C77 C50 C45

4 ,9 ,1 0,2 1 ,2 3 ,2 7,2 9 ,3 1 ,33 ,3 6 1 .5 V
10 ,3 3 VT T _M EM
0 .1 u_ 1 0 V _ X7 R _0 4 0 .1 u_ 1 0 V_ X7 R _ 04 0 .1 u_ 1 0 V_ X7R _ 04 0 .1 u _1 0 V_ X7R _ 04 0 .1 u _1 0 V_ X7R _ 04 0 .1 u _1 0 V_ X7R _ 0 4 0 .1 u _1 0 V_ X7 R _ 0 4 0 .1 u _ 10 V_ X7 R _ 0 4 0 .1 u _ 10 V_ X7 R_ 0 4 0 .1 u _ 10 V_ X7 R _ 0 4
2 ,1 0 ,12 ,1 3 ,1 4, 15 ,1 6 ,1 7,1 8 ,1 9 , 20 ,2 1 ,2 3 ,24 ,2 5 ,2 6,2 7 , 2 8 ,2 9,3 0 ,3 1 , 35 ,3 6 3 .3 VS
VT T _ MEM
C1 0 2 C 10 7 C 10 8 C 10 3
1 0 u_ 6 .3 V _ X5 R _0 6 1 u _6 .3 V_ X5R _ 0 4 *1 u _ 6 .3V _X5 R_ 0 4 1 u _6 .3 V_ X5 R _ 0 4
B - 12 DDR3 SO-DIMM_1
Schematic Diagrams
LVDS, Invert er
3 .3 VS

EDID Mode
PANEL CONNECTOR 2
1
3 RN 6
4 2 .2 K_ 4P2 R _0 4
VIN VIN _L CD
J _ LC D1
L 25 * 1 5 m i l _ s h o r t_ 0 6
80m ils 1 2 P_ DD C_ DAT A
3 1 2 4 P_ DD C_ CL K P _ D D C _ D A TA 1 7
5 3 4 6 P_ D DC_ C LK 17
7 5 6 8 BRI G HT N ESS
9 7 8 10 B R IG H T N E S S 28
C3 0 0 C2 9 7 C2 9 4
11 9 10 12 INV_ BL ON
0 .1 u_ 5 0V _Y 5V _0 6 0 .1 u_ 5 0V _Y 5V _0 6 0. 1u _ 50 V_ Y5 V_ 0 6 13 11 12 14
LVD S-L CL KN 15 13 14 16 LVD S-L 2N
17 LVD S-L CL KN LVD S-L CL KP 17 15 16 18 LVD S-L 2P LVD S-L 2N 1 7
17 L VDS-L CL KP 19 17 18 20 LVD S-L 2P 17
LVD S-L 1 N 21 19 20 22
17 L VDS-L 1 N 23 21 22 24
LVD S-L 1 P 3.3 VS
17 L VD S-L 1P 25 23 24 26
LVD S-L 0 N 27 25 26 28
CLOSE TO LVDS CONN. 17
17
L VDS-L 0 N
L VD S-L 0P
LVD S-L 0 P 29 27
29
28
30
30
PIN 87 2 1 6-3 0 0 6 C 2 91 B
0 .1 u _1 6 V_ Y5 V _ 04
PLVD D
C4 C6
.
S
4.7 u _ 6.3 V_ X5R _ 06 0 .1 u _1 6 V_ Y5 V_ 04
c
Sheet 12 of 42 h
LVDS, Inverter
e
PANEL POWER
m
3 .3V S
a
2A R 16 *1 5 m il _ s ho rt_ 0 6
t
C1 5
i
c
C1 7
0 .1 u_ 1 6 V_Y 5 V_0 4
*0 .01 u _ 50 V_ X7R _ 04 3 .3V
D
PL VDD D1 5
U1 C
4 1 2A B R IG H T N E S S AC C2 9 0
i
5 VIN VO UT A *0 .1 u_ 1 6 V_Y 5 V_0 4
VIN
* B A V 9 9 R E C TIF IE R
a
g
3 2
1 7 NB_ ENAV DD EN GN D r
R1 3 APL 3 51 2 A a
10 0 K_ 1% _ 0 4
G5243A 6- 02- 05243- 9C0 m
APL3512A 6- 02-03512-9C0
s
INVERTER CONNECTOR
R6 8 * 1 0 m i l _ s h o r t_ 0 4 BKL _ EN_ R
28 BKL _E N
R 67 C90
*1 0 0 K_ 1% _ 04 * 0 .47 u _ 10 V_ Y5 V_ 0 4
3.3 V 3.3 V 3. 3V
4 U3 A
1 4
7 4L VC 08 PW U 3B
1 1
7 4 LVC 0 8PW C8 9
3 Z 1 2 01 4
BL ON 2 6 *0 .1 u _1 6 V_ Y5 V_ 04
1 7 BL ON 5
7
R 69
7
1 0 0K_ 1 % _0 4 4 U 3C
1
7 4 LVC 0 8PW
19 SB_B LO N Z 1 2 02 9
3.3 V 8 IN V_BL O N
R7 0 1 0 0K _ 1 % _ 0 4 Z 1 2 03 1 0
4 U 3D
1
7 4 LVC 0 8PW R71 C9 3
7
12
2 8,3 0 L ID_ SW # 11 1 M _0 4 0 .1u _ 1 6V_ Y 5V_ 0 4
13
1 6,2 8 AL L _SY S_ PW RG D
7
3 0, 31 ,3 2 ,33 ,3 4 ,35 ,3 6 ,37 VIN
3 ,4 ,1 4,1 5 ,1 6,1 8 , 1 9,2 0 ,2 1, 23 ,2 4, 25 ,2 9 ,30 ,3 1 , 33 ,3 4 ,35 3 .3 V
2 ,1 0,1 1 ,1 3,1 4 ,1 5,1 6 , 1 7,1 8 ,1 9,2 0 ,2 1,2 3 ,2 4, 25 ,2 6, 27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,36 3 .3 VS
3 1 ,32 SY S15 V
LVDS, Invert er B - 13
Schematic Diagrams
HDMI, CRT
8/18/2019 clevo+6-71-w24h0-d02a.unlocked.pdf L 27
1 _0 4 5 VS
5VS
For ESD
HDMI PORT RD2 RD3

BAV99RECT IF IER BAV99 RECT IFIER
R210
FOR I NTEL GRAPHI C RD1
C A C A C A
1_0 4
J_ HDMI1
U2 BAV99 RECT IFIER
C C C
A A A C319 C31 7
17 HDMIB_ D2BP 39 22 HDMIB_DATA2P
17 HDMIB_ D2BN 3 8 IN_ D1+ OUT _D1 + 23 HDMIB _DATA2 N 10u _6 .3V_X5R_ 06 22 u_6 .3V_X5R_ 08
IN_ D1- OUT _D1- 5VS 19 HDMIB _EXT 1_ HPD
42 19 HDMIB_DATA1P RN2 18 HOTPLUG DET ECT
17 HDMIB_ D1BP 4 1 IN_ D2+ OUT _D2 + 20 +5 V 17
17 HDMIB_ D1BN HDMIB_DATA1N 2 .2K_4 P2 R_0 4
4 5 IN_ D2- OUT _D2- 16 HDMIB_DATA0P 1 4 HD MIB_ EXT1 _SDA 16 SDA DDC/CEC GND 15 HDMIB _EXT 1_ SCL
17 HDMIB_ D0BP 4 4 IN_ D3+ OUT _D3 + 17 HDMIB_DATA0N 2 3 14 SCL
FOR E MI FOR EMI
17 HDMIB_ D0BN IN_ D3- OUT _D3- RESERVED 13 HDMI_CEC
L5 CEC
48 13 HDMIB_CL OCKP HDMIB _CLO CKN 1 2 12
17 HDMIB_ CLKBP 4 7 IN_ D4+ OUT _D4 + 14 HDMIB_CL OCKN TMD SCL OCK- 11
17 HDMIB_ CLKBN IN_ D4- OUT _D4- HDMIB _CLO CKP 4 3 10 CLK SHI EL D
HDMI _CT RLCL K 9 28 HDMIB _EXT1_ SCL * HD MI201 2F 2 SF -90 0T 04s- ho rt TMD SCL OCK+ 9 4 3 HDMIB _D AT A0 N
1 7 HDMI_CT RLCL K F
17 HDMI_CT RLDATA HDMI_CT RLDATA 8 SCL SCL_ SINK 29 HDMIB _EXT1_ SDA F
L
- L
- 8 T MDSDAT A0 -
SDA SDA_ SINK P P SHIEL D0 7 1 2 HDMIB_ DATA0P
7 30 2 5 5 6 TMDS DATA0+
M_PORTB_ HPD# _R HDMIB _EXT1_ HPD 4 1
0 4 0
HPD HPD_ SINK R R R TMD SDATA1 - 5 3 L6
0 R F 4 F
s
0
E 4 L
- 4 L
-
R 56 * 4. 7K _ 0 4 Z 4 304 25 2 E
0 0
4 SHIELD1 R
P
R
P *HDMI2 01 2F 2SF -90 0T 04-s ho rt
3 .3VS OE# VCC[1] 11 3 .3VS 4 4 TMD SDATA1 + 3 5 5
R 47 * 0_ 04 VCC[2] R4 8 2
-
2
- T MDSDAT A2 - 0 0
DCC_ EN# 32 15 C1 C4 0 C3 2 2
2
0
2 R
0
R
1 0 DC C_EN# VCC[3] 21 2 0K_1 %_ 04 0 SHIEL D2 1 0
m
4 4
0 E
0 E
RT _EN# VCC[4] 26 0.1 u_ 16 V_ Y5V_0 4 *0 .1u _16 V_Y5 V_ 04 0 .1u _16 V_Y 5 V_ 04 0 R
TMDS DATA2+ 4 0
4
VCC[5] R A 2
- 2
PC0 3 33 A
V V 2
-
2
a
PC1 4 PC0 VCC[6] 40 L7 L
*
L
*
0
4
0
4
R2 9 4 99 _ 1% _0 4 Z 4 305 6 PC1 VCC[7] 46 HDMIB_DATA1N 1 2 0 0
r
RE X T VCC[8] R R
A A
1 4 3 V V
HDMIB_DATA1P L L
Sheet 13 of 42 34 GND[1] 5 * * 4 3 HDMIB _D AT A2 N
g
3.3 VS R 49 * 4. 7 K_ 0 4 Z 4 306 C27 C65 * HDMI20 12F 2 SF -90 0T 04 -sho rt F
C12 81 7-1 19A5 -L
R 58 * 4. 7 K_ 0 4 Z 4 307 3 5 OE_ 1 GND[2] 12 F
L L
-
QE_ 2 GND[3] 18 -
P 1 2 HDMIB_ DATA2P
GND[4] 0.1 u_1 6V_ Y5V_0 4 0.1 u_ 16 V_ Y5V_0 4 P
a
24 1 5 6 5
5 0 4 0
GND[5]
HDMI, CRT
R
i
27 R R R
0 0 5
F
L
F L8
GND[6] 31 E
E
5
- 5
9 L
- *HDMI2 01 2F 2SF -90 0T 04-s ho rt
GND[7] 0 0
4 R P R
5 P
36 4
2 2 0
5
0
49 GND[8] 37 - -
D
2 2
0 R
0 R
GN D GND[9] 43 0
4 4 E 0
E
GND[10] 0 0
0 R 4 0
4
R A 2
- 2
PTN3 36 0BBS A
V V 2 -
2
c
PIN 4 9= GND R2 7 L L 0
4 0
PORT C_HPD M_PORTB_ HPD# _R * * 0 4
0
i
17 PORT C_HPD 3 3. VS R R
PTN3360BBS 6-03- 03360- 030 A A
t
V V
*1 0m il_s ho rt _ 04 L
* L
*
PS8101 6- 03-08101- 032
a
C3 10 C 59
3.3VS R 57 4. 7K _04 DCC_EN#
0 .1u _16 V_Y5 V_ 04 * 0.1u _1 6V_Y5 V_0 4
R 31 4. 7K _04 PC0
m R 30 * 4. 7 K_ 04 PC1
e
h
c
S
.
B J_ CRT1
6- 19-31001- 266 10 8AH1 5F ST04 A1CC
CRT PORT 3 .3VS 5VS
L4 . F CM100 5M F -600T01
RED 1
2
9
24
17 DAC_ RED
L3 . FF CM1
0 0 5M F -600T01 GRN 10 mil
4 3 4 3 17 DAC_ GREEN
17 DAC_ BL UE L2 . CM100 5M F -600T01 BLUE 3
11
RN7 RN1 4 4 4 4
2 .2K_4 P2R_ 04 2.2 K_ 4P2 R_04 0 0 4
0 0 0 4
0
4
_ _ _ _ _ _ 12 DDCD ATA
O O O O
U15 R1 2 R11 R10 P P O
P P P O
P 5
1 2 1 2
10 9 DDCDATA N
_ N N N
_ N N 13 HS Y NC
1 7 DAC_DDCADATA DDC_ IN1 DDC_OUT 1 _ _ _ _
1 50 _1% _0 4 150 _1 %_ 04 15 0_ 1%_ 04 V
0 V V V
0 V V 6
11 12 0 0 0 0 14
DDCL K 5
_ 5 5 5
_ 5 5 V S Y NC
1 7 DAC_DDCACL K DDC_ IN2 DDC_OUT 2 p
_
p
_
p p
_
p
_
p 7
0 0
13 14 1 0
1 0
1 1 0
1 0
1 15
1 7 DAC_HSYNC CRT_ HSYNC R 15 33 _0 4 HS Y NC DDCL K
SYNC_IN1 SYNC_OUT 1 8
15 16 CRT_ VSYNC VSYN C 0 2 3 1 4 6 4
0 4 4
0 4
1 7 DAC_ VSYNC SYNC_IN2 SYNC_OUT 2 R 14 33 _0 4 1 1 1 1 1 1
_
0
_
_ 0
_
C C C C C C 1 2 O
R
7 O P R
7
1 3 BLUE D D
X
P
N X
5VS VCC_SYNC VIDEO_ 1 N N
_
N
_ _ _
G
G V V V
2 4 GRN 0 V 0 0
3 .3VS VCC_VIDEO VIDEO_ 2 5 0
5 5 5
_ _ _ _
p p p p
7 5 RED 0
0 0 0
2 0
0
3.3VS VCC_DDC VIDEO_ 3 0 2
2 2 0
8 6 1 1
BYP GND 5
9 3 2
9 7
2 9
2 2 C
4 4 4 TPD7S0 19
0 0
_ 0 C C C
_ _
8 V 9 V 6 V
5 5 9 5
IP4772CZ16 6-02-47721-B60
9 Y 2
9 Y 2 Y
2
_ _ _
C V C V C V
TPD7S019 6-02-07019-B20
0 0
1 0
1 1
_ _
u _
u u
2
2 2
. 2
2
.
0 0 .
0
2 ,10 ,1 1,1 2,14 ,15 ,16,1 7,1 8,19 , 20 ,2 1,2 3,24 ,25 ,26,2 7,2 8,29 , 30 ,3 1,3 5,36 3.3VS
2 ,17 ,20,2 1,2 6,27 ,30 ,3 1,3 5,36 5VS
B - 14 HDMI, CRT
Schematic Diagrams
IBEXPEAK- M 1/9
IBEXPEAK - M (HDA,JTAG,SATA)

RT CV CC
6-22- 32R76-0B2
R T C_ X 1
2 m il s 1 A
6-22- 32R76-0BG
V D D3 2 mils C 40 2
1 2
1 5p _ 5 0 V _ NP O _ 04 X8
C 3 C 36 9 2 .2 u_1 6 V_ X5R _ 0 6
1 T JS 12 5 DJ 4 A 4 2 0 P _ 32 .7 6 8 K Hz
RT C_ V B A T_ 1 2 A
2 1 4 3
R 30 4 6-22- 32R76-0B4 R T C_ X 2 Co- la yo ut X7, X8
2 0 K _ 1% _ 0 4 X7 R 3 02
D1 7 * MC -1 46 _ 3 2 .7 68 K H z
B A T 5 4C S 3 1 0 M_ 0 4 U2 0 A
1 3 4
RTC CLEAR C 39 7
R253 C3 9 9 JOPEN2 1 5p _ 5 0 V _ NP O _ 04 RT C _X 1 B13 D 33
D1 3 RT C X 1 F W H0 / LAD 0 B33 LP C_ A D 0 24 ,2 8
* OP E N_ 1 0 m il -1 MM RT C _X 2 LP C_ A D 1 24 ,2 8
mils 1 K _ 1 % _ 04 2 .2 u_ 1 6 V _ X5 R _ 06 2 Z o= 5 0 O ? 5 % RT C X 2 F W H1 / LAD 1 C 32 LP C_ A D 2 24 ,2 8
F W H2 / LAD 2 A32
RT C _ V B A T 1 RT C _R S T # C1 4 F W H3 / LAD 3 LP C_ A D 3 24 ,2 8
R 30 5
J _ RT C1 2 0 K _ 1% _ 0 4 RT C RS T # C 34
D1 7 F W H 4 / LF RA M E # LP C_ F R A ME # 2 4 ,2 8
S RT C _R T C#
1 S R TC RS T# A34
J_RTC1
C C
1 A16 L DR Q0 # F34
TPM CLEAR S M_ IN T RU DE R #
2
R299 C4 0 0 JOPEN1
IN TR UD E R #
T P
L DR Q1 # / GP IO2 3
8 5 20 5 -0 2 70 1 1 M _ 04 2 .2 u_ 1 6 V _ X5 R _ 06
* OP E N_ 1 0 m il -1 MM
R T CV C C
R 29 8 3 30 K_0 4 P CH _ INT V R ME N A14
IN TV RM E N R L S E R IRQ
AB9 S E R IRQ
S ERI RQ 2 4,28
1 2 2
B
A30
2 7 ,2 9 HD A _ B IT CL K HD A _ B C LK AK7 S A T A R XN 0
S A TA R XN 0 26
SATA HDD
D2 9 S A T A 0 RX N AK6 S A T A R XP 0 S A TA R XP 0 26
.
BIOS ROM 2 7 ,2 9 HD A _ S Y N C HD A _ S Y NC S A TA 0R X P
3 .3 V S AK11 S A T A T X N0
S A T A T XN0 26
S
HD A _ S P K R P1 S A T A 0 TX N AK9 SATATXP0
27 HD A _ S P K R SPKR SATA0TXP S A T A T XP 0 26
NC 1 c
C 2 09 C3 0
S HO R T 0 .1 u _1 6 V _ Y 5V _0 4
32Mbit
2 7 ,2 9 HD A _ RS T # HD A _ RS T#
S A T A 1 RX N
AH6
AH5
S A T A R XN 1
S A T A R XP 1
S A TA R XN 1
S A TA R XP 1
26
26
Sheet 14 of 42 h
S P I_ V D D 8
U10
VDD SI
5
2
S P I_ S I R 38 1 *0 _ 0 4 8 51 8 _ S PI_ S I 2 8
27
29
HD A _ S D IN0
HD A _ S D IN1
G3 0
F30
HD A _ S D IN0
HD A _ S D IN1
S A TA 1R X P
S A T A 1 TX N
SATA1TXP
AF11
AH9
AH8
S A T A T X N1
SATATXP1 S A T A T XN1
S A T A T XP 1
26
26 SATA ODD IBEXPEAK - M 1/9
e
R1 6 3 S P I_ S O R 38 2 *0 _ 0 4
SO 8 51 8 _ S PI_ S O 28
E32 S A T A 2 RX N AF9
m
3.3 K _ 1 % _ 0 4
S P I_ W P # 3
WP# CE#
1 S P I_ CS 0 # R 38 3 *0 _ 0 4
8 51 8 _ S PI_ C S 0 # 28
HD A _ S D IN2
A S A TA 2R X P A F 7
S A T A 2 TX N
F32
D AF6
H
R1 5 6 6 S P I_ S CL K R 38 4 *0 _ 0 4 HD A _ S D IN3 SATA2TXP
a
8 51 8 _ S PI_ S C L K 2 8
3.3 K _ 1 % _ 0 4
S P I_ HO L D# 7
S CK
4 B29
I S A T A 3 RX N
AH3
AH1
t
H OL D# VSS 2 7 ,2 9 HD A _ S DO UT HD A _ S D O S A TA 3R X P A F 3 i
S A T A 3 TX N AF1
M X 25 L 3 2 05 D M2 I-1 2 G D 18 S C D 34 0
C A R3 0 7 HD A _ DO C K _ E N # H3 2 SATA3TXP
c
6-04- 25320-A70 28 ME _W E # HD A _ DO C K _E N# / G P IO 33 A AD9 S A T A R XN 2
J30 T S A T A 4 RX N AD8 S A T A R XP 2
6-04- 02532-470 *1 0 m il_ s ho rt_ 0 4
A
HD A _ DO C K _R S T # / G P IO1 3 S A TA 4R X P A D 6
D
6-04- 26321-470 R 30 3 1 K _1 % _ 0 4
S S A T A 4 TX N AD5
S A T A T X N2
SATATXP2
SATA4TXP i
1
P CH _ JT A G _ T CK _ B U F M 3 AD3
J T A G_ T CK S A T A 5 RX N AD1
SPI_* = 1.5"~6.5" J OP E N3
S A TA 5R X P
Flash Descriptor * OP E N _ 10 m il -1 MM P CH _ JT A G _ T MS K3 ABB 13
2
J T A G_ T MS S A T A 5 TX N A
g
a
Security Overide P CH _ JT A G _ T DI K1 SATA5TXP
J T A G_ T DI 1 .1 V S _ V T T
r
3 .3 V P CH _ JT A G _ T DO J2 G AF16 S A T A IC OM P R 89 3 7 . 4 _ 1 % _0 4
A
J T A G_ T DO S A TA I CO MP O
a
3 .3 V S P CH _ JT A G _ RS T # J4 T AF15
J
J T A G_ R S T # S A T A IC OM P I
m
R2 9 5 R 29 3 R2 9 0 R 2 87 R 93 10 K _ 0 4 S E RIR Q
R282 *1 K _ 1 % _0 4 H DA _S P K R
*2 0 K _ 1 %_ 0 4 *2 0 0 _ 06 *2 0 0_ 0 6 * 20 0 _ 0 6 S P I_ S C LK BA2 3 .3 V S
S P I_ C LK
s
NO REBOOT STRAP: HDA_SPKR High Enable
P CH _ JT A G _ TM S S P I_ CS 0# AV3 R 2 78 * 1 0K _0 4
P CH _ JT A G _ TD I S P I_ C S 0 #
P CH _ JT A G _ TD O S P I_ CS 1# AY3 T3 S A T A _ L E D#
P CH _ JT A G _ RS T # S P I_ C S 1 # S A TA LE D # S A TA _L E D # 2 9 3 .3 V S
3 .3 V S iTPM ENABLE/DISABLE S P I_ S I AY1 Y9 O DD _ DE T E C T# R 1 08 1 0K_ 4

R2 9 4 R 28 9 R2 8 8 R 2 86 S P I_ M OS I S A TA 0 G P / GP IO2 1
*1 0 K _ 1 %_ 0 4 *1 0 0_ 1 % _ 04 *1 0 0_ 1 % _ 04 * 10 0 _ 1 % _0 4
R 26 3 * 1K _ 1 % _ 04 S P I_ S I S P I _ S O R 26 4 3 3 _0 4 S P I_ S O _R AV1
S P I_ M IS O I
P S A TA 1 G P / GP IO1 9
V1
O DD _ DE T E C T # 26
TPM FU
NCTI ON:SPI_SI High Enabl e
I b e x P e ak -M _ Re v 0 _ 9
S S A T A _ DE T# 1 R 2 74 1 0K_ 0 4
R 28 5 * 4. 7 K _ 0 4 P C H _J T A G _T C K _ B UF
ESATA
SATATXP2 C 16 8 * 0 .01 u _5 0V _X 7R _ 0 4
S A T A T X N2 C 16 5 * 0 .01 u _5 0V _X 7R _ 0 4
S A T A R XN 2 C 15 5 * 0 .01 u _5 0V _X 7R _ 0 4
S A T A R XP 2 C 16 4 * 0 .01 u _5 0V _X 7R _ 0 4
2 3 ,2 5 ,28 ,2 9 ,3 1 ,3 2,3 7 V D D3
21 R TC V C C
2 ,4 ,6 ,7 ,1 5 ,1 6,1 9 ,2 0 ,2 1,3 4 ,3 5 ,3 6 1.1 V S _V TT
3 ,4 ,1 2 ,1 5, 16 ,1 8 ,1 9, 20 ,2 1 ,2 3 ,24 ,2 5 ,2 9 ,30 ,3 1 ,3 3 ,3 4,3 5 3 .3 V
2 ,10 ,1 1 ,1 2 ,1 3,1 5 ,1 6 ,1 7,1 8 ,1 9 ,2 0,2 1 ,2 3 ,2 4, 25 ,2 6 ,2 7 ,28 ,2 9 ,3 0 ,31 ,3 5 ,3 6 3 .3V S
IBEXPEAK- M 1/9 B - 15
Schematic Diagrams
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf IBEXPEAK - M 2/9 65/96

8/18/2019 IBEXPEAK clevo+6-71-w24h0-d02a.unlocked.pdf
- M (PCI-E,SMBUS,CLK) RN 1 6 3 .3 V

2 .2K _ 4P 2R _ 0 4
SMB _C L K 3 2
SMB _D A T A 4 1
U 20 B RN 1 1
2 .2K _ 4P 2R _ 0 4
BG 3 0 B9 PC H_ BT _ EN # SML 0 _ DA T A 3 2
BJ 3 0 PER N1 S MB AL ERT # / G PI O 1 1 P CH _ BT _E N# 2 3 ,2 9 4 1
SML 0 _ CL K
BF2 9 PER P 1 H 14 SM B _ CL K S M B _C L K 2
BH 2 9 PET N 1 S M BC LK
RN 1 3
PET P1 C8 SM B _ DA TA 1 0K _8 P4 R _ 0 4
AW30 SM B DA TA SM B _ DA T A 2 1 8
PCH _ BT _ EN#
23 P CIE _ RX N 2_ N EW _ C A RD B A3 0 PER N2 U SB_ OC # 8 9 2 7
23 P CIE _ RX P2 _ NE W _ CA RD PER P 2 18 U SB_ OC # 8 9
23 P CI E _ T X N 2_ N EW _ C A RD C 1 17 0 . 1u _1 0V _ X 7R _ 04 P C IE _ T X N 2 _ C BC 33 00
BD PET N 2 SM L 0 AL ERT # / G PIO 6 0 J14 P C H _ U P E K _ IN IT # P C H _ U P E K _ IN IT # 1 8 LP D_ S PI _I NT R # 34 56
C 1 18 0 . 1u _1 0V _ X 7R _ 04 P C IE _ T X P 2 _ C
23 P CIE _ T X P2 _ NE W _ CA RD PET P2 C6 SM L 0_ C L K
SML 0 C LK S ML 0 _ CLK 23
AU 3 0 RN 1 0
s
23 P C IE _ R X N3 _ W L A N AT 3 0 PER N3 G8 SM L 0_ D AT A 2 .2K _ 4P 2R _ 0 4
u
23 P C IE _ R X P 3 _W L A N P C IE _ T X N 3 _ C AU 3 2 PER P 3 S ML 0 DA TA S M L 0 _D A T A 23 SMD _ CP U_ T HE RM 3 2
C 1 24 0 . 1u _1 0V _ X 7R _ 04
B
23 PC IE_ T XN3 _ W L AN P C IE _ T X P 3 _ C A V3 2 PET N 3 SMC _ CP U_ T HE RM 4 1
C 1 23 0. 1u _1 0 V_ X7 R_ 0 4
M
23 PC IE _ T XP 3 _W L AN PET P3 M 14 L P D _S P I_ INT R #
S
B A3 2 SM L 1 AL ERT # / G PIO 7 4
2 5 PCI E _ RXN 4_ G LAN PER N4
s
B B3 2 E10 SM C_ C PU_ T H E R M
2 5 PCI E_ RXP4 _ GL A N PER P 4 SM L 1 CL K / G PIO 5 8 S M C _ C P U _ T H E R M 3 ,2 8
C 1 19 0 . 1u _1 0V _ X 7R _ 04 P C IE _ T X N 4 _ C BD 3 2
2 5 P CIE_ T XN 4_ G L AN B E3 2 PET N 4 G 12
C 1 02 0 . 1u _1 0V _ X 7R _ 04 P C IE _ T X P 4 _ C SM D_ C PU_ T H E R M
2 5 P CIE_ T XP4 _ GL A N PET P4 SM L1 D AT A / G PIO 7 5 S M D _ C P U _ T H E R M 3 ,2 8
m BF3
BH 3
3
3 PER N5
*
E T13
PEG _ CL KR E Q # R 29 1 1 0K _ 04
a - Control ler

BG 3 2 PER P 5 CL _ C L K1 L AN _C L KR E Q# R 11 2 1 0K _ 04
r I
BJ 3 2 PET N 5 T11
PCI-E x1 Usage PET P5
C Link CL _ D A T A1
g Sheet 15 of 42 Lane 1 WLAN

B A3
AW3
4
4 PER N6 P C L_ R S T 1 #
T9
a
BC 3 4 PER P 6 10Kpull -down to
IBEXPEAK - M 2/9
PET N 6
Lane 2 NEW CARD
i
BD 3 4 GND
PET P6 H1 PE G _ CL KR EQ #
Lane 3 3G 100-MHz Gen2 dif fer enti al clock to PCIe Graphics
AT 3 4 PEG _A _ CL KR Q# / G PIO 4 7 devic e.
D
AU 3 4 PER N7
Lane 4 GLAN / CARD READER PER P 7
AU 3 6 AD43
Lane 5 X A V3 6 PET N 7
G CL KO UT _ PE G_ A_ N AD45
c E
PET P7 C LK OU T _ PEG _A _P
Lane 6 X
i P
BG 3 4 AN4
C LK _E XP _ N 4
t
PER N8 C L KO UT _ D MI_ N
Lane 7 X BJ
BG
3
3
4
6 PER P 8 CL KO U T_ D MI _P
AN2
C LK _E XP _ P 4
Lane 8 X
a
BJ 3 6 PET N 8
PET P8 AT1 PC H_ C L K _ DP _ N _ R R2 6 6 *1 0 m _il s h o rt _ 0 4 C L K _D P _ N 4
C LK OU T _ DP _ N / C LK OU T _ BCL K1 _ N AT3 PC H_ C L K _ DP _ P_ R R2 6 7 *1 0 m _il s h o rt _ 0 4
CL KO U T_ D P_ P / C L K O UT _ BC L K 1 _P C L K _D P _ P 4
m
3 .3 V 3 .3 V S A K4 8
A K4 7 CL K O U T_ P C IE 0 N
CL K O U T_ P C IE 0 P
e
RN 8 A W 24 100-MHz diff erenti al clock f romPCH to Pr ocessor.
P9 CL KI N_ D MI_ N B A2 4 C L K _ P C IE _I C H # 2 Connect t o PEG_CLK#/PEG_CLKpins of the
1 0 K_ 8P 4 R_ 0 4 PC IEC L K R Q0 #
1 8 P C IE C L KRQ 1 # P C IE C L K R Q 0 # / G P I O 7 3
R C L KIN_ D MI _P C L K _ P C IE _I C H 2 processo
h E
2 7 P C IE C L KRQ 0 #
3 6 AM 4 3 F A P3
c
P C IE C L KRQ 5 #
4 5 P E G_ B _ C LK RQ # AM 4 5 CL K O U T_ P C IE 1 N
F C L KIN _B CL K_ N A P1 C LK _ BUF _B CL K_ N 2
CL K O U T_ P C IE 1 P
U CL KIN _ BC LK _P C LK _ BUF _B CL K_ P 2
B
S
PC IEC L K R Q1 # U4
.
P C IE C L K R Q 1 # / G P I O 1 8 F18
K C L K IN _ D O T _9 6 N E18
C LK _ BUF _D O T9 6 _N 2
AM 4 7 L CL K IN _ DO T _ 9 6P C LK _ BUF _D O T9 6 _P 2
B C
2 3 C L K_ P C IE _ NE W _ CAR D # AM 4 8 CL K O U T_ P C IE 2 N
2 3 C L K_ PCI E _ NE W _ CAR D CL K O U T_ P C IE 2 P AH13
R 283 * 10 m i l _ sh or t_ 04 CL K _ SL O T2 _ O E# N4 mCC LL KIN _ S AT A_ N / CK S SC D_ N A H 12
C L K _ S A TA # 2 C 3 91 2 2p _5 0 V _ N P O _ 04
2 3 N EW C AR D _ C L KRE Q# P C IE C L K R Q 2 # / G P I O 2 0
o KIN _S A T A_ P / C KS SC D _P C LK _ SA T A 2
r
2 3 C L K _ P C IE _ M IN I#
AH 4 2 F P41
C LK _ BUF _R E F 14 2
AH 4 1 CL K O U T_ P C IE 3 N R E F C L K 1 4 IN 1
R2 6 8
2 3 CL K_ P C IE _ M INI CL K O U T_ P C IE 3 P
X6 6-22- 25R00-1B4
A8 J42 1 M_ 0 4 F S X5 L _2 5 M H z
2 3 W L AN _ CL K R EQ # P C IE C L K R Q 3 # / G P I O 2 5 C L K IN _ P C IL O O P B A C K C L K _ P C I_ FB 18 6-22- 25R00-1B5
2
AM 5 1 AH51 XT AL 25 _ IN
2 5 C LK _P CIE _G L AN # AM 5 3 CL K O U T_ P C IE 4 N X TA L2 5 _ IN AH53 XT AL 25 _ O UT C 3 87 2 2p _5 0 V _ N P O _ 04
2 5 CL K_ P CIE_ G L AN CL K O U T_ P C IE 4 P XT A L 2 5 _ OU T
LA N_ C LK REQ # M9 AF38 XCL K_ R CO M P R 87 9 0 . 9 _ 1 % _ 04 9 0. 9- O ? %pu l l u p
P C IE C L K R Q 4 # / G P I O 2 6 X CL K _ R CO MP 1 .1 V S_ V T T
to +VccI O
(1.05V, S0rail )
AJ 5 0 T45
AJ 5 2 CL K O U T_ P C IE 5 N x CL K O UT F L EX0 / G PIO 6 4
CL K O U T_ P C IE 5 P e
P C IE C L K R Q 5 # H6 l P43
P C IE C L K R Q 5 # / G P I O 4 4 F CL K O UT F L EX1 / G PIO 6 5
A K5 3 k T42
A K 5 1 CL K O U T_ P E G_ B _N c CL K O UT F L EX2 / G PIO 6 6
CL K O U T_ P E G_ B _ P o
PE G _ B_ CL K R Q # P1 3 l N 50
PEG _ B_ CL KR Q# / GP I O5 6 C CL K O UT F L EX3 / G PIO 6 7
Ib e x Pe ak -M _ Re v 0 _ 9
3 .3 VS 2,1 0 ,1 1 ,1 2,1 3 ,14 ,1 6 ,1 7,1 8 ,1 9, 20,2 1 ,2 3 ,2 4 ,2 5, 26 ,2 7 ,2 8 ,2 9 ,3 0,3 1 ,3 5 ,3 6

1 .1 VS _ VT T 2 ,4 ,6 ,7 ,1 4, 16 ,1 9 ,2 0 ,2 1 ,3 4, 35 ,3 6
3 .3 V 3,4 ,1 2 ,1 4 ,1 6,1 8, 19 ,2 0 ,2 1,2 3 ,2 4, 25,2 9 ,3 0 ,3 1 ,3 3,3 4 ,3 5
B - 16 IBEXPEAK - M 2/9
Schematic Diagrams
IBEXPEAK - M 3/9
8/18/2019 IBEXPEAK - M (DMI,FDI,GPIO) clevo+6-71-w24h0-d02a.unlocked.pdf

U2 0 C
BA18
B C 24 F DI_ R XN 0 B H1 7 F DI _T XN0 3
3 D MI_ RX N 0 D MI0 R XN F DI_ R XN 1 F DI _T XN1 3
B J 22 B D1 6
3 D MI_ RX N 1 A W 20 D MI1 R XN F DI_ R XN 2 BJ16 F DI _T XN2 3
3 D MI_ RX N 2 B J 20 D MI2 R XN F DI_ R XN 3 BA16 F DI _T XN3 3
3 D MI_ RX N 3 D MI3 R XN F DI_ R XN 4 BE14 F DI _T XN4 3
B D 24 F DI_ R XN 5 BA14 F DI _T XN5 3
3 D MI_ RX P 0 D MI0 R XP F DI_ R XN 6 F DI _T XN6 3
B G 22 B C1 2
3 D MI_ RX P 1 B A 20 D MI1 R XP F DI_ R XN 7 F DI _T XN7 3
33 D
D MI_
MI_ RX
RX P
P 23 B G 20 D MI3
D MI2 R
R XP
XP F D I_ RX P 0 B
B B1 8 F DI _T X P0 3
F17
F D I_ RX P 1 F DI _T X P1 3
B E 22 B C1 6
3 DM I_ TX N 0 B F 21 D MI0 T X N F D I_ RX P 2 B G1 6 F DI _T X P2 3
3 DM I_ TX N 1 D MI1 T X N F D I_ RX P 3 F DI _T X P3 3
B D 20 AW16
3 DM I_ TX N 2 B E 18 D MI2 T X N F D I_ RX P 4 B D1 4 F DI _T X P4 3
3 DM I_ TX N 3 D MI3 T X N F D I_ RX P 5 F DI _T X P5 3
BB14
B D 22 F D I_ RX P 6 B D1 2 F DI _T X P6 3
3 DM I_ TX P 0 B H 21 D MI0 T X P F D I_ RX P 7 F DI _T X P7 3
3 DM I_ TX P 1 B C 20 D MI1 T X P
3 DM I_ TX P 2 B D 18 D MI2 T X P BJ14
3 DM I_ TX P 3 D MI3 T X P F D I_IN T F D I_IN T 3 B
I I BF13
M D F DI_ F S Y NC 0 F D I_ FS Y N C 0 3
R 26 1 49 . 9 _ 1 % _0 4 DMI _C OM P _ R B H 25
1 .1 V S _ V T T D MI_ Z C OM P
D F B H1 3
F D I_ FS Y N C 1 3
.
F DI_ F S Y NC 1
B F 25
S
D MI_ IR CO MP BJ12
F D I_ LS Y NC 0 F D I_ LS Y N C 0 3 c
B G1 4
Sheet 16 of 42
F D I_ LS Y NC 1 F D I_ LS Y N C 1 3
h
IBEXPEAK - M 3/9
e
m
R 11 1 1 0 K _ 04 S Y S _ RE S E T # T6 J 12 P CIE _W A K E #
3.3 V S S Y S _ RE S E T # WAKE# P C IE _W A K E# 2 3,2 5
a
S Y S _ P W R OK M6 Y1 P M_ C LK RUN #
S Y S _ P W R OK C L K RU N# / GP I O3 2 P M _C L K RU N# 2 4 t
t 3 .3 V
n
i
e
S B _ P W RO K B 17 c
P W RO K
m
P CIE _ W A K E # R 12 1 1 K _ 1 %_ 0 4
K5 eS US _S T AT # / GP IO6 1 P8
g
P M_ MPW RO K S 4 _S TA T E # P M_ S L P _ L A N# R 12 7 * 10 K _ 0 4 D
M E P W R OK S 4 _ S TA TE # 2 4
a
n S US C L K / GP IO6 2
S W I# R 13 0 1 0K _0 4
A UX P P W R OK _ R A 10 F3
a
R 29 7 10 K _ 0 4
L A N _ RS T #
i
EXT-LAN M
S US _ P W R _ A CK R 28 4 1 0K _0 4
D9 E4 P W R_ B T N # R 10 9 * 10 K _ 0 4
4 P M_ DR A M _P W RG D D RA M P W R OK S LP _ S5 # / GP IO6 3
r
g
a
C 16
e
w H7
A C_ P R E S E NT R 11 5 1 0K _0 4
o
RS M RS T#
28 R S MR S T# R S MR S T # SLP_S4# S US C # 2 8 ,33
r
R 30 0 10 K _ 0 4
P P M_ B A T L OW # R 29 6 8 . 2 K _0 4
a
m
S U S _P W R_ A C K M1 P12 S US B #
28 S U S _ P W R_ A C K S US _ P W R _A CK / G P IO3 0 SLP_S3# SUS B # 2 3 ,28 ,3 1 3 .3 V S
m
e
t
s
P W R _B T N # P5 K8 P M _C L K RU N# R 27 1 8 . 2 K _0 4
28 P W R _B T N # P W RB T N # S L P _M #
y
s
1 8,2 8 A C _P R E S E N T
A C _P R E S E N T P7
A CP R E S E NT / G P IO 31
S TP23
N2 A L L _ S Y S _ P W R GD R 14 3 1 0K _ 04
P M_ B A T L OW # A6 BJ10
B A TL O W # / GP IO 7 2 P M S Y N CH H_ P M _ S YN C 4
S W I# F 14 F6 P M_ S L P _ L A N#
28 S W I# RI # S L P _ LA N #
R1 3 9 *1 0 m il_ s ho rt_ 0 4 P M_ M P W RO K
2 8, 36 V C OR E _ ON
Ibe x P e a k- M_ Re v 0 _ 9
3 .3 V
3 .3 V
3.3 V 3 .3V
U8 D
4
1
U8A 4 U 8C 7 4 LV C 0 8P W R1 4 4 *1 0 m il _ s ho rt_ 0 4 S B _P W RO K
1 12
7 4 L V C0 8 P W 4 U8 B 7 4 LV C0 8 P W
1 9 4 ,3 6 DE L A Y _ P W RG D 11 S Y S _ P W R OK
4 74 L V C 08 P W R1 4 2 *1 0 m il _ s ho rt_ 0 4
1 4 4 ,3 3,3 4 1 .1 V S _ V T T_ P W R GD 8 13
A L L_ S Y S _ P W RG D
1 33 1.8 V S _ P W RGD 6 1 .1 V S _ V T T_ E N 10
3 3 DD R1 . 5 V _ P W R GD
3 5 7
R1 4 5
SUSB# 2
7
10 K _ 0 4
7 A L L _ S Y S_ P W R GD 1 2 ,28
7 34 1 .1 V S _ V T T _E N
R 14 1 2K _1 % _ 0 4
H_ V T T PW R GD 4
C 4 70
ON R 13 8
1 u _ 6.3 V _ X 5 R_ 0 4
1 K _ 1% _ 0 4
3 .3V S 2 ,10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 7,1 8,1 9 ,2 0, 21 ,2 3 ,2 4,2 5,2 6, 27 ,2 8,29 ,3 0 ,3 1,3 5 ,3 6
3 .3V 3 ,4,1 2 ,1 4 ,15 ,1 8 ,1 9,2 0,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3,3 4,3 5
1 .1V S _V TT 2 ,4 ,6 ,7, 14 ,1 5 ,19 ,2 0 ,2 1,3 4 ,3 5 ,36
IBEXPEAK - M 3/9 B - 17
Schematic Diagrams
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf IBEXPEAK - M 4/9 67/96

8/18/2019 IBEXPEAK - M (LVDS,DDI)

U20D
T48 BJ46
12 BLON L_BKLTEN SDVO_TVCLKI NN BG46
T47
12 NB_ENAVDD L_VDD_EN SDVO_TVCLK INP
Y48 L_BKLTCTL SDVO_STALLN B

BJ
G44
88
AB48 SDVO_STALLP
12 P_DDC_CLK Y45 L_DDC_CLK BF45
3.3VS
12 P_DDC_DATA L_DDC_DATA SDVO_INTN BH45
L_CTRL_CLK AB46 SDVO_INTP
R 96 * 10 K
_04
R 97 * 10 K
_04 L_CTRL_DATA V48 L_CTRL_CLK
L_CTRL_DATA
R83 2.3
7K_
1%_04 LVD
S_IBG AP39 T51
s
AP41 LVD_IBG SDVO_CTRLCLK T53
LVD_VBG SDVO_CTRLDATA
AT43
m
AT42 LVD_VREFH BG44
LVD_VREFL DDPB_AUXN BJ44
a
DDPB_AUXP AU38
r
AV53 DDPB_HPD
12 LVDS-LCLKN
AV51 LVDSA_CLK# S BD42 B
Sheet 17 of 42 12 LVDS-LCLKP
D O
g
LVDSA_CLK DDPB_0N BC42 V
BB47 V DDPB_0P BJ42 t D
12 LVDS-L0N BA52 LVDSA_DATA#0 L DDPB_1N r
a
BG42 S
e o
i IBEXPEAK - M 4/9 12 LVDS-L1N

12 LVDS-L2N
AY48 LVDSA_DATA#1
AV47 LVDSA_DATA#2
LVDSA_DATA#3
c
a
DDPB_1P
DDPB_2N
DDPB_2P
BB40
BA40
AW38
RN 5
P

y
f 2.2K_4P2R_04
D BB48 DDPB_3N BA38 3 2 a

12 LVDS-L0P BA50 LVDSA_DATA0 r DDPB_3P 4 1
3.3VS l
12 LVDS-L1P
AY49 LVDSA_DATA1 e p
t
c
12 LVDS-L2P s
AV48 LVDSA_DATA2 Y49
n i
i
LVDSA_DATA3 DDPC_CTRLCLK AB49 HDMI_CTRLCLK13 D
I
t
DDPC_CTRLDATA HDMI_CTRLDATA 13
y
AP48
a AP47 LVDSB_CLK#

LVDSB_CLK a
l
BE44
DDPC_AUXN BD44
DDPC_AUXP AV40
p
AY53 PCH_DDPC_HPD
m AT49 LVDSB_DATA#0 DDPC_HPD

EMI AU52 LVDSB_DATA#1 s
i
BE40 HDMIB_D2BN_C C125 0.1u_10V
_X7R
_04
e
HDMIB_D2BN 13 C
D
R10 5 0_ 0
4 DAC_BLUE_R AT53 LVDSB_DATA#2 DDPC_0N BD40 HDMIB_D2BP_C C126 0.1u_10V
_X7R
_04
13 DAC_BLUE LVDSB_DATA#3 DDPC_0P BF41 HDMIB_D2BP13 t
C174 HDMIB_D1BN_C C111 0.1u_10V
_X7R
_04
DAC_GREEN_R AY51 DDPC_1N BH41 HDMIB_D1BP_C HDMIB_D1BN 13 r
l
h
*33p_50V_NPO
_04 R99 0_04 C112 0.1u_10V
_X7R
_04 o
13 DAC_GREEN AT48 LVDSB_DATA0 DDPC_1P HDMIB_D1BP13
a
BD38 HDMIB_D0BN_C
c
C170 C113 0.1u_10V
_X7R
_04 HDMIB_D0BN 13 P
AU50 LVDSB_DATA1 DDPC_2N
13 DAC_RED
*33p_50V_NPO
_04 R91 0_04 DAC_RED_R
t BC38 HDMIB_D0BP_C C114 0.1u_10V
_X7R
_04
HDMIB_D0BP13

y
i
C166 AT51 LVDSB_DATA2 DDPC_2P BB36 HDMIB_CLKBN_C C115 0.1u_10V
_X7R
_04
S
LVDSB_DATA3 DDPC_3N HDMIB_CLKBN 13 a
g
*33p_50V_NPO
_04 BA36 HDMIB_CLKBP_C C116 0.1u_10V
_X7R
_04 l
.
DDPC_3P HDMIB_CLKBP 13
i p
NEAR PCH AA52 D U50

s
B
R1
04 150_1%_04 DAC_BLUE_R i
R9
8 150_1%_04 DAC_GREEN_R AB53 CRT_BLUE DDPD_CTRLCLK U52 D
R9
2 150_1%_04 DAC_RED_R AD53 CRT_GREEN DDPD_CTRLDATA 5VS
CRT_RED
BC46 Q7
V51 DDPD_AUXN BD46 G
MTN7002ZHS3
13 DAC_DDCACLK V53 CRT_DDC_CLK DDPD_AUXP AT38
13 DAC_DDCADATA CRT_DDC_DATA DDPD_HPD PCH_DDPC_HPD S D
PORTC_HPD 13
BJ40 D
Y53 DDPD_0N BG40
13 DAC_HSYNC Y51 CRT_HSYNC DDPD_0P BJ38 t
R34
13 DAC_VSYNC CRT_VSYNC DDPD_1N BG38 r
DDPD_1P o
BF37 100K_1%_04 P
R8
8 1K_1%
_04 DA
C_IR EF_R AD48 T DDPD_2N BH37
AB51 DAC_IREF R DDPD_2P BE36 y
CRT_IRTN C DDPD_3N
DDPD_3P
BD36 a
l
p
IbexPeak-M_Rev0_9 s
i
Connect to GND D
PC H_ D
DPC _HP D R33 *0_04 PO
R TC _
HPD
No Connect
External Graphics (PCH I ntegrated Graphics Disable)
External Graphics (PCH Integrated Graphics Disable)
2,10,11,12,13,14,15,16,18,19,20,21,23,24,25,26,27
,28,29,30,31,35,36 3.3VS
2,13,20,21
,26,27,30,31,35,36 5V S
Schematic Diagrams
IBEXPEAK - M 6/9
IBEXPEAK M (GPIO,VSS_NCTF,RSVD)

U20F
E DP _ CAR D _D E T # Y3 AH 4 5
0213 S_GPIO CHANGE TO EDP_CARD_DET# B M B U S Y # / G P IO 0 C LK OU T _ P C IE6 N AH 4 6
S MI # C38 C L KO UT _ P C IE6 P
28 S M I# T AC H 1 / G PIO 1
3 .3 V S R 27 2 1 K _ 1 % _ 04 ED P_ C ARD _ D E T #
DG P U _ HPD _ IN TR # D37
T AC H 2 / G PIO 6
C AF 4 8
R273
28 S C I#
S CI # J32
T AC H 3 / G PIO 7 S C LK OU T _ P C IE7 N
C L KO UT _ P C IE7 P
AF 4 7
I
* 0 _ 04
27 P CH _ MU T E#
P CH _ M UT E# F10
G P IO 8
M R 27 6 1 0 K _0 4 3. 3V S
R 12 6 * 10 K _0 4 K9 U2
3. 3V L AN _ PH Y_ P W R _C T R L / GP IO1 2 A 2 0G AT E G A2 0 28
HO S T _ AL ER T #1 T7
B IO S _ R E C G PIO 1 5
3 .3 V S R 10 1 10 K_ 04
R 2 70 * 1 0 K _0 4 AA2 AM 3
3 .3 VS S AT A 4 GP / G PIO 1 6 C L K O UT _ BC L K 0 _N / C LK OU T _ PC IE8 N B C L K _C P U _ N 4
R102 GPI O1 7 F38 AM 1 R 25 6 * 10 K _ 0 4

BIOS RE COVERY BC LK _ CPU _ P 4 1 .1 V S _ VT T
s
T AC H 0 / G PIO 17 C L KO UT _ BC L K0 _ P / C L KO UT _ P C IE8 P
DISABLE----NO STUFF (DEFAULT) * 0 _ 04 B IO S_ RE C Y7 BG 1 0 H_ P E CI_ R R 26 0 * 1 0 m il _s ho rt _ 0 4
ENABLE-----STUFF S CL O CK / G P IO 22 O PE CI H _ P E C I 4 ,2 8
I
m
H10 T1
/ GP IO2 4 P
R 27 7 1 0 K _0 4 3 .3 VS
M EM _ L ED R C IN #
G
a
KB C_ R ST # 2 8
S B_ BL O N AB1 2 BE1 0
12 SB _B L ON H _ CPUPW RG D 4
r
R 28 1 * 10 K _ 0 4 C RB _S V_ DE T G PIO 2 7 PR O C PW RG D
3 .3 V S S PI_ C S # 2 V1 3 U BD 1 0 R 25 9 56 _ 0 4 R 25 5 56 _ 0 4
P
g Sheet 19 of 42 CRB/SV DETECT R280 S T P_ PC I# M11
G PIO 2 8
C
T HR M T RIP#
H _ TH R MTR IP#
1. 1V S_ VT T
a
S T P _ P C I # / G P IO 3 4
i IBEXPEAK - M 6/9 NO STUFF [DETECT] 1 0 0 K_ 1 % _ 0 4 GPI O3 5 V6

S AT A C LK RE Q# / G P IO 3 5
Connected to PCH( THRM
Rou
TRIP#)
t i ng guideli nes avail able in
D
R 27 9 * 1 K_1 % _0 4 AB7 BA2 2
3 .3 VS S AT A 2 GP / G PIO 3 6 T P1 Calpell a Desi gn Guide.
DG P U _ PRS NT # AB1 3 AW 2 2 NOTE: CRB uses a 54.9 O ?%
S AT A 3 GP / G PIO 3 7 T P2
c
R 95 10 K_ 04 SV _S E T _ UP se ri e s re si st o r a nd56- O pul l - up.
3 .3 V S
i
MF G _ M OD E V3 BB2 2
S LO A D / G P IO 3 8 T P3
t R100 CR B _ SV_ D E T P3

S DAT A OU T 0 / G P IO 39 T P4
AY 4 5
a * 0 _ 04 H3
P CIE CL KR Q 6# / GP IO4 5 T P5
AY 4 6
m
DR A M RS T_C T RL F1 AV4 3
4 ,9 D RA MR ST _ C TR L P CIE CL KR Q 7# / GP IO4 6 T P6
e
S V_ SET _ U P AB6 AV4 5
S DAT A OU T 1 / G P IO 48 T P7
AA4 AF 1 3
3 C RI T_ T EM P _ R EP# R 26 9 * 0_ 0 4 CR IT _ T EMP _R E P #_ R S AT A 5 GP / G PIO 4 9 T P8
h
3. 3V
c
R 12 8 1 0 K _0 4 P CH _ GPI O5 7 F8 M1 8
G PIO 5 7 T P9
S
R 10 7 1 K _0 4 H OS T_ AL E RT # 1 N1 8
TP 10
. RN 9
1 0 K_ 8 P 4 R _0 4
A4
A4 9 V SS_ N CT F _ 1 TP 11
AJ 2 4
B D
1 8 A5 V SS_ N CT F _ 2 AK4 1
P CH _ MU T E#
2 7 S P I_ CS #2 A5 0 V SS_ N CT F _ 3 V TP 12
3 6 D R A MR S T _ C TR L A5 2 V SS_ N CT F _ 4 S AK4 2
4 5 A5 3 V SS_
V SS_
N
N
CT
CT
F
F
_
_
5
6
R TP 13
B2 M3 2
B4 V SS_ N CT F _ 7 TP 14
B5 2 V SS_ N CT F _ 8 N3 2
B5 3 V SS_ N CT F _ 9 TP 15
BE1 V SS_ N CT F _ 1 0 M3 0
3 .3 VS BE5 3 V SS_ N CT F _ 1 1 TP 16
BF1 V SS_ N CT F _ 1 2 N3 0
BF 5 3 V SS_ N CT F _ 1 3 TP 17
BH1 V SS_ N CT F _ 1 4 H1 2
R 1 14 * 1 0 K _0 4 G P IO 1 7
BH2 V SS_ N CT F _ 1 5 TP 18
BH 5 2 V SS_ N CT F _ 1 6 F AA2 3
R N2 1
1 0 K_ 8 P 4 R _0 4 BH 5 3 V SS_ N CT F _ 1 7 T TP 19
1 8 S C I# BJ 1 V SS_ N CT F _ 1 8 C AB4 5
2 7 S M I# BJ 2 V SS_
V SS_
N
N
CT
CT
F
F
_
_
1
2
9
0
N N C _1
3 6 MF G_ M OD E BJ 4 AB3 8
4 5 S T P _ P C I# BJ 4 9 V SS_ N CT F _ 2 1 N C _2
BJ 5 V SS_ N CT F _ 2 2 AB4 2
BJ 5 0 V SS_ N CT F _ 2 3 N C _3
RN 4
BJ 5 2 V SS_ N CT F _ 2 4 AB4 1
1 0 K_ 8 P 4 R _0 4
1 8 DG PU _ HP D_ IN TR# BJ 5 3 V SS_ N CT F _ 2 5 N C _4
2 7 CR IT _ T EM P_ RE P# _ R D1 V SS_ N CT F _ 2 6 T39
3 6 DG PU _ PR SNT # D2 V SS_ N CT F _ 2 7 N C _5
4 5 GP IO3 5 D53 V SS_ N CT F _ 2 8
E1 V SS_ N CT F _ 2 9 P6
E5 3 VV SS_
SS_ N
N CT
CT FF __ 33 01 IN IT 3 _3 V#
C1 0
TP 24
I be x Pe a k -M _ Re v 0 _ 9
R 10 3 * 10 K _ 0 4 DG P U _ PR SN T #
LOW: DGPU PRESENT 2 ,4 ,6 ,7 ,1 4 ,1 5 , 1 6 ,2 0 ,2 1, 34 ,3 5 ,3 6 1 .1 VS _V T T

3 ,4 ,1 2 ,1 4 ,1 5 ,1 6 ,1 8, 20 ,2 1 ,2 3 ,2 4 ,2 5 ,2 9 ,3 0 ,3 1, 33 ,3 4 ,3 5 3 .3 V
2 ,1 0 ,1 1 ,1 2 ,1 3, 14 ,1 5 ,1 6 ,1 7 ,1 8 ,2 0 ,2 1, 23 ,2 4 ,2 5 ,2 6 ,2 7 ,2 8 ,2 9 ,3 0, 31 ,3 5 ,3 6 3 .3 VS
Schematic Diagrams
IBEXPEAK - M 7/9
IBEXPEAK - M (POWER)
R90 3 .3 VS
H C B1 6 0 8K F -1 2 1 T2 5
8/18/2019 clevo+6-71-w24h0-d02a.unlocked.pdf .
1 .1 V S_ VT T VCC A_ D A C _ 3. 3V S L12 5 VS
U20G POWER H CB1 6 0 8 KF - 12 1 T 2 5 U5
AB2 4
AB2 6 VC C CO R E[1 ] VC CA DAC [1 ]
AE5 0 . 5
OU T IN
1
C 17 6 C 1 51 AB2 8 VC C CO R E[2 ] AE5 2 C 3 93 C392 C1 3 2 C145 C 13 3 C1 4 6 R8 0 C 15 0

AD 2 6 VC C CO R E[3 ] VC CA DAC [2 ] 3 4
0
VC C CO R E[4 ] 8 S HD N # _
T
1 0 u _6 .3 V _X5 R _ 0 6 1u _ 6 .3 V_ X5 R _0 4 AD 2 8 AF 5 3 0 .0 1 u _ 50 V _X7 R _ 04 4 8
0 1 0 u _ 6 .3 V_ X5R _ 0 6 4 0 *2 3 .7 K_ 1 % _ 0 4
VC C CO R E[5 ] VSSA _ DAC [1 ] 0 0 R
AF 2 6 _ _ 4 2
R
_ _ 5
AF 2 8 VC C CO R E[6 ] AF 5 1 V R V R
5 SET GN D X
5 5 5 _
VC C CO R E[7 ] VSSA _ DAC [2 ] Y X Y X V
AF 3 0 R8 1 * APL 5 6 0 3 -33 B
R
E
O C
VC C CO R E[8 ] _ _ _ _ 3
.
AF 3 1 V V V V 6
6 3
. 6 3
. _
VC C CO R E[9 ] 1
C
AH 2 6 _
6 1
_
6 *1 0 K_ 1 % _ 0 4 u
1
AH 2 8 VC C CO R E[1 0 ] 3 .3 V S _ V C CA_ L VD u _ 3 .3 VS u _
u *
1 u 1 2
VC C CO R E[1 1 ] . 2 .
C
AH 3 0 2 2
VC C CO R E[1 2 ]
0 0
APL5603-33B 6- 02-56033- 4C0
C
AH 3 1 AH3 8 R 86 *1 5 m i _l s h o rt_ 0 6
VC C CO R E[1 3 ] V CC AL VD S G9091-330T11UF 6- 02-90913-4C0
V
AJ 3 0
AJ 3 1 VC C CO R E[1 4 ] AH3 9 C1 5 6
1 .1 V S_ VT T VC C CO R E[1 5 ] V SSA_ L VD S
1 0 u_ 6 .3 V_ X5 R _0 6
AP4 3 1 .8 VS _V CC T X_ LV D 1 .8 VS
B
VC CT X_ L VD S[1 ] AP4 5 L 11
VC CT X_ L VD S[2 ] AT 4 6
.
HC B1 6 0 8 KF -1 2 1 T 2 5
S
VC CT X_ L VD S[3 ]
.
1. 1V S_ VC C AP L L_ E XP AK2 4 AT 4 5
S
L29 VC C IO[ 24 ]
D VC CT X_ L VD S[4 ]
* BKP1 0 0 5 HS 12 1 _ 0 4 V C1 4 0 C1 3 9 C135 C1 3 4
c
. BJ 2 4
L
C3 7 2
VC C APL L EXP
VC C3 _ 3 [2 ]
AB3 4 0. 01 u _ 5 0 V_ X7 R_ 0 4 0 .0 1u _ 5 0 V_ X7 R_ 0 4 1 0 u _ 6 .3 V_ X5 R_ 0 6 10 u _ 6 .3 V_ X5 R_ 0 6 Sheet 20 of 42 h
AN 2 0 AB3 5
IBEXPEAK - M 7/9
AN 2 2 VC C IO[ 25 ] VC C3 _ 3 [3 ]
e
*1 0 u _ 6 .3 V_ X5 R_ 0 6
AN 2 3 VC C IO[ 26 ]
S AD3 5 3 .3 VS m
AN 2 4 VC C IO[ 27 ]
O VC C3 _ 3 [4 ]
M
AN 2 6 VC C IO[ 28 ]
AN 2 8 VC C IO[ 29 ]
C a
1 .1 VS_ VT T BJ 2 6 VC C IO[ 30 ]
V C1 5 9
BJ 2 8
AT 2 6
VC C IO[
VC C IO[
31 ]
32 ] H 0. 1u _ 1 6 V_ Y 5V _ 04
t
i
AT 2 8 VC C IO[ 33 ] c
C3 7 5 C160 C 1 61 C1 3 6 C141 AU 2 6 VC C IO[ 34 ]
AU 2 8 VC C IO[ 35 ] 1 .5 VS _ 1. 8V S
AV2 6 VC C IO[ 36 ]
1 0 u_ 6 .3 V_ X5 R _ 06 1 u _ 6 .3 V_ X5 R_ 0 4 1 u _ 6 .3 V_ X5R _ 0 4 1 u_ 6 .3 V_ X5 R _ 04 1 u _ 6 .3 V_ X 5 R_ 0 4
AV2 8 VC C IO[ 37 ] AT 2 4
D
AW26 VC C IO[ 38 ] VC C VRM [2 ]
AW28 VC C IO[ 39 ]
i
VC C IO[ 40 ]
I
BA2 6 AT 1 6 1 .1 VS _ VT T
BA2 8 VC C IO[ 41 ] VC C DM I[1 ]
BB2 6 VC C IO[ 42 ] AU1 6

M
D
BB2 8 VC C IO[ 43 ] VC C DM I[2 ]
g
a
BC 2 6 VC C IO[ 44 ] r
C1 2 7
VC C IO[ 45 ]
*
BC 2 8 a
VC C IO[ 46 ]
E
BD 2 6 1 u _ 6 .3 V_ X5 R_ 0 4
BD 2 8 VC C IO[ 47 ] m
VC C IO[ 48 ]
I
BE2 6 AM1 6
VC C IO[ 49 ] VC C PN A ND [1 ]
C
BE2 8 AK1 6
BG 2 6 VC C IO[ 50 ] VC C PN A ND [2 ] AK2 0 V_ NV RAM _ VC CQ 1 .8 VS 3 .3 V S
P
BG 2 8 VC C IO[ 51 ] VC C PN A ND [3 ] AK1 9
s
BH 2 7 VC C IO[ 52 ] VC C PN A ND [4 ] AK1 5 R7 5 *0 _ 0 4
VC C IO[ 53 ] VC C PN A ND [5 ] AK1 3
AN 3 0 VC C PN A ND [6 ] AM1 2 C1 5 2 R76 * 1 5m i l _ s ho r t _0 6
I
AN 3 1 AM1 3
P
1 . 5 V S _1 . 8 V S 3 . 3V S AM1 5 0. 1u _ 1 6 V_ Y 5V _ 04
VC C PN A ND [9 ]
AN 3 5
VC C 3 _3 [1 ]
S
/
1 .1 VS_ VT T 1. 1V S_ VC CAP L L_ F DI
D
L 28 AT 2 2
N
* HC B1 0 0 5 KF -1 2 1 T 2 0 VC C VR M[1 ] 3. 3V S 3 .3 V
A
BJ 1 8 AM8 VC CM E3 .3 V
VC C F D IPL L VC C ME3 _ 3 [1 ]
N
AM9 R 79 * 1 5 m il_ s h o rt_ 06
VC C ME3 _ 3 [2 ]
I
C3 7 0 AM 2 3 AP1 1
D
VC C IO[ 1] VC C ME3 _ 3 [3 ] AP9 R 82 * 0_ 0 4
VC C ME3 _ 3 [4 ]
*1 0 u _ 6. 3V _ X5 R _ 0 6
F C1 3 8
Ib e x Pe a k -M _ Re v 0 _ 9 0 .1 u_ 1 6 V_ Y 5 V_ 0 4
1 .1 VS_ V TT 1 .1 VS_ VC CD PL L _ F D I
R25 7 * 1 5 mi l _ s ho rt _ 0 6
3 ,4 ,1 2 ,1 4 ,1 5 ,1 6, 18 ,1 9 ,2 1 , 2 3 ,2 4 ,2 5 ,2 9, 30 ,3 1 ,3 3 ,3 4 ,3 5 3 .3 V
2 3 ,3 1 ,3 6 1 .5 VS
2 ,1 3 ,1 7 ,2 1 ,2 6, 27 ,3 0 ,3 1 ,3 5 ,3 6 5 VS
21 1 .5 VS_ 1 .8 VS
7 ,3 3 1 .8 VS
2 ,1 0 ,1 1 ,1 2, 13 ,1 4 ,1 5 ,1 6 ,1 7 , 1 8 ,1 9, 21 ,2 3 ,2 4 ,2 5 ,2 6 ,2 7 ,2 8, 29 ,3 0 ,3 1 , 3 5 ,3 6 3 .3 VS
2 ,4 ,6 ,7 ,1 4 ,1 5 , 1 6, 19 ,2 1 ,3 4 ,3 5 ,3 6 1 .1 VS_ VT T
1 .5 VS 1 . 8 VS 1 .5 V S _ 1.8 V S
R 2 58 * 15 m il_ s h o rt_ 0 6
R 2 54 * 0 _0 4
Schematic Diagrams
IBEXPEAK - M 8/9 71/96
Volt age Rai l Volta
ge S0 Iccm ax Curr ent (A )
IBEXPEAK - M (POWER) V_CP U_IO 1.1/1. 05 < 1 (mA)
8/18/2019 L3 2
1 .1 VS_ VCCA _C LK U2 0 J POWER 1 .1 V S_ VT T
V5RE F
V5RE F_Sus
Vcc3 _3
5
5
3.3
< 1 (mA )
< 1 (mA )
0.357
*H C B 1 0 05 K F -1 2 1T 2 0
52mA AP5 1 V2 4
VccA Clk 1.05 0.052
1 .1 VS _ V TT V C C A C L K [1 ] VC C IO [5 ] V2 6
C3 8 3 C3 8 4 AP5 3 VC C IO [6 ] Y2 4 C1 4 7 VccA DAC 3.3 0.069
V C C A C L K [2 ] VC C IO [7 ] Y2 6
VC C IO [8 ] VccA DPLLA 1.05 0.068
*1 0 u _6 .3 V_ X5 R _0 6 *0 .1 u_ 1 6 V_Y 5 V _0 4 1 u_ 6 .3 V_X5 R_ 0 4
AF 2 3 V2 8 VccA DPLLB 1.05 0.069
VCC LAN [1 ] VCC SUS 3_ 3 [1 ] U2 8 3 .3V
320mA AF 2 4 VCC SUS 3_ 3 [2 ] U2 6 Vcca pllEXP 1.05 0.040
1 .1VS _VT T VCC LAN [2 ] VCC SUS 3_ 3 [3 ] U2 4
142.6mA
VCC SUS 3_ 3 [4 ]
VccC ore 1.05 1.432
C1 4 3 T P_ PCH _ VCC DSW Y2 0 VCC SUS 3_ 3 [5 ] P2 86 C1 8 1 VccD MI 1.05 0.058
1 u_ 6 .3 V_X5 R_ 0 4 DCP SUSBY P VCC SUS 3_ 3 [6 ] N2 8
VCC SUS 3_ 3 [7 ] N2 6 VccD MI 1.1 0.061
C1 7 2 0 .1u _ 1 6V_ Y 5V_ 0 4
A D3 8 VCC SUS 3_ 3 [8 ] M2 8
V C C M E [1 ] VCC SUS 3_ 3 [9 ] VccF DIPLL 1.05 0.037
0.1 u _ 16 V_ Y5 V_ 0 4 M2 6
A D3 9 VC CSU S3 _3 [1 0 ] L2 8 VccI O 1.05 3.062
V C C M E [2 ] VC CSU S3 _3 [1 1 ] L2 6
1849mA VccL AN 1.05 0.320
A D4 1 B VC CSU S3 _3 [1 2 ] J2 8
1 .1VS _VT T V C C M E [3 ] S VC CSU S3 _3 [1 3 ] J2 6 3 .3 V _ V C C P U S B VccM E 1.05 1.849
s U
C3 7 3 C1 4 8 AF 4 3 VC CSU S3 _3 [1 4 ] H2 8
V C C M E [4 ] VC CSU S3 _3 [1 5 ] H2 6 VccM E3_3 3.3 0.085
R1 0 6 * 1 5 mi l _ sh or t_ 06
2 2u _ 6 .3V_ X 5 R_ 0 8 1u _ 6 .3V_ X5 R_ 0 4 AF 4 1 VC CSU S3 _3 [1 6 ] G2 8 Vccp NAND 1.8 0.156
m
V C C M E [5 ] VC CSU S3 _3 [1 7 ] G2 6 C1 7 8
AF 4 2 VC CSU S3 _3 [1 8 ] F28 VccR TC 3.3 2 (mA)
a
V C C M E [6 ] VC CSU S3 _3 [1 9 ] F26 0 .1u _ 1 6V_ Y 5V_ 0 4 VccS ATAPLL 1.05 0.031
V3 9 VC CSU S3 _3 [2 0 ] E2 8
r
V C C M E [7 ] VC CSU S3 _3 [2 1 ] E2 6 VccS us3_3 3.3 0.163
V4 1 s VC CSU S3 _3 [2 2 ] C2 8
Sheet 21 of 42
C3 7 4 C1 4 2
u VccS usHDA 3.3 0.006
g
V C C M E [8 ] VC CSU S3 _3 [2 3 ] C2 6
2 2u _ 6 .3V_ X 5 R_ 0 8 1u _ 6 .3V_ X5 R_ 0 4 V4 2 o VC CSU S3 _3 [2 4 ] B2 7 1.1 VS_ V T T
VccV RM 1.8/1. 5 0.196
e
a
V C C M E [9 ] VC CSU S3 _3 [2 5 ] A2 8
n VccV RM 1.05 < 1 (mA )
i IBEXPEAK - M 8/9 Y3 9
Y4 1
VCC ME[1 0 ] a
l
VC CSU S3 _3 [2 6 ]
VC CSU S3 _3 [2 7 ]
A2 6
U2 3
5 V_PC H_ VC C5 REF SU S
D 11
C
S C D 34 0
A
VccA LVDS 3.3 < 1 (mA )
l 3.3 V
D
VCC ME[1 1 ] VC CSU S3 _3 [2 8 ] VccT X_LVDS 1.8 0.059
Y4 2 e V2 3 R 12 3
1 .1 VS_ VT T C 1 77 0 .1 u _1 6V _Y 5 V _ 0 4 VCC ME[1 2 ] c V C C IO [5 6 ] 10 0 _ 1% _ 0 4
5V
s
c
L3 1 1.1 VS_ V C CA_ A _ DP L F24 C1 8 2
i V 5 REF _ SUS
i
HC B 10 0 5 KF -1 21 T 2 0
VCC RT CEXT V9 M 1 u_ 6 .3 V_X 5 R_ 0 4 D 10 S C D 34 0
t
DCP RT C VCC 5 REF C A
C 3 86 C 38 1 1 .5 VS_ 1 .8VS d 3 .3 VS
a
R 2 62 n K4 9 R 11 6 1 0 0 _1 % _0 4
2 2 u _6 .3 V _ X5 R _0 8 1 u _6 .3 V_ X5 R _0 4 A U2 4 a V5 REF 5V S
* 0 _0 4
68mA V C C V R M [3 ] C 1 83
k C
m
L3 0 J3 8
HC B 10 0 5 KF -1 21 T 2 0 1.1 VS _ VC CA_ B_ DPL
69mA
BB5 1 c P VCC 3_ 3 [8 ] 3. 3VS
1 u _ 6.3 V _ X 5R _ 04
BB5 3 V C C A D P L L A [1 ] o L L3 8
e
C1 6 9
V C C A D P L L A [2 ] l / VCC 3_ 3 [9 ]
C 3 85 C 37 8
C O M3 6 0 .1u _ 1 6V_ Y 5V_ 0 4
+ C3 82 B D5 1
I VCC 3 _3 [1 0 ]
V C C A D P L L B [1 ]
h
2 2 u _6 .3 V _ X5 R _0 8 1 u _6 .3 V_ X5 R _0 4 B D5 3
P N3 6
c
*2 20 u _ 4V_ V_ B V C C A D P L L B [2 ]
G VCC 3 _3 [1 1 ]
C 154 1 u_ 6.3 V _X 5 R _0 4 A H2 3 / P3 6
AJ 3 5 VCC IO[2 1 ] I VCC 3 _3 [1 2 ] 3. 3VS
S C
A H3 5 VCC IO[2 2 ] U3 5 C1 8 0
.
VCC IO[2 3 ] P VCC 3 _3 [1 3 ]
C 131 1 u_ 6.3 V _X 5 R _0 4 AF 3 4 0 .1u _ 1 6V_ Y 5V_ 0 4
V C C IO [2 ] AD1 3
B
VCCIO 3062mA A H3 4 VCC 3 _3 [1 4 ]
1 .1 VS_ VT T V C C IO [3 ] L3 3
C 157 1 u_ 6.3 V _X 5 R _0 4 AF 3 2 1.1 VS_ V CC AP L L *HC B 1 00 5 KF -1 2 1T 2 0
V C C IO [4 ] AK3
VC CSAT AP L L [1 ] AK1 1 .1VS_ VT T
V1 2
DCP SST VC CSAT AP L L [2 ]
C3 8 8 C3 8 9
C 1 75 0 .1 u _1 6V _Y 5 V _ 0 4 VCC SST
*1 u _ 6.3 V_ X5R _ 04 *1 0 u_ 6 .3 V_X5 R_ 0 6
C 1 73 0 .1 u _1 6V _Y 5 V _ 0 4 1 .1V_ IN T_ VC CSU S Y2 2
DCP SUS AH2 2
V C C IO [9 ]
20.4mA P1 8 AT 20
3 .3 V VCC SUS3 _ 3[2 9 ] V C C V R M [4 ] 1 .5 VS_ 1 .8VS
C1 8 8 U1 9
VCC SUS3 _ 3[3 0 ] AH1 9
U2 0 C A V C C IO [1 0 ]
0.1 u _ 16 V_ Y5 V_ 0 4
VCC SUS3 _ 3[3 1 ]
P T AD2 0
U2 2 L A V C C IO [1 1 ]
VCC SUS3 _ 3[3 2 ]
/ S AF 2 2 1 .1 V S_ VT T
O V C C IO [1 2 ]
I AD1 9
357mA V1 5 P V C C IO [1 3 ] AF 2 0
3 .3 V S VCC 3_ 3 [5 ] G V C C IO [1 4 ] AF 1 9 C1 6 7
C1 7 9 V1 6 / V C C IO [1 5 ] AH2 0
VCC 3_ 3 [6 ] I V C C IO [1 6 ] 1 u_ 6 .3 V_X5 R_ 0 4
0.1 u _ 16 V_ Y5 V_ 0 4 Y1 6 C AB1 9 1 4 RT C V CC
VCC 3_ 3 [7 ] P V C C IO [1 7 ] A B 2 0 2 ,1 0,1 1 ,1 2,1 3 ,1 4,1 5 ,1 6, 17 ,1 8 , 19 ,2 0 ,23 ,2 4 ,25 ,2 6 ,27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,3 6 3 .3 V S
V C C IO [1 8 ] AB2 2 2 0 1 .5 VS_ 1 .8V S
V C C IO [1 9 ] A D2 2 2 ,13 ,1 7 ,20 ,2 6 ,27 ,3 0 ,31 ,3 5 ,3 6 5 VS
<1mA AT 1 8 V C C IO [2 0 ] 4,9 ,1 0 ,11 ,2 3 ,27 ,2 9 ,31 ,3 3 ,3 6 1 .5 V
1 .1VS_ VT T V_C PU_ IO [1] 24 ,3 0 ,31 ,3 3 ,3 4 5 V
AA3 4
V C C M E [1 3 ] 1.1 VS_ VT T 3 ,4 ,1 2, 14 ,1 5 ,16 ,1 8 ,19 ,2 0 ,23 ,2 4 ,25 ,2 9 ,30 ,3 1 ,33 ,3 4 ,3 5 3 .3 V
C1 4 4 C1 3 7 C1 6 2 U Y3 4
A U1 8 V C C M E [1 4 ] Y3 5 2 ,4 ,6,7 ,1 4 ,15 ,1 6 ,19 ,2 0 ,34 ,3 5 ,3 6 1 .1 VS_ VT T
V_C PU_ IO [2] P V C C M E [1 5 ]
1u _ 6 .3V_ X5 R_ 0 4 0 .1u _ 1 6V_ Y 5V_ 0 4 0.1 u _ 16 V_ Y5 V_ 0 4 C V C C M E [1 6 ]
AA3 5
1 .5 V _ V C C S U S H D A 1 .5 V 3 .3V
2mA A1 2 L3 0 R 1 29 * 1 5 mi l _ sh o r t_0 6
RT CVC C VCC RT C C VC CSU SHDA
C1 8 6 C1 8 7 T HDA C1 8 9 R 13 1 * 0_ 0 4
Ib ex Pe a k-M _ Re v 0 _9
R
0 .1u _ 1 6V_ Y 5V_ 0 4 0.1 u _ 16 V_ Y5 V_ 0 4 1 u _6 .3 V _ X5 R _0 4
Schematic Diagrams
IBEXPEAK - M 9/9
U20I
IBEXPEAK - M (GND) AY7

B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260]
H49
H5
J24
B19
B23
VSS[161]
VSS[162]
VSS[261]
VSS[262]
K11
K43
B31 VSS[163] VSS[263] K47
B35 VSS[164] VSS[264] K7
B39 VSS[165] VSS[265] L14
B43 VSS[166] VSS[266] L18
B47 VSS[167] VSS[267] L2
B7 VSS[168] VSS[268] L22
BG12 VSS[169] VSS[269] L32
U20H
AB16 BB12 VSS[170] VSS[270] L36
VSS[0] BB16 VSS[171] VSS[271] L40
AA19 AK30 BB20 VSS[172] VSS[272] L52
AA20 VSS[1] VSS[80] AK31 BB24 VSS[173] VSS[273] M12
AM1 9 VSS[3] VSS[82] AK34 BB34 VSS[175] VSS[275] M20
AA24 VSS[4] VSS[83] AK35 BB38 VSS[176] VSS[276] N38
AA31 VSS[8] VSS[87] AK49 BC10 VSS[180] VSS[280] M46
AA32 VSS[9] VSS[88] AK5 BC14 VSS[181] VSS[281] M49
AB11 VSS[10] VSS[89] AK8 BC18 VSS[182] VSS[282] M5
AB15 VSS[11] VSS[90] AL 2 BC2 VSS[183] VSS[283] M8
B
AB23 VSS[12] VSS[91] AL 52 BC22 VSS[184] VSS[284] N24
AB30 VSS[13] VSS[92] AM1 1 BC32 VSS[185] VSS[285] P11
VSS[14] VSS[93] VSS[186] VSS[286]
AB31 BB44 BC36 AD15
.
VSS[15] VSS[94] VSS[187] VSS[287]
AB32 AD 24 BC40 P22
S
AB39 VSS[16] VSS[95] AM2 0 BC44 VSS[188] VSS[288] P30
AB43 VSS[17] VSS[96] AM2 2 BC52 VSS[189] VSS[289] P32 c
AB47 VSS[18] VSS[97] AM2 4 BH9 VSS[190] VSS[290] P34
AB5
AB8
VSS[19]
VSS[20]
VSS[21]
VSS[98]
VSS[99]
VSS[100]
AM2 6
AM2 8
BD48
BD49
VSS[191]
VSS[192]
VSS[193]
VSS[291]
VSS[292]
VSS[293]
P42
P45
Sheet 22 of 42 h
AC 2 BA42 BD5 P47
IBEXPEAK - M 9/9
AC 52 VSS[22] VSS[101] AM3 0 BE12 VSS[194] VSS[294] R2
e
AD 11 VSS[23] VSS[102] AM3 1 BE16 VSS[195] VSS[295] R52 m
AD 12 VSS[24] VSS[103] AM3 2 BE20 VSS[196] VSS[296] T12
AD 23 VSS[26] VSS[105] AM3 5 BE30 VSS[198] VSS[298] T46 a
AD 31 VSS[28] VSS[107] AM3 9 BE38 VSS[200] VSS[300] T5 t
VSS[30] VSS[109] VSS[202] VSS[302]
AD 34 AU 20 BE46 U30
i
VSS[31] VSS[110] VSS[203] VSS[303]
AU 22 AM4 6 BE48 U31
c
AD 42 VSS[32] VSS[111] AV22 BE50 VSS[204] VSS[304] U32
AD 46 VSS[33] VSS[112] AM4 9 BE6 VSS[205] VSS[305] U34
AD 49 VSS[34] VSS[113] AM7 BE8 VSS[206] VSS[306] P38
D
AD 7 VSS[35] VSS[114] AA50 BF3 VSS[207] VSS[307] V11
AE2 VSS[36] VSS[115] BB10 B F49 VSS[208] VSS[308] P16 i
AE4 VSS[37] VSS[116] AN 32 B F51 VSS[209] VSS[309] V19 a
AF 12 VSS[38] VSS[117] AN 50 BG18 VSS[210] VSS[310] V20
Y13 VSS[39] VSS[118] AN 52 BG24 VSS[211] VSS[311] V22
AH 49 VSSS
S [[ 4
410 ]] VSS[119] AP12 BG4 VSSS
S [[ 2
2113
2 ]] VSSS
S [[ 3
3113
2 ]] V30
AU 4 V VSS[120] AP42 BG50 V V V31
g
VSS[42] VSS[121] VSS[214] VSS[314]
AF 35 AP46 BH11 V32
r
AP13 VSS[43] VSS[122] AP49 BH15 VSS[215] VSS[315] V34 a
AN 34 VSS[44] VSS[123] AP5 BH19 VSS[216] VSS[316] V35
AF 45 VSS[45] VSS[124] AP8 BH23 VSS[217] VSS[317] V38 m
AF 46 VSS[46] VSS[125] AR 2 BH31 VSS[218] VSS[318] V43
AF 49 VSS[47] VSS[126] AR 52 BH35 VSS[219] VSS[319] V45
AF 5 VSS[48] VSS[127] AT11 BH39 VSS[220] VSS[320] V46 s
AF 8 VSS[49] VSS[128] BA12 BH43 VSS[221] VSS[321] V47
AG 2 VSS[50] VSS[129] AH 48 BH47 VSS[222] VSS[322] V49
AG 52 VSS[51] VSS[130] AT32 BH7 VSS[223] VSS[323] V5
AH 11 VSS[52] VSS[131] AT36 C12 VSS[224] VSS[324] V7
AH 15 VSS[53] VSS[132] AT41 C50 VSS[225] VSS[325] V8
AH 16 VSS[54] VSS[133] AT47 D51 VSS[226] VSS[326] W2
AH 24 VSS[55] VSS[134] AT7 E12 VSS[227] VSS[327] W5 2
AH 32 VSS[56] VSS[135] AV12 E16 VSS[228] VSS[328] Y1 1
AV18 VSS[57] VSS[136] AV16 E20 VSS[229] VSS[329] Y1 2
AJ 19 VSS[61] VSS[140] AV34 E38 VSS[233] VSS[333] Y2 8
AJ 28 VSS[67] VSS[146] AV8 F49 VSS[239] VSS[339] Y4 6
AJ 32 VSS[68] VSS[147] AW 14 F5 VSS[240] VSS[340] P49
AJ 34 VSS[69] VSS[148] AW 18 G10 VSS[241] VSS[341] Y5
AT5 VSS[70] VSS[149] AW 2 G14 VSS[242] VSS[342] Y6
AJ 4 VSS[71] VSS[150] BF9 G18 VSS[243] VSS[343] Y8
AK12 VSS[72] VSS[151] AW 32 G2 VSS[244] VSS[344] P24
AM4 1 VSS[73] VSS[152] AW 36 G22 VSS[245] VSS[345] T43
AN 19 VSS[74] VSS[153] AW 40 G32 VSS[246] VSS[346] AD51
AK26 VSS[75] VSS[154] AW 52 G36 VSS[247] VSS[347] AT8
AK22 VSS[76] VSS[155] AY 11 G40 VSS[248] VSS[348] AD47
AK23 VSS[77] VSS[156] AY 43 G44 VSS[249] VSS[349] Y4 7
AK28 VSS[78] VSS[157] AY 47 G52 VSS[250] VSS[350] AT12
VSS[79] VSS[158] AF3 9 VSS[251] VSS[351] AM6
I b e xP e a k- M _ R e v0 _ 9 H16 VSS[252] VSS[352] AT13
H20 VSS[253] VSS[353] AM5
H30 VSS[254] VSS[354] AK45
H34 VSS[255] VSS[355] AK39
H38 VSS[256] VSS[356] AV14
H42 VSS[257] VSS[366]
VSS[258]
I b e xP e a k- M _ R e v 0 _ 9
Schematic Diagrams
New Card, Mini PCIE

3 .3 V
8/18/2019 NEW CARD(Port 8) clevo+6-71-w24h0-d02a.unlocked.pdf

BUF _ PL T _R ST # 1
5
C 4 59
U2 6
* 0 .1u _1 6V _ Y 5 V _0 4 3 .3 V
4 *M C7 4V HC1 G 08 D F T1 G
2 R 3 36 R 33 8 C2 1 0 C 2 24 C2 2 0
* 1 00 K_ 1 %_ 0 4 * 10 0 K_ 1% _ 0 4 *0 .1 u_ 1 0 V_X7 R_ 0 4 * 0 .1u _ 1 0V_ X7 R_ 0 4 *0 .1 u_ 1 0 V_X7 R_ 0 4

3
1 .5 VS 3.3 VS 3 .3 V
U 25 J _ NEW 1
17 8 N C_ RST # N C_ PERST # 13
AU XIN PER ST # P E R S T#
15 N C_ 3 .3VA UX 36mils 12
AUXO U T + 3.3 VAU X
2
3 .3 VIN 3 .3 VOU T
3 N C_ 3 .3V 48mils 14
15 + 3.3 V
+ 3.3 V
1 .5 VOU T
11 N C_ 1 .5V 48mils 10
+ 1.5 V
9
12 + 1.5 V
1 .5 VIN 10 NC _C PPE# 17
CPP E# 9 NC _C PUSB# 4 CPP E#
s
CPUS B# P C IE _ W A K E # 11 CPU SB#
6 1 6 ,25 P C IE _ W A K E # 16 W AKE#
4 ,1 8 ,25 ,2 8 BUF _ PL T _R ST # 19 SY SRST # 1 5 NEW CAR D_ CL KRE Q # CL KR EQ#
1 8 U SB_ OC# 2 3 3 .3 VS R 1 70 1 0 K _0 4
OC # 19
m 1 1 5 CL K_ PCIE _N EW _ CAR D 18 REF CL K+

1 6 ,2 8,3 1 SUS B# ST BY# 1 5 CL K_ PCIE_ N EW _ CAR D# REF CL K-
a
R 34 7 1 0 K _0 4
3.3 V
r
4 18 N C_ RC L KEN R 33 9 * 10 K _ 0 4 22
5 NC R CL KEN 20 N C_ SHD N# R 35 5 * 10 K _ 0 4 3 .3V 15 P CIE_ RXP2 _ NEW _ CA RD 21 PET p 0
Sheet 23 of 42 13 NC SH DN # 15 P CIE_ RXN2 _ NEW _C ARD 25 PET n 0 5
g 14 NC 7 15 PCIE_ T XP2_ N EW _ CAR D 24 PER p0 R ESER VED 6

3 .3 VS 3 .3V 16 NC G ND 21 15 PCIE_ T XN2 _ NEW _ CAR D PER n0 R ESER VED
1 .5 VS
a
NC G ND 3
New Card, Mini PCIE Port 3

i
1 8 U SB_ PP3 2 USB _D +
* W 8 3L 3 5 1Y G
1 8 U SB_ PN3 USB _D - 1
GN D 20
6- 02-83351-9Q0
D
C4 4 3 C4 6 4 C 45 1
GN D 2 3
8 GN D 26
*0 .1 u _1 6 V_ Y5 V _ 04 *0 .1 u_ 1 6 V_ Y5 V _ 04 *0 .1 u _1 6 V_ Y5 V_ 0 4
1 5 SM L0 _ DAT A 7 SMB _D AT A GN D G ND 1
ENE P2231 pin3,4,15,22
c
1 5 SM L0 _ CL K SMB _C LK G ND1 G ND 2
i
has internally G ND2
t
* 13 0 8 01 -0 2
pul led hig h (170K ohm)
a
m
e
h
c MINI CARD (WLAN,Port 5)
S
Layout Show "WLAN(Wimax, 802.11N)" Note
20 mil
.
3 .3 V
J _ MIN I1 W LAN 1 .5V 1.5 V
B
P C IE _ W A K E # 1 2
W AKE# 3 .3VA UX_0
3 6 20 mil R3 2 5 * 1 5 mil _ s h o rt _ 06
R 31 2 1 0K _0 4 5 CO EX1 1 .5 V_0 8
3 .3V S CO EX2 UIM _ PW R 10 PC H_ BT _ EN#
R 39 7 0_ 0 4 C4 3 8
7 U IM_ DAT A 12
1 5 W L AN _C L KREQ # 11 CL KR EQ # U IM_ CL K 14
1 5 C L K_PC IE_ MIN I# *0 .1 u _1 6 V_ Y5 V _ 04
13 REF CL K- U IM _ R E S E T 16
1 5 C L K_P CIE_ MIN I 9 REF CL K+ U IM _ V P P
15 GN D0 4
GN D1 G ND5
KEY
21 18
27 GN D2 G ND6 26
29 GN D3 G ND7 34 R 32 6
GN D4 G ND8 40 3. 3VS
* 10 K_ 0 4
35 G ND9 50
28 W L AN_ DE T# 23 GN D1 1 G ND 10
15 PC IE_ RXN3 _ W L AN 25 PET n 0 20
15 PCIE _R XP 3_ WL AN 31 PET p 0 W _ DISA BLE# 22 W L AN _EN 2 8,29
BU F _P LT _ RST #
15 PCIE _T XN3 _ W L AN 33 PER n0 P E R S E T# 30
15 PCIE_ T XP 3_ W L AN PER p0 SMB_ CL K 3 2
17 SMB_ DAT A 3 6 BT _ DET # 2 8,2 9
28 3 IN1
R 36 2 * 0 _ 0 4
28 8 0 DET # 19
37
Re s e rv e d0
Re s e rv e d1
U SB_ D- 3 8
USB_ D+
20 mil
U SB_P N2 1 8
U SB_P P2 1 8 Port 2
39 GN D1 2 24
3.3 V 3 .3 V A U X _ 1 R 32 9 * 15 m il _ s ho rt_ 0 6
R 35 9 0 _ 04 41 3 .3V AUX_ 3 3 .3VA UX_1 2 8 3 .3 V
2 8 ,29 BT_ EN 43 3 .3V AUX_ 4 1 .5 V_1 48
GN D1 3 1 .5 V_2 5 2
40 mil W LA N1 .5 V
M INI_ CL K1 45
M INI_ DAT A1 47 Re s e rv e d2 3 .3VA UX_2 42 3 .3V
M INI_ RST # 1 49 Re s e rv e d3 LE D_ W W AN# 4 4 20 mil
51 Re s e rv e d4 L ED_ W L AN# 46 W L AN_ L ED# 2 8 ,29
R 31 5 * 0_ 0 4
VD D3 Re s e rv e d5 LE D_ W PAN# 8 0 C LK 28
8 8 91 0 -5 20 4 M-0 1
R 39 6 0 _ 04
15 ,2 9 PCH _BT _ EN#
4 ,9,1 0 ,1 1,2 1 , 2 7,2 9 ,3 1, 33 ,3 6 1.5 V

2 0, 31 ,3 6 1.5 VS
3 ,4 ,12 ,1 4 ,15 , 1 6 ,18 ,1 9 ,20 ,2 1 ,2 4,2 5 , 2 9,3 0 ,3 1,3 3 ,3 4,3 5 3 .3 V
2,1 0 ,1 1,1 2 ,1 3, 14 ,1 5 , 16 ,1 7 ,18 ,1 9 ,20 ,2 1 ,24 ,2 5 , 2 6,2 7 ,2 8,2 9 ,3 0,3 1 ,3 5, 3 6 3 .3 V S
1 4 ,2 5,2 8 ,2 9,3 1 ,3 2,3 7 VD D3
B - 24 New Card, Mini PCIE
Schematic Diagrams
3G, CCD, TPM

MINI CARD 3G(Port 6) 3G POWER
G5243A 6- 02- 05243- 9C0
Layout Show " 3.5G(H
SDPA)" Note
3 G_ 3.3 V 3 .3V
APL3512A 6-02- 03512-9C0 3 G_ 3 .3V
3A 120mils U 12 3A 120mils
J _ 3G 1 5 1
6 0 m ils
1 2 VIN VO U T
3 W AKE# 3.3 VAU X_ 0 6 2
5 CO EX1 1. 5V_ 0 8 U IM_ PW R G ND
CO EX2 UIM_ PW R 10 U IM_ DAT A 4 3
C1 90 R 1 76 * 1 5m il _ s ho rt_ 0 6 R1 7 3 C2 3 1
7 UIM _D AT A 12 U IM_ CL K C1 93 + C2 34 C2 4 1 SS EN
11 CL KR EQ # UIM _ CL K 14 U IM _ R S T A P L3 5 12 A *1 0 0K _1 % _0 4 0 .1u _ 1 6V_ Y 5V_ 0 4
13 REF CL K- UIM _R ESET 16 U IM _ V P P 0.1 u _ 16 V_ Y5 V_ 04 0.1 u _1 6 V_ Y5 V_ 04 22 0 u_ 4 V_ V_B 1 0u _ 6.3 V_ X 5R _0 6 C2 30
9 REF CL K+ U IM _ V P P
15 GN D0 4 *0 .01 u _ 50 V_ X7 R _0 4
GN D1 GN D5
KEY
21 GN D2 GN D6 18
27 26
29 GN D3 GN D7 34 2 8 3 G _PO W ER
GN D4 GN D8 40
35 GN D9 50
28 3 G_ D ET# GN D1 1 GN D1 0 From SB GPIO Pin default HI
23
25 PET n 0 20 Po we r P la n e : Su sp en d
31 PET p 0 W _ DISABL E# 22 3 G _E N 28
L19
33 PER n0 PERSET # 30 S3: Defined
*W C M2 0 12 F 2 S-1 61 T 0 3-s h o rt
PER p0 SM B_ CL K 32 3 4
SM B_D AT A USB_ PN9 1 8 B
3 G_ 3 .3V 17 36
19 Re s e rv ed 0 US B_D - 38 2 1
Re s e rv ed 1 U SB_ D+ U S B _P P 9 1 8
37 .
39 GN D1 2 24
Sheet 24 of 42
R 1 60 * 1 5 mi l _ sh o rt _ 06 S
41 3 .3V AUX_3 3.3 VAU X_ 1 2 8 3 G_ 3 .3V
C2 13 C4 14 43
45
3 .3V AUX_4
GN D1 3
Re s e rv ed 2
1. 5V_ 1 48
1. 5V_ 2 5 2
3.3 VAU X_ 2
6 0 m ils
3 G_ 3 .3 V
SIM CONN c
0.1 u _ 16 V_ Y5 V_ 04 10 u _6 .3 V_ X5 R _0 6 47
49
51
Re s e rv ed 3
Re s e rv ed 4
L ED _W W AN#
L ED_ W L AN#
42
44
46 C4 1 5
R 14 0 4 .7 K _ 0 4 3G, CCD, TPM h
Re s e rv ed 5 L ED _W P AN# +C 19 8 e
8 8 91 0 -5 20 4 M-0 1 *0 .1 u _1 6 V_Y 5 V_0 4
2 2 0u _ 4 V_V_ B J_ SIM 1 m
R 32 2 LOCK R 31 0
* 10 m il _ s ho rt_ 0 4 (TOP VIEW) * 10 m il _ s ho rt_ 0 4
U IM_ CL K C3 C7 U IM_ DAT A
a
U IM _ R S T C2 U IM_ CL K U IM_ DAT A C6 U IM_ VPP
U IM_ PW R C1 U IM _ R S T U IM _ V P P C5
U IM_ PW R U IM_ GN D
t
C 42 4
i
C 4 04 C 40 3 C4 0 5
2 2 p_ 5 0 V_N PO_ 0 4 OPEN
c
C1 77 0 6 61 -1 2 2 p _5 0 V_N PO_ 0 4 2 2 p _5 0 V_N PO_ 0 4 22 p _ 50V_ NP O _0 4
SIML OC K D
i
a
3 .3 VS
TPM 1.2
Asserted before enteringS3 4
4
4
g
0
_ 0 0 r
V _ _
CCD
5 V V
LPC reset timing: 5 5
Y
_ Y Y
_
a
_
LPCPD# inactive to LRST# in active 3 2~96us [PVT-1] V
6
1
V
6
V
6
m
_ 1 1
u _ _
u
U14 u 5V Q4 5 V_ CC D
1
. 1
. 1
.
26 10 0
0 0 C 27 2 MT P3 4 03 N3
1 4,2 8 L PC_ AD 0 23 L AD0 V DD1 19
* * *
S D 48 mil s
L1 * 15 m il _ s ho rt_ 0 6
1 4,2 8 L PC_ AD 1 20 L AD1 V DD2 24 7 6 0 *1 u _ 6.3 V_ X5R _0 4
1 4,2 8 L PC_ AD 2 7
2 5 8
17 L AD2 V DD3 2 2
1 4,2 8 L PC_ AD 3 L AD3 C C C MJ_CCD1
C3 C2 R9 C5 C8 C9
21 G
TPM 1
18 PC LK _T PM L CL K 3 .3 VS 1 u _6 .3 V_ X5 R_ 0 4 1 00 K_ 1 %_ 0 4 1 u _6 .3 V_X5 R_ 0 4 0 .1u _ 1 6V_ Y 5V_ 0 4 1 u_ 6 .3 V_X5 R_ 0 4
22 5 0 .1 u _1 6 V_ Y5 V _0 4
1 4 ,28 L PC_ F R AME# 16 L F RAM E# VSB R8 5
18 PL T _R ST # 27 L RESE T#
1 4 ,28 S E R IR Q C 25 5
15 S E R IR Q 1 00 K_ 1% _ 0 4
16 PM _C L KRUN # C LKR UN #
* 0.1 u _1 6 V_ Y5 V_ 04 J _C CD1
R 19 9 * 0_ 0 4 T PM_ L PCPD # 28 6 T PM 30 0 4 R7 3 3 0K _ 0 4
1 6 S4 _ ST ATE# L PCPD # G P IO 2 T PM 30 0 5 1
9 G P IO 2 D 18 USB_ PN5 2
T PM_ BAD D 18 USB _PP5
T E S T B I/B A D D 13 XTALI Q5 CCD _D ET # 3
TPM _ PP 7 XTAL I CCD _ EN G 2 8 C CD _D ET # 4
28 CC D_ EN MT N7 0 02 Z H S3
PP X4 5
14 XTALO 4 1 S
* MC - 14 6 _ 32.7 68 KH z 8 52 0 5-0 5 0 01
HI: A CCESS TPM 30 0 1 1 XT AL O 3 2
6- 22-32R76- 0B4 From H8 default HI
TPM 30 0 2 3 N C_ 1 4
TPM_PP C2 4 4 C 2 50
LOW: NORMAL( Internal PD) TPM 30 0 3 12 N C_ 2 G ND _1 11
N C_ 3 G ND _2 18 *1 8p _ 5 0V_ NPO _ 04 * 1 8p _ 50 V_ NPO _ 04
HI: 4E/ 4FH
8 G ND _3 25
TPM _BADD LOW: 2E/ 2F H T EST I G ND _4
* SL B96 3 5 TT
3 ,4 ,12 ,1 4 ,15 ,1 6 , 18 ,1 9,2 0 ,2 1,2 3 ,2 5,2 9 ,3 0,3 1 , 3 3,3 4 ,35 3 .3 V
XTAL O
PC LK_ T PM 2 ,1 0,1 1 ,12 ,1 3 ,14 ,1 5 , 16 ,1 7 ,18 ,1 9 ,20 ,2 1,2 3 ,2 5,2 6 ,2 7,2 8 , 2 9,3 0 ,3 1,3 5 ,36 3 .3 V S
R 18 6 * 33 _0 4 C 266 * 10p _50 V_ NPO _06 2 1,3 0 ,3 1,3 3 ,34 5 V
XTAL I Co-l ayout X4, X9
3 .3V S 1 4 X9
T PM _L PC PD# R 20 0 * 10 K _0 4 2 3
*1 T J S12 5 DJ 4 A4 20 P_ 32 .7 6 8KH z
T PM _PP R 19 0 * 10 K _0 4
6-22- 32R76-0B2
T PM _BAD D R 18 8 * 1 0 K _ 1% _ 0 4 6-22- 32R76-0BG
R 18 5 * 1 0 K _ 1% _ 0 4
3G, CCD, TPM B - 25
Schematic Diagrams
Card Reader/LAN JMB251C

http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf SD _C L K
75/96
JMC251C
3 .3 V_ L AN
S w i t c h i n g R e g u l a t or
C2 7 0 near Pi n#
41
close to PIN33
*1 0 p _5 0 V_ NPO _ 06 D V DD R 31 7 * 4 . 7K _0 4
3 .3 VS SD_ CL K R 18 7 2 2 _ 1 %_ 0 4 L3 5 U2 1
(>20mil)
R 31 4 * 4 . 7K _0 4 SD _ CD #
R EGL X . D V DD (>20mil)
L AN _SC L R 31 8 * 4 . 7K _0 4 8
VC C WP
7
6
SD XC_ POW ER SW F 2 5 20 C F -4 R7 M-M C4 5 0 C 45 7
V C C_ C A RD L AN _SD A 5 SC L 1
R
C2 7 1 0 1 E 10 u _ 6. 3V_ X5 R_ 0 6 0 .1 u_ 1 6 V_ Y5 V _ 0 4 SD A A0 2
D D For JMC251/261 only A1
N W 4 3
C276 1 E E A Pi n#
33 Pi n#33
1 L L O
L S 3 2 1 0 X G ND A2
R 31 1 1 0K _0 4 S D_ W P 0 .1u _ 1 6 V_Y 5 V_ 04 2 .2 u _ 6.3 V_ X5 R_ 0 6 O _ _ _ P B D D D D D L V DD 3 3 .3 V
I N _ _ _ _ D G
R 31 3 * 10 K _0 4 M S_ INS# D N N O V
3
C _ D _ V E * AT 24 C 02 BN
A A S . X D D D D
M L L I 3 S S
S S S D R V DD3 3 .3 V
D
Card Reader Pull High/Low S
R 3 48 R 3 58
Resistors 4
7 5 4 3 2 1 0 8 6 4 3
8 4 4
6 4 4 4 4 4 4 3
9 3 3
7 3 3
5 3 3 * 1 5m il _s h o rt_ 06 * 0 _0 6
U 13 U27
1 0
1 N D 5 4 3 2 1 0 2 D
R 1 77 R 3 54 DV DD 5 1 3.3 VS VD D3
1
D D
O O
I O O O X
1 N L
O UT IN
O O N I O I O I O
I L
E L
E
S
I G D D
D I D D
D D I D D
I F
B
G * 1 5m il_s h o rt _ 06 * 0_ 0 6 R 2 01 C 4 69
D _ _ D V
V M M M M M M 3
M N N (>20mil) S HD N#
M DIO 1 0 49 A A 32 * 2 K_ 1% _ 0 4 4 M PD R3 20 1 00 K _1 %_ 04
L L 0
_
M DIO 9 5 0 MD IO1 0 V DD RE G 3 1 4 2
(>20mil) R
M DIO 8 5 1 MD IO9 VC C3 V 3 0 3 .3 VS SET G ND 5 R32 1 * 4. 7 K _ 04
5 2 MD IO8 P W RC R 2 9 V C C_ CA R D X
R 35 1 * 15 m il_ s ho rt_ 0 6 A VDD 12 _ 5 2 R 1 98 *G 91 4 1 _
DV D D 5 3 VDD T EST 2 8 MPD V
2 6 L AN_ M DIP0 3
.
5 4 VIP_ 1 MP D 2 7 * 1 0K _1 % _ 04 6 C2 3 9 0 . 1u _1 6V _ Y 5V _ 04
s
2 6 L AN_ M DIN 0 _
R 35 0 * 15 m il_ s ho rt_ 0 6 A VDD 12 _ 5 5 5 5 VIN _1 W AKE N 2 6 LA N_ SCL L AN_ PC IE_ W AKE# 2 8 u
DV D D 1
5 6 AVD D1 2 LA N_ L ED2 25 LA N_ SDA G9141
26 L AN_ M DIP1 5 7 VIP_ 2
JMC251 C CR _ LE D 2 4
APL5603- 12B(no R201,R198)
m
26 L AN_ M DIN 1 5 8 VIN _2 R ST N 2 3 BUF _PL T _ RST # 4 ,1 8,2 3 ,2 8
5 9 GN D CP P E N 2 2
a Sheet 25 of 42 3 .3 V_ LAN

2 6 L AN_ M DIP2
L AN _ MD IP2 6 0 AVD D3 3
L AN _ MD IN2 6 1 VIP_ 3 (LQFP 64)
GN D 21
V DDI O 2 0 SD_ W P
3 .3 V_L AN
(>20mil)
V D D3
(>20mil)
3.3 VS
r
2 6 L AN_ M DIN 2 A VDD 12 _ 6 2 6 2 VIN _3 MD IO6 1 9 M DIO 12
DV D D R 34 9 * 15 m il_ s ho rt_ 0 6
Card Reader/LAN L AN _ MD IP3 6 3 AVD D1 2 MD IO1 2 1 8 MD IO1 4
g
26 L AN_ M DIP3 VIP_ 4 MD IO1 4 1 7
L AN _ MD IN3 6 4 S D_ C D# C4 5 3 C 2 33 C 42 5 C2 3 7
26 L AN_ M DIN 3 VIN _4 N C R_ CD 0 N
1
a
3
3 2 2
1 3
JMB251C 1 1 7 D 1 0u _ 6 .3 V_X5 R_ 0 6 0 .1 u _1 6 V_ Y5 V _ 0 4 1 0 u _6 .3 V_ X5R _ 06 0. 1u _ 1 6V _Y 5 V_0 4
i
T D T D D C
D N P N D N P D O
I O
I _ Pi n#3
2 Pi n#
32 Pin#31 Pin#31
X U K K D P 3 .3V _L AN 3.3 V
E V I
N O L L V X
X N X X V D D R
R A X X C C A R
R G
T T A M M C
D J MC 25 1 _ C
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6
6
1 1 1 1 1 1 1
PCIe Differential
Pairs = 100 Ohm V DD 3
R 35 7 * 0_ 0 6
c
0 3
t_ 1
i
T 7 r _
_ # ISON 3. 3V_ L AN
U
N O 2 o 2 R 3 44 1 0 K _1 %_ 04
1 3 7 S 28 ISON
t
I 1 h
X X s 1 N
D O
D l_ O I_
N N D i D I I
D S R 1 92 * 1 0 0K _ 1% _0 4
a
A A V m V D
R 20 2 L L A 5 A M M M R31 9 1 0K _ 0 4
1
*
1 2 K_ 1% _ 0 4 D1 9
A C
m
PC IE_ W AKE# LA N _ PCIE _W A KE#
7 8 6
2
1 6, 2 3 PC IE_ W AKE# LA N_ P CI E _W A K E # 2 8
3
3 3 0
AVDD 1 2_ 7 AVD D1 2 _ 13
e
R t_
R r
o
SCD 3 4 0
3 .3 V_ LAN h
D D s
_
D D i
l
C 44 9 C4 4 4
h
V
D V 5
D m
4 IN 1 SOCKET SD/MMC/MS/MS Pro
c
1
*
0 .1 u_ 1 6 V_ Y5 V_ 0 4 0.1 u _ 16 V_ Y 5V _0 4 C 2 35 0 . 1u _ 1 0V _ X 7R_ 04
PC IE_ RXP4 _ GL AN 15
S
Pi n#7 Pin#13 C 2 36 0 . 1u _ 1 0V _ X 7R_ 04
P CIE_ R XN 4 _G L AN 1 5
.
J _C ARD -RE V1
SD _C D# P1
SD _D 2 P2 CD_ S D
B
AVDD 1 2_ 5 2 AVD D1 2 _ 55 AVDD 1 2_ 6 2 A VDD 12 _7 SD _D 3 P3 DAT 2 _S D
P CIE_ T XN4 _GL AN 15 Card Reader SD _BS P4 CD/ DAT 3 _S D
PC IE_ TXP4 _GL AN 1 5 P5 CMD _ SD
C L K_ PCIE_ G LA N 1 5 Power P6 VSS_SD
C 28 6 C2 8 7 C 28 9 C4 4 7 C LK_ PC IE_ GL AN # 15 VC C_ CA RD V C C_ C A RD SD _C L K P7 VDD _S D
C4 2 0 P8 CL K_ SD
SD _D 0 P9 VSS_SD
0 .1 u_ 1 6 V_ Y5 V_ 0 4 0.1 u _ 16 V_ Y 5V _0 4 0 .1 u_ 1 6 V_ Y5 V_ 0 4 *1 0 u _6 .3 V_ X5 R_ 0 6
Pi n#52 Pin#55 Pi n#62 Pi n#7 0 .1u _ 1 6V _Y 5 V_ 04 SD _D 1 P10 DAT 0 _S D
SD _W P P11 DAT 1 _S D
Reserved
L A NX O UT R 31 6 P12 W P_ SD
P13 VSS_ MS
For JMC251 C 7 5 _1 % _ 0 4
V C C_ C A RD SD _C L K P14 VCC _M S
3 .3 V_L AN P15 SCL K_ MS
R 18 4 * 1M _0 4 LAN XIN C4 1 3 SD _D 3
MS _IN S# P16 DAT 3 _M S
3 .3 V_ LA N P17 INS_ MS
X5 0 .1u _ 1 6V _Y 5 V_ 04 SD _D 2
2 1 SD _D 0 P18 DAT 2 _M S
C 28 8 C4 6 3 C 26 8 C 42 2 SD _D 1 P19 SDIO /DA T 0 _ MS
SD _BS P20 DAT 1 _M S P2 2
F SX5L _ 2 5 MH z
0 .1 u_ 1 6 V_ Y5 V_ 0 4 *0 .1 u_ 1 6 V_ Y5 V_ 0 4 C2 4 8 0 .1 u _ 16 V_ Y5 V_ 0 4 1 0u _ 6 .3 V_X5 R_ 0 6 P21 BS_ MS GN D P2 3
C2 6 1 VSS_ MS GN D
Pi n#43 Pin#43
2 2p _ 5 0 V_N PO _0 4 Pin#2 Pi n#
2 MD R0 1 9 -C0 -1 04 2
22 p _ 5 0V_ N PO_ 0 4
3 .3 V_L AN
6-22-25R00-1B4
6-22-25R00-1B5 VC C_ CAR D V CC _C ARD
C 28 5 C4 6 0 C 46 1 C2 4 0
*1 0 u _ 6.3 V_ X5 R_ 0 6 0.1 u _ 16 V_ Y 5V _0 4 0 .1 u_ 1 6 V_ Y5 V_ 0 4 0 .1 u_ 1 6 V_ Y5 V_ 0 4
Pi n#59 Pin#59 Pi n#2 Pi n#21 C4 2 3 C4 1 0 C 2 38 C4 1 9
Reserv ed
0 .1u _ 1 6V _Y 5 V_ 04 4. 7u _ 6 .3V _X5 R_ 0 6 0 .1 u _1 6 V_ Y5 V_ 0 4 0 .1u _ 1 6V _Y 5 V_ 04
Place allcapacitors closedto chip.

Near Cardreader CONN
The subscriptin each CAP incicates the pin
numberofJMC251/JMC261that s hould be 1 4,2 3 ,2 8 ,29 ,3 1 ,3 2, 37 V D D3
26 D VD D
closedto. 2, 10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 6 ,1 7,1 8 ,1 9 ,20 ,2 1 ,2 3, 24 ,2 6 ,2 7,2 8 ,2 9 ,30 ,3 1 ,3 5,3 6 3 .3 VS
3,4 ,1 2 ,1 4,1 5 ,1 6 ,18 ,1 9 ,2 0, 21 ,2 3 ,2 4,2 9 ,3 0 ,31 ,3 3 , 3 4,3 5 3 .3 V
B - 26 Card Reader/LAN JMB251C
Schematic Diagrams
LAN (JMC251C), SATA HDD, ODD

GIGA LAN (JMC251C)
8/18/2019
L2 6 LP 2
* SB 0 40 2 TL -0 4 0- sh o rt
clevo+6-71-w24h0-d02a.unlocked.pdf J _ RJ 1
L AN_ MD IP0 12 13 L MX1 + 1 8 D LM X1 + 1 G ND1
25 L AN_ M DIP0 11 T D4+ M X4+ 14 2 7 2 DA + sh iel d G ND2
L AN_ MD IN0 L MX1 - D LM X1 -
25 L AN_ M DIN 0 L AN_ MD IP1 9 T D4 - M X4- 16 L MX2 + 3 6 D LM X2 + 3 DA - sh iel d
25 L AN_ M DIP1 8 T D3+ M X3+ 17 4 5 6 DB +
L AN_ MD IN1 L MX2 - D LM X2 -
25 L AN_ M DIN 1 T D3 - M X3 - DB - GN D
L AN_ MD IP2 6 19 L MX3 + R 36 7 0 _ 04 D LM X3 + 4

25 L AN_ M DIP2 5 T D2+ MX2 + 2 0 5 DC +
L AN_ MD IN2 L MX3 - R 36 8 0 _ 04 D LM X3 -
25 L AN_ M DIN 2 L AN_ MD IP3 3 T D2 - M X2- 22 L MX4 + R 36 9 0 _ 04 D LM X4 + 7 DC -
25 L AN_ M DIP3 L AN_ MD IN3 2 T D1+ MX1 + 2 3 L MX 4 - D LM X4 - 8 DD +
T D1 - MX1 - R 37 0 0 _ 04
25 L AN_ M DIN 3 DD -
DVD D 10 15 PJ S-0 8 SO1 B
7 T CT 4 MC T4 1 8
4 T CT 3 MC T3 21 D LM X3 + R 36 5 D LM X3-
1 T CT 2
T CT 1
MC
MC
T2 2 4
T1
D LM X4 + R 36 6
* 0_ 0 4
* 0_ 0 4 D LM X4- E4120 PJ S-08SL3B
R 28
P10 1 2
E5120Q PJ S-08S01B
* 0_ 0 4
GST5009 L F N MC T_ 1 R 24 7 5 _1 % _ 04 N MCT _ R R 36 3 * 57 _ 1 % _0 4 D LM X3- 6- 21-B4010-008
40mil N MC T_ 2 R 25 7 5 _1 %_ 04 R 36 4 * 75 _ 1 % _0 4 D LM X4-
N MC T_ 3 R 26 7 5 _1 % _ 04
4 4 4 4 N MC T_ 4
B
0
_ 0 0 0 L6 2 R 32 7 5 _1 % _ 04
_ _ _
R R R R .
7 7 7 7 L AN_ MD IN0 7 10 L MX1 - C3 2 2
Sheet 26 of 42
X X X X 8 T D+ T X+ 9
S
_ _ _ _ L AN_ MD IP0 L MX1 +
V
0 V
0 V
0 V T D- T X-
0 1 00 0 p _2KV _ X7R _ 12
5 5 5 5 4 12
_ _ _ _
u
1 u
1 u
1 u
1 5 NC NC 13
c
0
.
0
0
.
0
0
.
0
0
.
0
L AN_ MD IN1
L AN_ MD IP1
1
2
NC
R D+
NC
RX+
16
15
L MX2 -
L MX2 +
LAN (JMC251C), h
SATA HDD, ODD
R D- RX -
e
1 8 6 4 3 14 NM CT _ 2
3 2
2 2 R D_ CT RX_C T NOTICE:
6 11 NM CT _ 1
C C C C
T D_ C T T X_C T
m
*P3 0 12
FORJ MB251C GI GA LAN PARTS FORJ MB261C 10M/ 100M LAN PARTS a
L26,LP1 L62,L P2
t
L26, L62 CO- LAYOUT C31,C28,C26,C24,C322 C26,C24
i
c
R24,R25,R26,R32,R367,R368,R369,R370 R24,R25,R363,R364
D
i
a
g
r
a
SATA HDD
m
SATA ODD s
J _ HD D1
S1
S2 S A TA _ T X P 0 C 42 1 0 .0 1 u_5 0 V_ X7 R_ 0 4 J _ OD D1
S3 S ATA_ T XN0 C 41 8 0 .0 1 u _50 V_ X7 R_ 04 SATA TXP0 1 4 S1
S4 SATA TXN0 1 4 S2 SAT A_ T XP 1 C3 8 0 0 .0 1u _5 0 V _X 7 R _ 04 SAT AT XP1 14
S5 S ATA_ R XN 0 C 41 7 0 .0 1 u_5 0 V_ X7 R_ 0 4 S3 SAT A_ T XN 1 C3 7 9 0 .0 1u _5 0 V _X 7 R _ 04
S6 S ATA_ R XP0 S A TA R X N 0 1 4 S4 SAT AT XN1 1 4
C 41 6 0 .0 1 u_5 0 V_ 7X R_ 0 4 S A TA R X P 0 1 4
S7 S5 SAT A_ RXN 1 C3 7 7 0 .0 1u _5 0 V _X 7 R _ 04
S6 SAT A_ RXP1 SAT AR XN1 1 4
3 .3V S C3 7 6 0 .0 1u _5 0 V _X 7 R _ 04 SAT AR XP1 1 4
S7
P1
P2
P3 C 41 2 C4 1 1
P4 P1 5 VS
P5 P2 OD D_ DET EC T# 1 4
*0 .0 1 u_ 5 0 V _ X7 R_ 0 4 *1 0 u _6 .3 V _ X5 R _0 6
P6 P3
P7 5VS P4
P8 P5 C3 6 1 C3 6 3 C 35 8 C 3 68 C3 6 6 C 36 5 C3 6 7
P9 P6 +
P1 0 *0 .1 u _1 6 V_ Y5 V_ 04 0. 1u _ 1 6V_ Y 5V_ 0 4 0 .1 u_ 1 6 V_Y 5 V_0 4 1 u _ 6.3 V_ X5R _ 04 1 0u _ 6. 3V_ X5 R_ 06 1 0 0u _ 6 .3V_ B_ A *0 .1 u _1 6 V_ Y5 V_ 04
P1 1 H DD _N C0 4 4 4 4 8 8
0 0 0 0 0 0 C 1 8 55 3 -1 13 0 5 -L
P1 2 _ _ _ _ _ _ PIN GN D1 ~ 2 = G ND
V V V R
5 R R
P1 3 H DD _N C1 5 5 5 5 5
P1 4 Y
_ Y
_ Y
_ X
_ X X
H DD _N C2 _ _
V V V V V V
P1 5 H DD _N C3 6 6 6 3 3
1 1 1 . . 3
. +C2 0 3
6 6 6
_
u _
u _ _ _ _
u u
1 - 16 2 -1 00 5 6 1 1
. 1
. 1
. 1 u
2 u
0 0 0 2 2
2
P IN G N D1 ~ 2 = G N D *1 00 u _ 6. 3V_ B_ A
5VS 2 ,1 3 ,17,2 0 ,21 ,2 7,30 ,31 ,35,3 6
9 8 6 7 2 1
6-20- 43740- 022 0
4 0
4
0
4
0
4
9
1
9
1 5 VS D VD D 25
C C C C C C 3.3 V 3 ,4 ,1 2,1 4,1 5,1 6 ,1 8,1 9 ,2 0, 21,2 3 ,24 ,2 5,29 ,3 0 ,31 ,3 3 ,34,3 5
1.5 V 4 ,9 ,1 0,1 1 ,2 1,2 3 ,2 7,2 9 ,3 1, 33 ,3 6
3.3 VS 2 ,1 0 ,11 ,1 2 ,13 ,1 4 ,15 ,1 6 ,17 ,1 8 ,1 9,2 0 ,2 1,2 3 ,2 4,2 5 ,2 7,2 8 ,2 9, 30 ,3 1 ,35 ,3 6
C 2 74 C 74 C 4 32
0 .0 1 u_ 5 0 V_X7 R_ 0 4 0 .0 1u _ 5 0V_ X7 R_ 0 4 0 .0 1 u_ 5 0 V_X7 R_ 0 4
LA N (JMC251C), SATA HDD, ODD B - 27
Schematic Diagrams
KBC-ITE IT8502E
R17 1 * 1 5 m i l _ s h or t_ 06 KBC _ AVDD L17
VD D3 H CB 1 0 0 5KF - 12 1 T2 0
C 2 08
0 .1 u _1 6 V_ Y5 V_ 04
C2 32
10 u _ 6.3 V_ X5R _0 6
C2 2 9
0 .1u _ 1 6V_ Y 5V_ 0 4

C2 2 5
0 .1u _ 1 6V_ Y 5V_ 0 4

C 19 5
0 .1 u_ 1 6 V_Y 5 V_0 4
C2 1 8 C2 1 9
.
C2 2 2
VD D3 VDD 3
8
U2 8
5 K B C _ S P I_ S I_ R
VD D3
8/18/2019 0 .1u _ 1 6V_ Y5 V_ 0 4 *0 .1 u _1 6 V_ Y5 V_ 04 *0 .1 u_ 1 6 V_Y 5 V_0 4

clevo+6-71-w24h0-d02a.unlocked.pdf VD D SI
SO 1
CE#
2 K B C _ S P I_ S O _ R
K B C _ S P I_ C E # _ R R 15 8
C 22 6 6 K B C _ S P I_ S C L K _ R
L1 8 K BC_ F L ASH 3 SCK 1 0 0K_ 1 % _0 4
W P#
HC B 10 0 5 KF -12 1 T 20 0 .1 u_ 1 6 V_Y 5 V_0 4 KBC _ AG N D
3 .3 VS . EC_ VCC FOR E4120 FOR E5120Q KBC_ W R ESET #
K BC_ HO LD # 7 4 C 21 6
4 7 H OL D# VSS
1 6 0 2 1 1
2 2 4 J_ KB1 J _ KB2
1 2 5 9 1 1 1 3 7
U1 1 * 85 2 0 1-2 4 0 51 8 52 0 1- 24 0 51 EN2 5 P05 -5 0 GCP 1 u _6 .3 V_ X5 R _0 4
10
C
C
Y Y
Y Y Y
B B
B
Y
B B
B
T C
A C
58 K B - S I0 4 K B - S I0 4 For 8502E
14 ,2 4 L PC_ AD 0 9 L AD0 K S I0 /S T B # 59 K B - S I1 5 K B - S I1 5
14 ,2 4 L PC_ AD 1 8 L AD1
V T
S
V
T S
S T
V V
T S
S T
V V
T
S
V
B
V V
A
K S I1 /A F D # 60 K B - S I2 6 K B - S I2 6 U9 U28 Co-l ayout
14 ,2 4 L PC_ AD 2 7 L AD2 K S I2 /I N IT # 61 K B - S I3 8 K B - S I3 8
14 ,2 4 L PC_ AD 3 13 L AD3 K S I3/S LIN # 62 11 11
PC LK_ KBC K B - S I4 K B - S I4
18 PC L K_K BC 6 L PCC L K KSI4 63 K B - S I5 12 K B - S I5 12
1 4,2 4 L PC_ F RAM E# 5 L F RA ME# KSI5 64 14 14
K B - S I6 K B - S I6
14 ,2 4 S E R IR Q 22 S E R IR Q LPC K/B MATRIX KSI6 65 K B - S I7 15 K B - S I7 15
EC MODULE CHOOSE (FOR DIFFERENCE K /B TYPE)
4 ,1 8,2 3 ,2 5 B UF _ P L T_ R S T# L PCR ST #/ W UI4 /GPD 2 ( PU ) KSI7
KBC _W R ESET # 14 36 KB-SO 0 1 KB-SO 0 1 1 J_KB1 24
W R ST # K S O 0 /P D 0
VER. RX VOLTA GE MODE L_ID
37 KB-SO 1 2 KB-SO 1 2 B
K S O 1 /P D 1
19 GA 2 0
1 26
4 G A20 /G PB5 K S O 2 /P D 2
38
39
KB-SO 2
KB-SO 3
3
7
KB-SO 2
KB-SO 3
3
7
V1.0 R157 10K/ R153 X 3.3V E4120
37 A C _ IN # K B R S T # /G P B 6 ( P U ) K S O 3 /P D 3
16 40 KB-SO 4 9 KB-SO 4 9 R157 X /R153 10K 0V E5120Q
29 L ED _AC IN# 20 PW U REQ # /GPC 7( PU ) K S O 4 /P D 4 41 KB-SO 5 10 KB-SO 5 10
.
S
3 T H ERM _AL ER T# L 8 0LL AT /GPE7 ( PU ) K S O 5 /P D 5 42 KB-SO 6 13 KB-SO 6 13
23 K S O 6 /P D 6 43 KB-SO 7 16 KB-SO 7 16
30 AP_ KEY #
15 E C S C I# /G P D 3( P U ) K S O 7 /P D 7
30 W EB _EM AIL # E C S M I# /G P D 4 ( P U ) K S O 8 /A C K #
44 KB-SO 8 17 KB-SO 8 17 M OD EL_ ID R 15 7 * 10 K _ 0 4
VDD 3
c
Sheet 28 of 42
45 KB-SO 9 18 KB-SO 9 18
K S O 9 /B U S Y 46 KB-SO 10 19 KB-SO 10 19 R 15 3 1 0 K_0 4
DAC
85 0 2_ C PU_ F AN 76 KSO 1 0/PE 51 KB-SO 11 20 KB-SO 11 20
h
85 1 8_ D D_ ON 77 D AC0 /GP J0 KSO1 1 /ERR # 52 KB-SO 12 21 KB-SO 12 21 RX
KBC-ITE IT8502E
85 0 2_ IS O N 78 D AC1 /GP J1 KS O1 2/S LC T 53 KB-SO 13 22 KB-SO 13 22
e
2 3,2 9 W L AN_ EN
W LAN _ EN 79
80
D AC2 /GP J2
D AC3 /GP J 3 ITE 8502E KS O1 3
KS O1 4
54
55
KB-SO 14
KB-SO 15
23
24
KB-SO 14
KB-SO 15
23
24
m
24 3 G_POW E R 81 D AC4 /GP J4 KS O1 5
27 KBC _M UT E# D AC5 /GP J 5 ITE 8518E VDD 3
RN 1 9 VDD 3
ADC FLASH
BAT _ DET 66 10 0 2 .2K _4 P2 R_ 0 4
a
37 BAT _D ET 67 AD C0 /G P I 0 F L F RA ME# /GPG 2 10 1 3 2
BAT _ VOL T K B C _ S P I_ C E # SM D _ BAT 3 G_ DET # R 14 7 10 K _ 0 4 t
W L AN_ L ED# 68 AD C1 /G P I 1 F L A D 0 /S C E # 10 2 K B C _ S P I_ S I SM C_ BAT 4 1 CC D_ DET # R 15 0 10 K _ 0 4
2 3 ,2 9 W LAN _ LED # AD C2 /G P I 2 F L AD 1/SI
69 10 3 KBC _ SP I_ SO
i
3 T H ERM _VO L T AD C3 /G P I 3 F L AD2 /SO 10 4
2 5 LAN _ PCIE_ W AKE#
P C IE _ W A K E # 70
AD C4 /G P I 4 F L AD3 /GPG 6
8 51 8 _D D_ ON _ LAT C H
c
3 G_ DET # 71 10 5 KBC_ SPI_ SC LK 3 .3VS
24 3 G_ DET # CC D_ DE T# 72 AD C5 /G P I 5 F L CL K/SCK 10 6
24 C CD _D E T # MO DEL _ ID 73 AD C6 /G P I 6 ( PD )F L R ST# /W U I7 /TM /GPG 0 C C D _E N 24 ITE 8502E W L AN _L ED # R 36 0 * 1 0 K _ 04
D
AD C7 /G P I 7 85 0 2 _D D_ ON _L AT CH R 37 1 0_ 0 4
GPIO 56 85 0 2 _W L AN _D ET # DD _O N_ L AT CH 3 1
R 37 2 0_ 0 4
SM C_ BAT 1 10
SMBUS ( PD )K SO1 6/GPC 3 57 SUS B# 1 6,2 3,3 1
85 0 2 _BT _ DET # R 37 3 0_ 0 4
W L AN_ DET # 2 3 i
37 SMC _ BAT SM D_ BAT 1 11 S M C L K 0 /G P B 3 ( PD )K SO1 7/GPC 5 S U S C# 1 6, 3 3 85 0 2 _D D_ ON BT _D ET # 2 3 ,2 9 a
37 SMD _ BAT R 37 4 0_ 0 4 D D _O N 3 1 C2 1 5
1 15 S M D A T 0 /G P B 4 93 85 0 2 _ISO N R 37 5 0_ 0 4 PCL K_ KBC R 16 4 * 10 _0 4 PCL K_ KBC _R
1 16 SM CL K1 /GPC 1 ( P D ) ID 0 /G P H 0 94 SUS _PW R _ ACK 1 6 85 0 2 _C PU_ F AN I S ON 25
M E _ WE # 1 4 R 37 6 0_ 0 4 CPU _F AN 3 0
1 17 S M D A T 1 /G P C 2 ( P D ) ID 1 /G P H 1 95
3,1 5 SMC _ CP U _T HE RM SM C_
D_ CPU _T H ERM 1 18 SM CL K2 /GPF 6 ( PU ) ( P D ) ID 2 /G P H 2 A C _ P R E S E N T 1 6,1 8 *1 0p _ 5 0V_ N PO_ 0 6
3,1 5 SMD _ CP U _T HE RM
96 8 5 0 2_ DD _ ON_ L AT C H
g
r
SM DAT 2 /GPF 7 ( PU ) ( P D ) ID 3 /G P H 3 97 8 5 0 2_ W L AN_ D ET#
( P D ) ID 4 /G P H 4 98 8 5 0 2_ BT _ DET #
0831
PWM
L CD _B R IGH T NE SS 24 ( P D ) ID 5 /G P H 5 99 8 5 0 2_ DD _ ON
a
KBC _BE EP 25 PW M 0 /GPA0 ( PU ) ( P D ) ID 6 /G P H 6 ITE 8518E m
27 KBC _ BEEP 28 PW M 1 /GPA1 ( PU ) 10 7 85 0 2 _D D_ ON _L AT CH R 37 7 * 0_ 0 4 C2 0 0
2 9 LE D _ SCR OL L# 29 PW M 2 /GPA2 ( PU ) ( P D ) ID 7 /G P G 1 3 G _EN 24 85 0 2 _W L AN _D ET # R 37 8 * 0_ 0 4 8 51 8 _S PI _C S0 # 1 4 B AT_ VO LT
29 L ED_ NU M# 30 PW M 3 /GPA3 ( PU ) 8 518 _S PI_SC L K 1 4 37 BAT _ VOL T
85 0 2 _BT _ DET # R 37 9 * 0_ 0 4
29 L ED_ CAP# 31 PW M 4 /GPA4 ( PU ) EXT GPIO 82 85 0 2 _D D_ ON R3 8 0 *0 _ 0 4 8 518 _S PI_SO 1 4 1u _ 6. 3V_ X5 R_ 04
LOW ACTIVE 29 L ED_ BAT _ CH G# 32 PW M 5 /GPA5 ( PU ) ( P D ) E G A D /G P E 1 83 S MI # 19 8 518 _S PI_SI 14
s
2 9 LED _B A T_ F U LL # 34 PW M 6 /GPA6 ( PU ) ( P D ) E G C S # /G P E 2 84 S CI # 19
29 L ED _P W R# PW M 7 /GPA7 ( PU ) ( P D ) E G C L K /G P E 3 PW R _BT N # 1 6
85 1 8 _D D_ ON _L AT CH R 38 5 * 0_ 0 4
85 1 8 _W L AN _D ET # R 38 7 * 0_ 0 4 DD _O N_ L AT CH 3 1
8 0 CL K 85
PS/2 WAKE UP 35 85 1 8 _BT _ DET # W L AN_ DET # 2 3
R 38 6 * 0_ 0 4
23 8 0 CL K 3 IN1 86 PS2 C LK0 /G PF 0( PU ) ( P D ) W U I5/G P E 5 17 RSM RST # 1 6 85 1 8 _D D_ ON R 38 8 * 0_ 0 4 BT _D ET # 2 3 ,2 9 SM C_ CPU _ TH ERM
23 3 IN 1 8 0 DET # 87 PS2 D AT0 /G PF 1( PU ) ( P D ) L P C P D # /W U I6 /G P E 6 KBC _R ST # 1 9 85 0 2 _C PU_ F AN D D _O N 3 1 4 ,1 9 H_ PEC I
R 38 9 * 0_ 0 4 R 17 5 *0 _0 4
23 8 0D ET # 88 PS2 C LK1 /G PF 2( PU ) 85 0 2 _ISO N R 39 0 * 0_ 0 4 I S ON 25
18 PM E# 89 PS2 D AT1 /G PF 3( PU ) PWM/COUNTER 47 CPU _F AN 3 0
30 T P_ CL K PS2 C LK2 /G PF 4( PU ) ( P D ) T A C H 0 /G P D 6 48 C P U _ FA N S E N 3 0
90 MC H_ T SATN _ EC
30 T P _D A T A PS2 D AT2 /G PF 5( PU ) ( P D ) T A C H 1 /G P D 7
12 0
1 25 WAKE UP ( P D )T MR I0/W UI 2 /GPC 4 12 4 VCO RE_ O N 1 6 ,36
37 V CHG _ SEL PW R SW /G PE4( PU ) ( P D )T MR I1/W UI 3 /GPC 6 AL L_ SY S_ PW RG D 1 2 ,16 VDD 3 C2 0 1
For 8512E
18
CIR 11 9 8 51 8 _W LAN _ DE T #
KBC_SPI_*_R = 0.1"~0.5"
31 PW R _S W # 0 .1 u_ 1 6 V_Y 5 V_0 4
21 R I1# /W U I0 /GP D 0( P U ) ( P D ) C R X /G P C 0 12 3 8 51 8 _B T_ DE T#
12 ,3 0 L ID_ SW # R I2# /W U I1 /GP D 1( P U ) ( P D ) C TX /G P B 2
U9
8 5 KBC _S PI_SI _R R 39 1 4 7 _ 04 K B C _S P I_S I
33
GP INTERRUPT LPC/WAKE UP 19 VD D SI
30 W EB _W W W # G INT /GPD 5 ( PU ) ( PD )L 80H LAT /G PE0 S WI # 16 2 K BC _S P I_S O _ R R 39 2 1 5 _ 04 K B C _S P I _S O
11 2 R1 3 5 1 K_ 1% _ 0 4 ? ? ? SO
( PD )R ING #/ PW RF AIL # /L PCR ST# /G PB7 C H G _E N 37 3 1
KBC _ F LAS H KBC _S PI_C E# _R R 39 3 1 5 _ 04 KBC _SP I_C E#
1 08
UART W P# CE#
23 ,2 9 BT_ EN 1 09 R XD /GPB0 ( PU )
CLOCK 2 6
S CK3 2 KE KBC _S PI_SC L K_R R 39 4 4 7 _ 04 K B C _S P I_S C L K
12 BKL _ EN T X D /G P B 1 ( P U ) S
S S
S S
S S S C K 3 2K E 12 8 CK3 2 K R1 6 2 4 .7 K_0 4 SC K
S
S S
S S
S S V C K 3 2K
V V V V V V V A R 16 9 * 1 0M _ 0 4 KBC _ HOL D # 7 4
HO L D# VS S
IT8 5 02 E
1 2 7 9 1 3 2 5 AT25F512AN f or 8502 6- 04-25320-A70
1 2 4 9 1 2
1 1
7
X3 U9U28Co-l ayout * MX2 5L 3 20 5 DM 2 I-12 G
2I - 12G f or 8518 6-
MX25L3205DM 04-02532-470
EC_ VSS
R3 9 5 * 0_ 0 4
1 4
6- 04-26321-470
R 16 8 * 0_0 4
2 3 C K3 2KE
C 2 23 0 .1 u_ 1 6V _ Y 5V _ 04 C 22 7 C 2 21 VD D3 1 4, 23 ,25 ,29,3 1 ,32 ,3 7
C K3 2K Co-la yout X2, X3 3 .3 VS 2 ,1 0,1 1 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 ,1 8,1 9 ,2 0,2 1 ,2 3,2 4 ,2 5,2 6 ,2 7,2 9 ,3 0,3 1 ,3 5, 36
0_04 FOR IT8512CX/EX 1 2 p_ 5 0 V_N PO_ 0 4 1 2 p _5 0 V_ NPO _0 4
0.1U_04 FOR ITE8512-J(ITE8502-J W/0 CIR) NC 3 SH O RT 1 4 X2
* MC - 14 6 _ 32 .7 6 8KH z 2 3
EC Cost Down
1T J S1 25 D J4 A4 2 0P_ 3 2 .76 8 KHz
6-2 2-32R76-0B4
12 B R IG H T N E S S R 1 51 * 10 m il_ sh o rt_ 04L CD _BR IGH T NESS KBC _AG ND 6-22-3 2R76-0B2
6-22-3 2R76-0BG
C2 11 * 0. 1 u_ 16 V _ Y 5V _ 04
KBC-ITE IT8502E B - 29
Schematic Diagrams
LED, MDC, BT
3 V_ BT
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf Bluetooth(Port8) COSTDOW
N 79/96
3 .3V
Port 11
18 U SB PN1 1
J _ BT1
1
2
3
18 U SB_ PN1 1 3
MJ_ MDC
1
20 MI L 1.5 V
R 2 92
18
2 3 ,2 8
U SB_ PP1 1
BT_ DE T#
4
5
12 11 BT _EN #
R 1 67 * 15 m il_ s ho rt_ 0 6 4 7 K_ 1% _ 0 4 6
2 1 3 .3 V
87 2 1 2-0 6 G0
3 .3 V R 3 08 * 0_ 0 4
BT _D ET # 1 5 ,23 PC H_ BT _E N#
J_ MD C1
1 2 R166 * 0_ 0 6 3 .3 V
R 1 65 33 _ 0 4 HD A_SD OU T_ R 3 G ND R E S E RV E D 4 C 4 01 R3 09
From EC default HI
1 4 ,27 H DA_ SDO UT 5 Az a li a _SD O
G ND
R E S E RV E D
3 .3 V Ma in /au x
6 MD C_ 3.3 V 10mil L 1 6 * 1 5 m i l _s h o r t _0 6
R 1 61 33 _ 0 4 HD A_SY NC _R 7 8 *1 8 0 p_ 5 0 V_N PO_ 0 4 10 K_ 0 4 3 .3 V 3 V_ BT
1 4 ,27 H DA_ SYN C 9 Az a li a _SY NC GND 10 R3 0 6
R 1 59 22 _ 1 %_ 0HD
4 A_SD IN1 _ R 5 0m il 50 mi l
1 4 H DA_ SDIN 1 R 1 55 33 _ 0 4 HD A_R ST #_ R 11 Az a li a _SD I GND 12 HD A_B ITC LK _R R 15 2 33 _04 BT _ EN#
1 4 ,27 H DA_ RST # Az a li a _R ST # Aza li a _ BCL K HDA _BIT C LK 1 4 ,2 7
D
88 0 1 8-1 2 0G C 21 7 C 21 2 *1 5m il_s h o rt_0 6
Q1 5 C 39 8 C3 95
0 .1 u_ 1 6 V_Y 5V _0 4 2 2 p_ 5 0 V_N PO_ 0 4 2 3,2 8 BT _EN G MT N7 0 02 Z H S3
4
S
0 10 u _ 6.3 V_ X5R _0 6
_
O
P
G ND N
_
V
0
5
_
p
s
0
8
1
m
a
r
g Sheet 29 of 42 LED 3 .3V S 3.3 VS 3 .3 VS 3 .3VS
3 . 3V S 3 . 3V S V DD3 V D D3 V DD 3 V DD3
a
i LED, MDC, BT E
R6 R5 R 1 93 R 19 4 R1 96 R 1 95
D
B R2 R3 R4 2 2 0_ 0 4 2 20 _ 0 4 * 2 20 _ 04 * 22 0 _ 04 *2 20 _ 0 4 * 2 20 _ 04
S ATA_ LED# 1 4
Q3 2 2 0_ 0 4 22 0 _ 04 22 0 _0 4 POWER ON BAT LED
c
C DT A1 14 EU A BT WLAN LED
i
1 3 1
1 3 1 3
LED LED
t
R1 1 3 D1 D1 3 D1 4
A A A 2 G
HDD/ODD NUM CAPS SCROLL Y G
S
Y G
S
Y
S
a
22 0 _ 04 D3 D4 D5 2 4 R Y-SP1 5 5 HYY G4 *R Y-SP1 5 5H YY G4 *R Y-SP1 5 5 HYY G4
LED LOCK LOCK LOCK 2 4 2 4 2 4
M M M
A
5
- LED 5
- LED 5
- LED R 3 43
m
4 4
3 3 4
D2 G G 3
C Y C Y C G W L AN _L ED # 2 3 ,2 8
Y
e
0 0
7 0 C
M 7 1 7
*1 0 m il_ sh o rt_ 04
5
- 1 P 1 B L ED _PW R# 28 LED _B AT_ F U LL # 2 8
4 P S P W L AN_ EN 23 ,2 8
3 S
- - S
-
C G Y Y LE D_ ACIN # 2 8 L ED_ BAT _C HG # 28
Y Q2
h
c
Y
0 R R R *D T C1 14 EU A
7
1 LE D_ NU M# 2 8 LE D _ C AP # 2 8 L E D_ S CR O LL # 28 E
P
S
S
-
C
Y 6 -5 2- 520 01 -02 7 6 -52 -5 20 01- 02 7 6- 52- 52 001 -0 27 E4120
.
R B
6-52-52001- 027 BT_ EN 2 3, 2 8
B
Q1 4 ,9 ,1 0,1 1 , 2 1,2 3 ,2 7,3 1 ,3 3,3 6 1 .5V
D TC 11 4 EUA
E 3 ,4 ,1 2,1 4 , 1 5,1 6 ,1 8,1 9 , 2 0,2 1 ,2 3,2 4 ,2 5,3 0 ,3 1,3 3 ,3 4,3 5 3 .3V
1 4,2 3 ,2 5,2 8 , 3 1,3 2 ,3 7 V DD3
2 ,1 0,1 1 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 , 1 8,1 9 ,2 0,2 1 , 2 3,2 4 ,2 5,2 6 ,2 7,2 8 ,3 0,3 1 ,3 5,3 6 3 .3V S
H2 5 H1 4 H1 3
M1 M5 M7 M8 M2 9 9 9
M-M ARK1 M -MAR K1 M-MA RK1 M-M ARK1 M -MAR K1 3 8 3 8 3 8
H1 0 H8 4 1 7 4 1 7 4 1 7
H6 _ 3 D3 _8 H 6_ 3 D4 _ 4 5 6 5 6 5 6
C 46 8
MT H3 1 5 D1 1 1 MT H 31 5 D1 1 1 M TH 31 5 D1 1 1 *0 .1 u_ 1 6V _Y 5V _0 4
V DD 3
H2 H1
C1 58 D 15 8 C 1 58 D 15 8 M6 M3 M4 H5 H3 H2 4
M-MA RK1 M-M ARK1 M -MAR K1 9 9 9 GN D
3 8 3 8 3 8 J _ T P4
4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 1 L ED_ PW R #
2 L ED_ ACIN #
3 L ED_ BAT _ F UL L #
MT H3 1 5 D1 1 1 MT H 31 5 D1 1 1 M TH 31 5 D1 1 1
H1 8 H 15 H1 7 H 12 4 L ED_ BAT _ CHG #
H6 _ 0 D3 _ 7 S1 S2 H 4_ 7 B6 _0 D 3_ 7 H4 _7 B6 _ 0D 3 _7H 6_ 3 D3 _ 8 5
SMD 80 X8 0 SMD8 0 X80 H1 1 H7 H2 2 6
9 9 9 8 52 0 1 -06 0 5 1
1 1 3 8 3 8 3 8
1 1
4 1 7 4 1 7 4 1 7 GN D
5 6 5 6 5 6
MT H3 1 5 D1 1 1 MT H 31 5 D1 1 1 M TH 31 5 D1 1 1
H2 3 H6 H2 1 H 20 H1 9 H 16 H9 H4
C6 7 D6 7 C6 7 D6 7 C1 58 D 15 8 C 15 8 D1 5 8 H4 _ 0 B7_ 0 D3 _ 7 H 4_ 0 B7 _0 D 3_ 7 9 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
MT H3 1 5 D1 1 1 M TH 31 5 D1 1 1
B - 30 LED, MDC, BT
Schematic Diagrams
USB, Fan, TP, Multi-Conn

USB PORT*2(Port 0,Port1) FAN CONTROL
5V S F A N 5 VS U19
5 V S _F A N 5 VS U19
U4 F ON # 1 8
5V USB_ F L G# 5 6 U SB VC C0 1 2 FON GN D 7
F L G# VO UT 1 3 VIN GN D 6
2 7 100 MIL 4 V O UT
GN D 5
V I N 1 VO UT 2 28 CPU _F AN VSET GN D
C 94 3 8 C1 10 C1 21 C1 28 G 9 90 P1 1U
V I N 2 VO UT 3
1 0 u_ 6 .3 V_X5 R_ 0 6 4 1 0.1 u _1 6 V_ Y5 V _ 04 0.1 u _1 6 V_ Y5 V _ 04 *1 0u _ 6 .3V_ X5 R_ 06 G990P11U 6- 02-99011-B20
EN# G ND
31 ,3 3 DD _O N# U P75 3 4 DSA8 -2 0 P2793A 6- 02-02793-B20
UP7534D 6-02 - 75348- 920

5 VS 5 VS_ F AN
RT9715BGS 6- 02-09 715-920 J _ F AN1
APL3510 6-02- 03510- 920
U SBVCC 01 C 3 94 12
C3 9 0
3
0 .1 u _1 6 V_ Y 5 V_ 04
L10 U SB_ VCC 01 _ 0 1 0u _ 6 .3V_ X5 R_ 06 85 2 0 5-0 3 7 01
* 15 m il_ s ho rt_ 0 6 60 mil
C 95 +C 92 C 80
+
2 20 u _6 .3 V_ 6.3 * 6.3 *4 .2 * 10 0 u_ 6 .3 V_B_ A 0 .1 u_ 1 6 V_Y 5V _0 4 Port 0 28 CPU _ F ANSEN
R 2 75 4. 7K _0 4
B
3 .3 VS
JFAN
.
S
3
J _ USB1
1 c
1
V+
18 US B_PN 0
4 L9 3 2
DAT A_ L Sheet 30 of 42 h
18 U SB_ PP0
1 2 3
DAT A_ H CLICK CONN FOR CLICK BOARD
USB, Fan, TP,
*W C M2 01 2 F 2 S -16 1 T 03 -s h ort
e
4 1 2 3 4
GN D D D D D m
N
N N N
3 .3 V 3 .3 V G G
G
G
6- 21- B4400- 004

1 -28 4 - 8 00 2 81 1 2 3 4
D D D
N N D
N N 5 VS_ T P
Multi-Conn a
R7 4 R7 7 G G
G G
USB_ VC C0 1 _0 t
10 K_ 0 4 *1 0 K_0 4
R 94 * 15 m i _l s ho rt_ 0 6
5V S
U SB_ F LG #
i
c
18 U SB_ OC# 0 1
80 mil C 1 58 C1 6 3
R7 3 R8 5 R8 4
*0 _0 4 * 1 0u _ 6.3 V_ X5R _ 06 1 u_ 6 .3 V_X5 R_ 0 4 D
+C1 2 9 C1 7 1 J_ T P1 10 K_ 0 4 10 K_ 0 4
1
*1 0 0u _ 6 .3V_ B_ A 0 .1u _ 1 6V_ Y 5V_ 0 4 T P_D AT A 2 8
i
2
Port 1 3 T P_C L K 2 8
a
4 C1 5 3 C1 4 9
8 52 0 1- 04 0 51
J_ U SB2 47 p _ 50 V_ NPO _0 4 47 p _ 50 V_ NPO _0 4
1
g
r
V+ a
4 L13 3 2
18 USB_ PN 1 D AT A_L m
1 2 3
18 U SB_ PP1 D AT A_H
*W C M2 01 2 F 2 S-16 1 T 03 -s h ort
4
G ND
1 2 3 4
N
G
D D
D D
N N
G G
N
G
POWER SWITCH CONN. s
1 -2 8 4- 8 0 0 28 1 1 2 3 4
6-21- B4400-004 D
N
D D
N N
D
N
CLOSE TO J_SW1
G
G G
G
FOR POWER SWITCH BOARD AP_ KEY#
AP_ KEY# 2 8 3 .3 VS 3 .3 V
3 .3 VS 3 .3V D
C 21 C2 0 Q6 J_ SW 2
G 20mil
Audio/B CONN.(Port 2) 5V 0 .0 1u _ 5 0V_ X7 R _ 04 0. 01 u _5 0 V_ X7 R_ 0 4
S
* MT N7 0 0 2Z H S3 1
2
3
MBT N R 18 * 10 m il_ sh o rt_ 04 M_ BT N#
W EB_ W W W #
1.1A 60mils 4 W EB_ EMAIL #
C2 1 4 0. 01 u_5 0 V_X7R _0 4 J_ SW 1 5 LID _ SW #
20mil R 21 6
FOR AUDIO BOARD 1
2 M_ BTN # _R
*1 0 mil_ sh o rt_0 4 7
8
AP_ KEY#
J _ AUD IO1
R 15 4 * 1 5 mil _ sh ort _ 0 6 3 W EB_W W W # M _ B T N# 31 88 4 8 6-0 8 01
MIC 1-R 1 4 W EB_E MAIL # W EB_ W W W # 2 8
2 7 MIC 1-R 2 5 W EB_ EMA IL# 2 8
MIC1-L LID _SW #
2 7 MIC 1-L 3 6 L ID_ SW # 12 ,28
R 18 1 2 2 0 _0 4 H E A DP H O NE -RR 4 7 AP_O N
2 7 HE A D P HO NE -R H EADPH ONE -LL 5 8 A P _O N 31
2 7 HE A D P HO NE -L R 18 0 2 2 0 _0 4 3 ,4,1 2 ,1 4,1 5 ,1 6,1 8 ,1 9,2 0 , 21 ,2 3 ,24 ,2 5 ,29 ,3 1 ,33 ,3 4 ,35 3 .3 V
MIC _SEN SE 6 9
2 7 MIC _SEN SE SPK_ HP# 7 10 VIN 2 ,13 ,1 7 ,20 ,2 1 ,26 ,2 7 ,31 ,3 5 , 36 5 VS
8 21 ,2 4 ,31 ,3 3 , 34 5 V
18 US B_PN 4 R 1 72 * 1 0 m i l _ s h ort _0 4 USBN 4 _R HP _ S E NS E
2 7 HP_ SEN SE USBN 4_ R 9 *5 0 50 0 -0 10 4 1-0 0 1 L
10 1 2 ,31 ,3 2 ,33 ,3 4 ,35 ,3 6 ,37 VIN
18 U SB_ PP4 R 1 74 * 1 0 m i l _ s h ort _0 4 USBP4 _ R USBP4 _ R
11
12 2,1 0 ,1 1,1 2 ,1 3,1 4 ,1 5,1 6 ,1 7,1 8 ,1 9,2 0 ,2 1,2 3 , 24 ,2 5 ,26 ,2 7 ,28 ,2 9 ,31 ,3 5 ,36 3 .3 VS
SPKOU TR +
2 7 SPKOU T R+ 13
SPK OUT R-
2 7 SPKOU T R- 14
8 7 2 13 -1 4 00 G
I f systemhas APON functi on, uses J _SW 1

I f system has no APON f unct i on, uses J _SW2
USB, Fan, TP, Mult i-Conn B - 31
Schematic Diagrams
5VS, 3VS, 1.5VS

VA VIN VIN1
PC 64 PC6 3 PC6 2
SYS5 V SY S5 V
0 .1 u_ 5 0 V_ Y5 V_ 0 6 0 .1u _ 5 0 V_Y 5 V_ 06 0.1 u _ 5 0V _Y 5 V_ 06
ON PR 2 13 PR2 1 1
DD_ON "L" TO
P U4 1 0 K_ 04 1 0K _0 4
1 8 "H" FROMEC
8/18/2019 VA
2
VA clevo+6-71-w24h0-d02a.unlocked.pdf
VIN 1
7
VIN 1
DD _ ON # S US B
VIN R1 32 * 1 0m i l _sh ort _ 04 DD _O N_ L ATCH 2 8 DD _O N# 3 0, 3 3
VIN D D_ O N _ L ATC H
3 6
30 M_ BT N# M _ BTN # PW R _SW # P W R_ S W # 2 8 P Q4 4 A 6 PQ 44 B 3
4 5 PR 98 MT DN 7 0 02 Z H S6 R D M T DN 70 0 2 Z HS 6R D
30 AP_ O N IN ST ANT -O N GN D
1 0 K_ 04
P 28 0 8 A1 2 G PC 1 88 5 G PC1 8 9
VD D3 28 DD _O N 16 ,2 3 ,2 8 S U S B #
S S
ON
1 * 0.1 u _ 1 6V_ Y 5 V_0 4 4 *0 .1 u _1 6 V_ Y5 V_ 0 4
PR2 1 0 P R2 1 2
ON
1 00 K_ 1 % _0 4 1 0 0 K_ 1 %_ 0 4
5V
s ON
ON
m C2 0 4 C 2 64 C9 1
a
r
0.0 1 u _ 50 V_ X7 R_ 0 4 0 .0 1 u _5 0 V_ X7R _ 04 0 .0 1u _ 5 0V _X7 R_ 0 4
g Sheet 31 of 42
a
i 5VS, 3VS, 1.5VS 5V 5VS 1.5VS
D NMO S
c
i SY S1 5 V V D D5 PQ 4 6A S Y S 1 5V V DD 5 PQ 45 A 5 VS SYS 15 V 1 .5 V
NMO S 1 .5V S
t
M T NN 20 N 03 Q 8 5V M TN N2 0 N0 3 Q8 PQ 1 6A
8 2 8 2 M TN N2 0 N0 3 Q 8
a PR 1 13
3A 7 1 3A
Power Plane
5V
PR1 1 2
7 1
PR2 1 4
8
7
2
1
m 1 M_ 0 4 3
1M _ 04 3
P C1 9 2 1M _ 04
e
3
P C1 9 1 PC1 9 0 PR1 1 1
Z 3 5 06 Z3507 0 .1u _ 1 6 V_ Y5 V_ 04
1 .5 VS_ EN 0 .1 u _ 16 V_ Y 5V _0 4 10 u _ 6. 3V_ X5 R_ 0 6 10 0 _ 1 %_ 0 4
4 4
P Q4 6 B PQ 45 B
4
M T NN 20 N 03 Q 8 M TN N2 0 N0 3 Q8 PQ 1 6 B DZ 3 51 5
h
c
PC 73 PC7 2 M TN N2 0 N 03 Q 8 PQ1 5
5 DD _ ON # 5 PC1 9 3 MT N7 0 0 2 Z HS3
S
S US B 33 5 S US B G
4 7 0 p_ 5 0 V_ X7 R _0 4 47 0 p _5 0 V_ X7 R_ 0 4
.
1 1
6 6
22 0 0 p _5 0 V_ X7R _ 04
S
PJ 15 P J1 6 6
B 2
4 0m il 2
40 m il
VA 37
1 .5VS_ CPU 4 ,7
ON ON 1 .5 V 4 ,9 ,10, 11,2 1 ,23,2 7,2 9 ,33 ,3 6
3 .3 V 3. 3VS 1 . 5V S 2 0, 2 3,3 6
S Y S 5V 3 2, 3 7
5 V 2 1, 2 4,3 0 , 3 3 ,3 4
3 .3 V 3 ,4 ,1 2, 14 ,1 5 ,16,1 8 ,19 ,20 ,21 ,2 3 ,24 ,2 5 ,2 9, 30 ,3 3 ,34,3 5
C1 3 0 C1 0 0 C184
0.0 1 u _ 50 V_ X7 R_ 0 4 0 .01 u _ 5 0V _X7 R_ 0 4 0 .0 1 u _5 0 V_ X7R _ 0 4 1.5VS_CPU V IN 1

VIN
V DD 5
32
1 2,3 0,3 2,3 3,3 4,3 5,3 6,37
32
VD D3 1 4,2 3,25 ,28 ,2 9,3 2 ,3 7
3.3V 3.3VS 1 .5 V
PJ7
OPEN _ 2A
1 .5 VS_ CPU
PJ3 MUST SHORT

3 .3 VS 2 ,1 0 ,11 ,1 2 ,1 3 ,14 ,1 5 ,1 6,1 7 ,1 8 ,1 9,2 0 ,2 1 ,23 ,2 4 ,2 5, 26 ,2 7 ,2 8,2 9 ,3 0 ,35 ,3 6
S Y S 15V 3 2
2 1 5 VS 2 ,1 3,17 ,20 ,2 1,26 ,27 ,3 0,3 5 ,36
NMO S 3 .3 VS SYS1 5 V
SY S1 5 V V D D3 PQ 4 0A 3 .3 V SYS1 5 V P Q1 4 A
V DD 3
M T NN 20 N 03 Q 8 M T NN 20 N 03 Q 8 PQ 4A NM OS PR 73
3A 8 2 3A 8 2 *M T NN 20 N 0 3Q 8
7 1 7 1 P R7 6 8 2 *2 2 0 _0 4
PR 1 92 P R1 1 0 7 1
Power Plane
* 1 M_ 0 4
1 M_ 0 4 1 M _0 4 PC6 9 PC7 1 PR1 0 9 P C2 7 PC 2 6 6
3 3 1
5
3 3
Z 3 5 08 Z3509 0. 1u _ 1 6V _Y 5 V_ 04 1 0u _ 6 .3 V_X5 R _0 6 *1 0 0 _1 % _ 0 4 1 .5 VS_ CP UEN *0 .1 u_ 1 0 V_ X7R _ 04 * 10 u _ 6 .3V _X5 R_ 0 6 Z
4 4 4
P Q4 0 B PQ1 4 B DZ 3 5 10 PQ 4 B D

M T NN 20 N 03 Q 8 M T NN 20 N 0 3Q 8 PQ1 3 *M T NN 20 N 0 3Q 8 PQ 3
PC 1 67 P C7 0 *M T N7 0 02 Z H S3 P C2 8 *M T N7 0 02 Z H S3
5 DD _ ON # 5 SU SB G 5 SU SB G
2 2 0 0p _ 5 0V _X7 R _ 0 4 2 2 0 0 p_ 5 0 V_ X7 R _0 4 S
* 2 20 0 p _ 50 V_ X7 R_ 0 4 S
6 6 6
ON ON
B - 32 5VS, 3VS, 1.5VS
Schematic Diagrams
Power 3.3V/5V
S YS5 V
PC1 6 8
0 .0 1 u _ 50 V_ X7 R_ 0 4
PD7
BAT 54 SW GH
A 1
SY S5 V
C8 8 L GAT E1 Z3613 3 C
A 2
SY S1 0 V
V IN 1 VIN 0. 01 u _ 5 0V _X7 R _0 4
PD6 PC 16 2
Z 36 0 4 P R 2 04 2 _ 06 PC1 6 9 BAT 54 SW GH
A C A 1
0 .0 1 u _ 50 V_ X7 R_ 0 4 2 2 00 p _ 5 0V _X7 R _ 0 4
PC 1 83 PC 18 4 Z3614 3 C
2 .2 u _1 6 V_ X5 R_ 0 6 1 0 0 0 p_ 5 0 V_ X7R _ 04 PR 1 9 6 PD2 0 R B0 5 4 0S 2 A 2
SY S1 5 V
IN TV C C 2
6-13-42231-28B 2_06 PC 16 3
P R 20 3 4 22 K _1 %_ 06 SG N D 4 Z 36 0 5 2 2 00 p _ 5 0V _X7 R _ 0 4
Z3606
P R2 0 5
PR 1 9 0 P R1 9 5 7 5 K_ 0 4 PC4 6 PC5 2 P C5 3
1 0 K _ 1 %_ 0 4 2 0 K_ 1 % _0 4
1
2 1 2 3 4 5
PU8 PC 18 1
1 u _2 5 V_ 0 8 8 8
6 0 0
0 _
T _ _
D B L A C V R R
SG ND 4 SG N D 4 F B D U 5 5 5
A F N
Z 3 6 02 20 P D O 6 Z3607
Y X X
V V _ _ _
EN L VI N V V V
0 5 5
VDD5
5 2 2
Z 3 6 03 19 7 PC1 7 2 _ _ _
R T ON VL D O IN T V C C 2 u u u
B
1 u _2 5 V_ 0 8 1 7 7
.
18 8 Z3608 5 6 7 8 . .
0 4 4
AG ND SC418 BST PQ 1 1 SY S5V VD D5 .
Z3601 17 9 Z3609 4 P1 2 0 3 BV PL 8 S
E N /P S V DH 4 .7 UH _ 6.8 * 7. 3* 3 .5 PJ 2 3
16
D
10 Z 3 6 1 0 1 2 3 1 2 5A 1 2
IL IM O V P D
LX c
O S D N
Sheet 32 of 42
PC 1 7 3 PC 1 7 9 P R1 9 8 P C1 7 5 P R1 9 3 *O PE N- 5m m
G P D L G 5 6 7 8
P R V D P PQ7
4
4
P1 20 3 BV C C P R1 8 5 PC 18 5 PR2 0 8
h
0
0
_ 5 4 3 1 4
_ R 1 1 1 2
1 1 L GAT E1
Power 3.3V/5V
R
7 8 4 7 4
PD 5 PD8 *2 .2 _ 0 6 *2 2 0 p _ 50 V_ 0 4 9 3.1 K_ 1 % _ 0 6
e
X
_
0
_
0
_ X
_
0
_ OCP 1 2 3
*SK3 4 SA m
V V
5 % V %
0 2 1 0 1 H PC 1 6 5 P C5 4 P C1 7 0
5 _ _ 1 _ S
A A
K _ K Z 36 1 1 P R 19 1 1 0 K _ 1 %_ 0 4 P C1 6 1 + + PR2 0 9
_ u 0 u 7 0
p
0 1 1 1
. 3 4 0 .1 u _ 50 V_ Y 5 V_ 06 *1 5 mil _ s ho rt_ 0 6
1
0
0
0
*
1
PR 18 6 Z 36 1 2 P R 18 7 * 1 0 0 K _ 1 % _0 4 D PC 18 6 PR2 0 1 * 1 50 u _ 6 .3V _V _A 22 0 u _ 6 .3V _6 .3 * 6.3 * 4. 2
a
1 O *2 2 0 0p _ 5 0 V_ X7 R _ 04
S
1 1 3 K_ 1% _ 0 4 PC 16 6 PC 1 77 C * 10 0 p _ 50 V_ N PO _0 4 1 0K _1 % _ 0 4
t
i
2009/12/22 S GN D4 c
SG ND 4 SG ND 4 SG ND 4 SG N D4 1 u _2 5 V_ 0 8 1 u _ 25 V _ 0 8
S GN D4
D
i
a
S YS5 V I NT VC C2
g
r
a
P R2 0 2 PR 2 0 0 m
* 1 5m il _ sh o rt _ 0 6 * 0 _0 6
P R 18 8 * 9. 1 K _ 0 4
S YS5 V
s
A VIN
PR 2 07
PD2 1 *1 5 m il _ s h o rt _ 06
4
OCP RB0 5 4 0 S2
0
PC5 7 PC 5 5 P C5 6
_
O Ra C 5 6 7 8 8
P P R 18 9 1 0 K _ 1% _0 4 0
P R1 9 4 7 N PR1 9 9 5 _
8 _ 2 R
Z3618 4 0. 1u _ 5 0 V_ Y5 V_ 0 6 4 .7 u _2 5 V_ X5 R_ 0 8 5
1 V 6
VDD3
C 0 3 X
1 0 K_ 1 % _0 4 5 1 0K _1 % _ 0 4 PR 1 97 _
P _ Z 1 2 3 V
p 0_04 PC1 7 8 PQ 8 5
0 2
0 3 4 5 PU9 P1 2 0 3B V _
1 1 1 1 6
1 u
SC4 1 2 A 0.1 u _ 5 0V _Y 5 V _ 0 6 7 SY S3 V
.
4 VDD 3
PJ 2 2
Z 3 6 15 12 M C
I . C
. H
D
1 Z3619 1 2 5A 1 2
EN L N N
I LX
11 2 Z3620 PL 9 *O PEN -5m m
PG D BST
4 .7 U H_ 6 .8 *7 .3 *3 .5
10 3 5 6 7 8
Z 3 6 16 Z3621 PQ4 1 PR 1 84
VO UT VCC C C
P1 20 3 BV PC 44 PC 1 74
Z 3 6 17 9 4 Z3622 4 * 2.2 _ 0 6 +
FB D
DL P D1 8 PD 1 7 0 .1 u _5 0 V_ Y5 V_ 0 6
N 1 2 3
PC1 8 2 C C
. T N 17 * SK3 4S A 2 2 0 u_ 6 .3 V_ 6 .3 *6 .3 *4 .2
Rb .
N N PAD
R G PC 1 80 H PC 1 60
4 S
A A
P C1 7 1 PR2 0 6 PC 1 76 0
0 8 7 6 5 4
_ 1 u _2 5 V_ 0 8 1
0 .0 1 u _5 0 V_ X 7 R_ 0 4 O 2 .94 K_ 1 % _ 0 4 0 .0 1 u_ 5 0 V_ X7R _ 0 4 D * 22 0 0 p _5 0 V_ X7 R_ 0 4
P O
N S
_ C
V
0
5
p
_
7
4
*
V IN 1 31
S Y S 1 5V 3 1
VDD 3 1 4 ,23 ,2 5, 2 8 ,29 ,3 1,3 7
VDD5 31
S Y S 5V 3 1,37
V IN 1 2,3 0 ,3 1, 3 3 ,3 4,3 5 ,3 6,3 7
Power 3.3V/5V B - 33
Schematic Diagrams
Power 1.5V/0.75V, 1.8VS

5V 3 .3 V
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf V D DQ VIN
83/96
PR8 8
A
P R9 4 PR 96 10 0 K_ 1% _ 0 4
PD 4
(1.5V=1.517V) 1 .5 M_ 0 4 1 0 _0 6 R B0 54 0 S2
PU3
P R 95 10 _ 0 6 Z3801 3 7 C DD R1 .5 V_ PW RG D
VD DQS PGD DD R1 .5 V_P W RG D 1 6
Ra VIN
PC 58 PC 59 PC 5 0
PR 9 7 Z3802 2 6 6
T ON 0 0
_
1 0 0p _ 5 0V _N P O_ 0 4 1 K_ 1 %_ 0 4 1 u_ 2 5 V_ 08 1 u _ 25 V_ 0 8 _
V
5 V
5
PR9 1 Y
6 Y
Z3803 *1 5 m il_ s ho rt_ 0 6 _ _
FB V V
8 2 4 Z3812 Z3813 0 0
RE F BST 3 5 4 5
+ PC1 5 8 5 _
u 5 _
u
PR8 6 Z3805 9 PC 4 5 5 6 7 8
1
C 1
. 1
C
1
.
CO MP PR8 9 0 .1 u _5 0 V_ Y5 V_ 0 6 PQ 37 15 u _ 25 V_ 6 .3 *4 .5 _E LN A P 0 P 0
10 _ 0 6 PC4 3 *1 5 m il_ s ho rt_ 0 6
PR8 5 Rb 2 3 Z3814 Z 3 8 15 4 M DS2 6 5 9
10 _ 0 6
PR 9 0
1 0 0 K_1 % _ 0 4
* 0. 1u _ 1 0V_ X7 R_ 0 4
4
0
Z3806 1 0
VT T S
DH
PR 87
1 2 3
1.5V
Z 3 80 8 _ 5 2 1 Z3816
s
R Z3807 OCP V D DQ
7 VC CA IL IM
PL6 2 .5 UH _ 1 0* 10 * 5 PJ 9
PC4 0
PC 37
PR8 0 9
4
C
X
_
V
0
PC 5 1
LX
7.1 5 K_ 1 %_ 0 4
2 2 Z3817 8A 1 2
1 .5 V
m
P 5
1u _ 2 5V _0 8 _ 1 9 Z3818 PQ3 5 PQ3 6 OP EN_ 8 A
*0 .0 6 8u _ 5 0V _0 6 *1 5m il_s h o rt_ 06 p DL 5 6 7 8 5 6 7 8
0 1 u _ 25 V_ 0 8 *M DS2 6 55 9
a
.
VTT_MEM
0 C C
VSSA 0 4 MD S2 65 5 7 5 + PC1 4 3 PC 1 50 P C1 5 2
1 *
4
VSSA
r
4 4 PD 1 5 1 6
. +
6
C
*
PJ 20 Z3809 1 4 20 PD 1 6 *2 20 u _ 2 .5V_ B_ A 0 .0 1 u _5 0 V_ X7 R _0 4
1.5A P 6 0 .1u _ 5 0V _Y 5 V_0 6
Sheet 33 of 42 2 1 15 VT T V DD P 1 5V 1 2 3 1 2 3 .
g
* SK3 4 SA _ 6
VT T _ MEM 6 6 VT T
0 0 PC3 9 H V
_ _ 6 12 S
A A 5
.
a
O PEN_ 2 A R
R
0 0
2
5 5 _ V DD Q V D DP 2 4
Power 1.5V/0.75V,
13
i
X X R 1u _ 2 5V_ 0 8 1 _
u
3 V D DP 2 25
*
PC 15 5 PR7 9 _ 4 _ 5 5 D 0
1
3
V 3 V 3 X PC3 8 P GND 2 6
0
+ 1 18 O
P
C 3
. C 3
. C _ u
C
S 5
P P P V
D
6 6 EN /PSV P GND 1 16 C
_
* 22 0 u _2 .5 V_ B_ A PR1 8 1
6 3
_ 3
1.8VS _ . P GND 1
. 6
u u 11 17
3
*2 0 K_ 1 %_ 0 4 0 0 6 V
1u _ 2 5 V_0 8 * 15 m _
il s h ort_ 0 6
1 1 _
u VT T EN P GND 2 VSSA
_
*
0
X
c
1
5
SC 48 6
i
R
_
1 .5 VEN
0
t
P R 92 47 K _ 1 % _ 04 6
5V
3
a P R9 3 1 0 0 K_ 1 % _ 0 4 Z 38 1 9 G
D
PQ 10 B
5 M TD N7 0 0 2Z H S6 R
D
PQ9
P C4 8
m
6 S G 0 .1 u _ 50 V_ Y5 V_ 0 6
D 1 4 *M TN 7 00 2 Z HS 3
e 1 6 ,2 8 S US C # G
S
2
PJ1 1
4 0m il
S
DDR3 VDDQ --> 1.5V ( V POWER)

2
1
3 0,3 1 DD _ ON #
PQ1 0 A
h
c MT DN 7 00 2 Z HS6 R
P R 83 1 0 0 K _1 % _ 0 4 330uF*3 , 10uF*6
S
5V
. 4 ,1 6 ,3 4 1 .1 VS_ VT T _P W RG D
P R 82 * 1 00 K _ 1 % _0 4 VT TEN VTT-->0.75V ( VS POWER)
B
P R 18 2 1 0 0 _1 % _ 0 4 6
VT T_ M EM
3
D S USB G
D
2 PQ 6A
PC 41
0 .1 u_ 5 0 V_ Y5 V_ 06
10uF*3, 1uF*4
PQ 6 B S
SU SB G 5 M T DN 70 0 2 Z HS6 R 1 MT D N7 0 02 Z H S6 R
31 SUSB
S
4
ON
3 .3 V
5V
1 0K _0 4
3.3V
PC1 5 7 1.8VS
PR1 8 3 2A PU7 1u _ 2 5V _0 8
5 6
9 VIN
VIN
VCN TL 3A VS1 .8 PJ 1 0
1 .8 VS
1 .8 VS_ PW RG D 7 4 1 2
1 6 1 .8 VS_ PW RG D POK V OUT
6 6 4
3 0
0 0 OP EN_ 3 A
8 V OUT _ _ _
P R 81 1 0 K _04 EN 1.8 VS PR1 7 9 R
R
R
5V EN 5 5 7
1.2 7 K_ 1 %_ 0 4 X X X
1 2 _ _ _
GND VF B V V V
3 3 0
D . . 1
P C3 2 PC1 4 8 6 6
_ _ _
u
u u 1
7 ,2 0 1 .8V S
PQ 5 AX6610 0 0 .
P R 84 6 2K _ 1 % _0 4 G * 1 u_ 2 5 V_ 08 PC1 4 9 PC 1 56 1 1 0 1 2 ,30 ,3 1 ,3 2,3 4 ,3 5 ,36 ,3 7 VIN
31 SU SB 2 1,2 4 ,3 0 ,31 , 3 4 5V
S M T N7 00 2 Z H S3 6 82 p _ 50 V_ N PO_ 0 4 3 ,4, 12 ,1 4 ,15 ,1 6 ,1 8,1 9 ,2 0 ,21 ,2 3 ,24 ,2 5 ,2 9,3 0 ,3 1 ,34 ,3 5 3 .3V
6 0
0 _ 5 4 6
4,9 ,1 0 ,11 ,2 1 ,2 3,2 7 ,2 9 ,31 ,3 6 1 .5V
PC4 2 _ R PR1 8 0 4 4 4
V 5 1K_ 1 % _ 04 1 1 1 1 0 ,1 1 VT T_ M EM
5 X C C C
0.1 u _ 50 V_ Y 5V_ 0 6 Y _ P P P
_ V
V 3
.
0
5 6
_ _
u u
1 0
. 1
0 GS7113 6-02- 07113- 320
AX6610 6- 02-06610-320
APL5930KC 6- 02- 05930-420
B - 34 Pow er 1.5V/0.75V, 1.8VS
Schematic Diagrams
Power 1.1VS_VTT
5V

http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf OCP A
PD 9
VIN 84/96
PR 99 RB 05 4 0 S2 1. 1VS VTT=0. 75 X (1+
PR101 / PR102)
6 .4 9K _1 % _ 04
C
PC 16 4
+
5 6 7 8 5 6 7 8
PQ 3 9 PQ 38 1 5u _ 2 5V _6 .3 *4 .5 _ ELN A
4
2 3 1
M DS2 6 59
4
* IRF 7 4 13 Z PBF
2 3 1 VT T_SE NSE 6

1.1VS_VTT
PC6 1
ON PU 5 25A(15A)
1 .1 VS_ VT T_ EN _R 3 4
5 6 SC 41 2 A 0 .1u _ 5 0V _Y 5V _0 6
1 1 1 1 VT T 1.1 VS 1 .1VS _VT T
PL 7 PJ2 1
3. 3V P R 10 3 1 0 K _0 4 M
0 1 H 0 .5 6U H_ 1 0* 1 0* 4.1
12 I G G
D
1 1 2
EN L LX
I
11 2 9 9
. *OP EN-1 2 mm .
4,1 6 ,3 3 1.1 VS_ VT T _PW RGD PG D B ST 5
*
5
*
6 6
10 3 5 6 7 8 5 6 7 8 C . .
PQ4 2 PQ4 3 6
*
6
*
VO UT VC C MD S26 5 5 MD S26 5 5 PD 19 6 6
. .
FB 9 4 4 4 6
_ 6
FB DL _
N D 2 3 1 2 3 1
SK3 4 SA V
5
V
5
B
0 1 T N 17 . .
2 2
PAD A
D D R G _ _
u
0
u
0
.
S
8 7 6 5
6 PC6 8 6
P C6 0 5 5
+ 0.1 u _ 50 V_ Y5 V_ 0 6 + c
1 u _ 25 V_ 0 8
1
5
1
9
5
1
Sheet 34 of 42 h
Power 1.1VS_VTT
C C
e
P P
PR 10 5 P R1 01 PC6 5
m
0 _ 04 1 0 K_ 1% _ 0 4 *2 0 p_ 5 0 V_ NPO_ 0 4 a
P R1 06 * 9 0 . 9K _1% _04
5V
t
i
c
PC 66
P R1 02 D
0 .1 u_ 1 0 V_X7 R_ 0 4
2 4 K_ 1% _ 0 4
i
a
g
r
a
(1.1VS_VTT=1.067V)
m
s
PJ 1 4
1 2
4 0m il PJ 1 3
P R 10 7 1 0 K _0 4 1 2 1 .1V S_V TT _ EN_ R
5V
4 0 m il
D 12 PR1 0 0
3
SC D3 4 0 *1 0 0K_ 1 % _0 4
C A D
PQ 1 2B PR1 0 4
G 5 * 2N 7 00 2 KDW
6 S *1 0K _0 4
1 4
D PQ1 2 A
PR 1 08
*2 N7 0 02 KD W PJ 1 2
G 2
1 6 1 .1VS _VT T _ EN 4 0m il
S
1 2
1 0 0K _1 % _ 04
PC6 7
*1 u_ 2 5 V_ 08
2 ,4,6 ,7 ,1 4 ,15 ,1 6 ,19 ,2 0 ,21 ,3 5 ,3 6 1 .1 VS_ VT T

3 ,4 ,1 2 ,14 ,1 5 ,16 ,1 8 ,19 ,2 0 ,2 1,2 3 ,2 4,2 5 ,2 9,3 0 ,3 1, 33 ,3 5 3.3 V
2 1,2 4 ,3 0, 31 ,3 3 5V
1 2 ,3 0,3 1 ,3 2,3 3 ,3 5, 36 ,3 7 VIN
Power 1.1VS_VTT B - 35
Schematic Diagrams
Power VGFX_Core
1 .1VS_ VTT
3.3 V
PR 71 10 K_0 4
7 DF GT _VID _0
P J4
2
4 0 m il
1
0
4 4 4 4 4 4
4 0
0 0 0
_ _ _ _ 0 _ 0
K K _ K
_
85/96
7 DF GT _VID _1 K
1 1 1 K
1 1
K 1 K
* * 1 *
7 DF GT _VID _2 * * *
7 DF GT _VID _3
7 DF GT _VID _4
7 DF GT _VID _5
8/18/2019 7 DF GT _VID _6
clevo+6-71-w24h0-d02a.unlocked.pdf 7
R
9 8 7 5 4
0 6 6 6 6
R R
6 6 6
R R R R
P P P P P P P
DF GT _VID_ 0
DF GT _VID_ 1
DF GT _VID_ 2
DF GT _VID_ 3
P J5 4 0m i l DF GT _VID_ 4
P R 72 1 K _0 4 2 1 DF GT _VR_ EN DF GT _VID_ 5
3.3 VS DF GT _VID_ 6
4 4 4 4 4 4
3.3VS 0 0
_ _ _ _
0 0 4
0 0 0
_ _
7 DF GT _VR _EN 5VS K K K K _ K
K
K
1 1 1 1 1 1 1
* * * *
s
PR4 2 PR4 8
VIN
4 70 _ 04 1 0 K_ 0 4 8 7 6 4 3
m
PR4 1 9 5 5
5 5 5 5 5 5
R R R R R
R
R
1.1VS_VTT 8
6 4
8 8 P P P P P
P
P
1 0_ 06
a
0 0 0
_ 0
_ 0
_ _ _
R V R R
r
5 R 5 5
X 5 7 X X
Y X
_ _ _ _
Sheet 35 of 42
_
V V V V
g
PR6 2 V
5 0 0 5 5
*10 K_ 1% _0 4 VGF X_ VOR E_ PG PC1 1 6
2
_
u
5
_
u
5
_
u
2
_
u
2
_
u
VGFX_CORE
a
7 1 7 7
. . 1 . .
0
i Power VGFX_Core 7 GF X_IMO N

1 u_ 6 .3V_ X5 R_ 04
5 6 7 8
4 0 .
0
*
4 4
*
15A(7A)
D 3.3VS PQ18 0 3 2

2 1 0 9 7 5 PR21 7 4 MDS2 65 9 8 7 5 8
3 3 3 2 8 2
2 6 2
2
C
C C
C
9
C
(0.7V~1.77V)
0_ 04 1 2 3 P P P P P
c
N 0
1
2
3
4 5 6
G ND_ 32 1 1 VGF X_CO RE
i
E D D D D D D D
I I I I I I I
24 2
t
PR 34 V V V V V V V PR38 PC1 4 GPU
PC 18 PR6 1 1 VCC 0 _ 06 0.2 2 u_ 50 V_ 06 PJ 19
*1 0K_ 0 4 PWR GD 23
a
BST O PEN _8 A
0.1 u_ 5 0V_ Y5 V_0 6 4.7 K_1 %_ 0 4 2 1
IMON 22 3 2 11 _D RVH PL 3
3 21 1_ CL KEN# 3 DRV H 1 .0 UH _1 0* 10 *4 .5
m
CLKEN # 21 3 2 11 _SW 1 2
4 PU2 SW
4
e
F BR TN 20 9
. 0
4
5 P V CC 5VS 5
*
_ 0
_
PC 21 22 0p _ 50 V_N PO_ 04 PR 16 5 6 R
5 R
FB 19
h
PC 19 5 ADP3 21 1 3 2 11 _D RVL . 7
6 X X
PC2 3 6 DR V L PC 19 4 * 2.2 _0 6 *
6
_
_
COMP . V
4
0 6 0 V
0
18
c
_ PC1 9 7 PGND 5 6 7 8 5 6 7 8 C _ 1
_ 5
4 7p _ 50 V_N PO_0 4 2 .2 u_ 16 V_ X5 R_ 06 V _
R 5 u u
7 PR43 20 K_1% _04 GPU 17 PQ 23 PQ22 PD1 2 . 1
. 1
S
X AGND 2 0 0
_ 8 4 4 MDS2 65 5 _ * .
.
V ILIM P u 0
0 PR 50 33 MDS2 65 5 SK3 4SA 0 *
5 P E F M
AGND 1 2 3 1 2 3 6
_ 1K_ 1% _ 04 47 0p _ 50 V_X7 R_0 4 E B O PC 12 5 5 +
p F N
M M I R F C A
0 E P T S S
B
0 R A L S 4 3
PR4 9 I R R R L C C C 4
0 0 3 3
1 _ 2 1 1
0 _0 4 PR2 1 8 9 0 1 2
R 3
3 4 5 6 7 1 C C
1 1 1 1 1 1 1 GN D_3 2 11 P P
5VS X
_
C
P
GN D_3 2 11 V
7 .5K_ 1% _ 04 0
5
_
p
0
GPU App. P P
Place RTH1 close to 0
2
PR 21 9 P RT 1 2
M
O
PR 22 0 PR2 2 1 PR2 2 2 M
O
M
O
10 0 K_ NT C_ 06 _ B inductor on the same layer *
0 CPU *0_ 0 4 C

S 4 6
C C
S
2 1
4 0 0 S
C 0 _ _ C C
_ _ _ _
1 % % % 1 1
1 1 1 1
1 GPU 2 1
_
_ _ 1
2 2
3
K
K
0
K
2
3 3 PR1 67
6
. 0 3 1 10 K_1 %_ 0 6
0
8 2 3
GND _3 21 1
GN D_3 2 11 PR 22 3 PC2 0 PC 12 7 PR3 6

GPUVCC SEN SE 7 GND_ 3 21 1
6
1 50 0 p_ 5 0V_ 04 2 2 0p _ 50 V_N PO _0 4 1 80 K_1 %_ 0 4 PR24 0
G ND_ 32 1 1 0 16 0K_ 1 %_ 04
_
PR2 2 4 1 00_ 1%_0 4
GPU %
1
_ distributeevenlybetw eenN sideandSsi de,
K
2
PR2 2 5 1 00_ 1%_0 4 2 preferably onsecondary side.
4
P R2 2 6 1 K_ 1% _0 4
VIN
G P UV S S S E NS E 7
PC19 6 PC 11 2
1 00 0p _ 50 V_X7 R_ 04 1 0 00 p_ 5 0V_ X7 R_ 04
GND _3 21 1GND_ 3 21 1
2 ,4 ,6 ,7,1 4,1 5 , 16 ,19 ,2 0,2 1,3 4 ,36 1.1 VS_VT T
3,4 ,12 ,14 ,1 5,1 6,1 8 , 19 ,20 ,2 1,2 3,2 4 ,25 ,29 ,3 0,3 1,3 3 ,34 3.3 V
4,9 ,1 0,1 1,2 1 ,23 ,27 ,2 9,3 1,3 3 ,36 1.5 V
7 VG F X_ COR E
1 2,3 0 ,31 ,32 ,3 3,3 4,3 6 ,37 VIN
2 ,1 3,1 7,2 0 ,21 ,26 , 2 7,3 0,3 1 ,36 5VS
2 ,10 ,11 ,1 2,1 3,1 4 , 15 ,16 ,17 ,1 8,1 9,2 0 ,21 ,23 ,2 4,2 5,2 6 ,27 ,28 ,2 9,3 0,3 1 ,36 3.3 VS
B - 36 Power VGFX_Core
Schematic Diagrams
V-Core
VIN
FOR EMI

PC1 97
*1 n_ 5 0V_ 0 4
SG ND 2 A
N
L
E
_
A
N
L
E 6
A
N
L
6 E
_
8
6
0
_
6
6 0
_
0
_
6
6 0
_
0
_
6
6 0
_
6
0
_
6
0
_
L
5
1
3
R
86/96
_ 0 0 0
5 5 V V
_ 5
_ 0 V V V V V V A
PR2 2 7 . . _ . _ 5 5 5
V 4
5 Y 5 Y 5 Y 5 5 C
4 4
* V
R V Y
*4 7 K_0 4 PC1 9 8 * 5 5 *
3 5 5 Y _ Y
_ _ Y
_ _ _ Y _
3 3 Y . X _ _ u
1 u_ 2 5V_ 0 8 . . Y Y V V V V V V 0
6 6 _ _ 6 _ _ V
0 0 0 0 0 0 0 V 3
0
CS_ PH1 _ _ V V _ V 5 5 5 5 3
PR 17 3 2 00 K_1% _06 V V 0 0 V 5 V
0 5
_ _ 5
_ _ 5
_ _ _ 5
_ *
5 5 2 u u
CS_ PH2 PR 16 8 2 00 K_1% _06 5 5 5 5 u u u u u u
2 2 u_ _ 2 _
u _ 1 1
. 1 1
. 1
. 1
. 1
. 1
VIN _ _ u _ u . . .
u u 1
. 1
. u 7
. 1 0 0 0 0 0 0 0 0 +
5 5 5 .
0 0 4 0
P R 2 41 1 6 2K _ 1% _0 6 1 1 1 *
* *
P R 2 28 1 K _ 04 + +
+ 0
RT1cl ose to PL6 PQ2 9 PQ 34 0 2 3 5 5 9 7 6
7 7 4
1 8 7 3 2 C 2 1 9 7
PC 13 6 PC 19 9 1 0 00p _5 0V_X7R _0 4 MDU 26 5 7 * IRF H7 92 3 C C P C C C C C
D D 7 8 1 1 8 8 P P P P P C P P
RT 3 PR 24 2 1 5 00 p _5 0V_ 0 4 C C 8 8 P
P 0
P 1 3 9 2
10 0 K_N TC _0 6_ B 7 3 .2K_ 1 %_ 0 4 C C C 1
C P P P C
2
PC1 38 SGN D2 G G P P
4 70 p_ 5 0V_ X7R _0 4 4 6 4 4
0 0 0 0 S S
_ _ _ _
% % %
% 1
1 1 1
_ _
P P _ K
_ K K HDR1
VCORE
M
M
F M
K 2 5 6
SG N D2 VCO RE
3 .3 VS 3 .3VS PR1 75 E 0 . .
O
U O 8 6 0
C R C
S 7 8
6 1 4
1 .6 9 K_1 % _0 4 S
S
S S
PL5
0 .36 UH _1 2 .9 *1 4 *3 .8
C
C
C C
9 0 1 2
24A
2 3 3 3
2 2 2 2 2 9
. .
R R R R 4
P P P P D 1 * A 5
* A A
PU1 PC2 0 0 PR1 7 1 3 _ _
4 1 0 8 7 4 3 5 VS D C H . _ 6
. V V
PR2 PR4 PQ2 8 5 .1_ 0 6
2 2 2 2 2 1 1 1 6
3 2 9 1 5
1 1 1 ADP3212 6 G MD U2 65 4 PQ3 3 PD 14
P
_ PR1 72
6 V
* _ 6
*
_ _
B
S 3 V 6 V V
0 . 5 5
_ G 6 5 . . .
3 K_1 % _0 4 3K_ 1 %_ 0 4 3 3 # M T F
P V MDU 26 54 C .
_ 2
6
2 2
3 I
M
P
U F E R M S _
B M
D L M E
F W I O S R
N
E
M P
I A R
R
PR9 0
5 S
SK3 4 SA 10 _ 06 4
0
V
3
_
u
V
_
u
_
u
.
VR _ON 1 I 36 _ _ . 0 5
. 0 0
EN W P
O S L
C S L R BST1
2_ 0 6 BST 1 u A
PC1 3 1
%
6 3
_ 2 3
3 3
3
S
4 ,1 6 DEL AY_ PW RG D 2 S C C
S
35 2
2
1 3
u * _
u *
3 PW RGD C
D RVH1 34 . _ 0 0
6 IMON PR5 0 2 20 p _5 0 V_NPO _0 4 0
0
2
6
c
4 IMON SW 1 33 10 0 _0 6 CS_PH 1 VIN 1
2+ + 5
+ + +
PC2 9
2 CL KEN# 5
6
7
CL KEN#
F BRT N
FB
SW F B1
PVC C
DR VL1
32
31
30 PR2 33
5 VS
A
CSR EF
5
3
7
3 9
3
1
2 4
4
Sheet 36 of 42 h
COM P PGN D N 1 1
8 8 1 1 1
V-Core
10 0 0p _ 50 V_X7 R_ 04 PC9 3 PC 86 PC 81 T RDET # 8
TR DET # DR VL2
29 10 0 _0 6 PC 20 1 PQ 26 PQ 31 0
_
L
E
0
_
C C C C C
e
1 5 0p _ NPO_ 5 0V_1042 p_ 5 0V_ NPO_ 0 4 5VS 9 28 CS_ PH2 M DU2 6 57 * IRF H7 9 23 6
0 R _ R P P P P P
VARF R SW F B2 27 8 D D 5 6
_ 5 . 5
SW 2 26
0
_ V X 4
* X 7
1
m
SG N D2 0.1 u_ 5 0V_ Y5 V_ 06 PC 20 2 5 _ _
D RVH2 R
5 Y V 3
. V R
1 5 0p _ NPO _ 5 0V_ 04 10 25 G G _ 5 6 5 PR1 78 P
VRT T BST2 X
T T SN S 1 1 P _ V 2 _ 2
L 0 _ V _
12 TT SNS S 6 2
0 # 5 4 3 1 0
V
5 S S 5
_
u +
7
5
2
u
7 10 _ 06
a
N P PR 12 6 AGND C
1 R I D D D D D D D 2 u .
4 _ .
4
S
PR7 7 S
PR12 1 49 C
H
H P
S I I I I I I I _
u 1
. * 6 u * 2 t
AGND V
P
P D
P V V V V V V V 5 5 H
R 5.4 9 K_1 % _0 4 R 1 .6 K_1 % _0 4 39 .2K_ 1 %_ 0 4 7
. 9 0 9
2 0 1 5
0 P
1
4
HD R2 C 1 1 _
i
SG ND2
7 8 9 0 1 2 3 4 5 6 7 8
3 3 3 4 4 4 4 4 4 4 4 4 P C
P
C
P
C
P
S
C PL 4 24A c
5VS 0 .3 6U H_ 12 .9* 14 *3 .8
4 H_ PRO CHO T#
D
PC8 2 PR1 7 0
D D
PR2 1 6 PR2 43
D C
5 .1_ 0 6
i
a
PQ 47 SGN D2 2 _0 6 0 .22 u _5 0 V_0 6 PQ2 7
M TN 70 02 Z HS3 G 1 0_ 0 6 BST2 G MDU 26 54 PQ 32 PD 13
G M DU2 6 54
S S
SK3 4 SA PC1 3 0
S
1 .1VS_ VT T
1 .5V 1 .5VS A
g
r
PC6 2 20 p _5 0 V_NPO _0 4 a
1 u_ 2 5V_ 08
4 4
4 4 4 4 0
4 4
0 0
_ PR2 34
m
0 0 0 4 0 _
0 _0 4
_ _ 0
_ K _ 0 % %
SG N D2 K K _ _ K _ 1 1 RS P
1 1 1 K K 1 K _ _ VCC_ SENSE 6
1 *
1 *
1 9 9
* 4 4
6
s
6
*
PC 20 4
P R19 0_ 0 4
6 PM _D PR SLPVR * 10 0 0p _5 0 V_X7 R_ 04 PR2 35
RS N 0 _0 4
6 P S I# PR6 0_ 0 4 VSS_SEN SE 6
6 7 8 9 0 1 2 4 5
2 2 2 2 3 3 3 5
1
5
1
R R R R R R R R R
P P P P P P P
P P
6 H _VID 0 2
PR 23 6
PR2 0 6 H _VID 1 PJ 1
6 H _VID 2
*R_ 0 4 6 H _VID 3 10 0 _1 % _0 4
4 0m il
6 H _VID 4 1
6 H _VID 5
6 H _VID 6
4 4 4 4
0 0 4 4 0 4
0
_ _ _ 0 0 0
_ _ _ _
K K K K K K K
1 1 1 1 1 1 1
* * * *
5 VS PR2 37
5 VS 0_ 0 4
PR 14 3 1 0 K _0 4 VR_ ON
3.3 VS
PR 23 8
3 4 5 6 7 8 3
PR 16 9 1 1 1 1 1 1 3 PR 15 6 PQ2 0B SG ND 2
5 .1 K_1 % _0 4 R R R R R R R 3
P P P P P P P
7 .3 2K_ 1 %_ 0 4 1 0 0K_ 0 4 MT DN7 0 02 Z HS6 R D
PR1 19
T TSN S T RDET # G 5
PQ 20 A S *1 0K_ 04
1 6 2 4
R T2 PC 20 3
PR 23 9 M TD N7 00 2Z H S6R D PJ1 8
1 0 0K_ NT C_ 06 _ B 0 .0 1u _5 0 V_X7 R_ 04 2 4 0 mil 4,9 ,1 0,1 1 ,21 ,2 3,2 7,2290 ,31
,23,3,331 .5 VS
1 .5 V
2 * R_ 04 1 6, 2 8 VCOR E_ ON G 1 2,4 ,6,7 ,1 4,1 5 ,16 ,1 9,2 0,2 1 ,34 ,3 5 1 .1 VS _ V T T
S 6 VC O RE
1
1 2,3 0 ,31 ,3 2,3 3,3 4 ,35 ,3 7 VIN
2 ,13 ,1 7,2 0 ,21 ,2 6,2 7,3 0 ,31 , 3 5 5 VS
2,1 0 ,11 ,12 ,1 3,1 4 ,15 ,1 6,1 7,1 8 ,19 ,2 0,2 1 , 23 ,24 ,2 5,2 6 ,27 ,2 8,2 9,3 0 ,31 ,3 5 3 .3 VS
PC 10 8
* 0.1 u _1 0 V_ X5R _0 4
V-Core B - 37
Schematic Diagrams
AC_IN, Charg er

CHARGER #Charge Current 3.0A
http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf VIN
VA
4
1
P Q2 4
P 20 0 3E VG
5
#Charge Voltage1 2.6V
#Total Power 60W 87/96
2 6
JAC K1 3 7
50 9 3 2-0 0 3 01 -0 0 1 PL 1 VA PQ 17 8
HC B45 3 2 KF -8 00 T 6 0 P2 0 03 EVG PQ2 5 A
8 PR 1 14 AP6 90 1 GSM PL 2 PR1 4 6 V_B AT
1 7 3 2
0 .0 2 _1 % _ 32 4 .7 UH _6 .8 *7 .3 *3 .5 0 .02 _ 1 %_ 3 2
2 6 2 1 7
G ND 1
8/18/2019 G ND 2
PC 7 4
6
PC1 PC 2
6
PR1 1 8 5 1
8
4
0
_
4
0
_ 8 8
6
5 6 8 8 8 8 8 8
0
6
0 0
PR 1 1 30 K_ 1 %_ 0 4 4 0
0 0 0
_
0
0
6
0 8
0 0 0 0 0 0
_ _ _ 4 _ _ _ _ _ _ _ _ _ _ 6
V 0 V R R R R R R R R 0
V V 6 5 V V
5 5 5 1 _ 0 5 5 5 5 5 5 5 5 5 _
Y Y Y 1 % 5 X
_ X Y Y 3 X X X X X X V
_ _ _ 1 0K_ 0 4 R 1 _
u V _ _ _
PR1 5 7 _ _ _ _ _ _ 5
V V _ V V V V V V V Y
0 V 0 P K 3 5 5 V
0 V
0 5 5 5 5 5 5 _
5 0
5 5 0 3
. 2 2 5 5 2 2 2 2 2 2 V
_
_ _
PR1 1 7 0
_ _ 0_ 0 4 PQ2 5 B _ _ _ _ _ _ 0
u u 2 0
* 2 1 u u _ _ 4 u u u u u u 5
u 7 7 u u AP6 90 1 GSM 7 7 7
1 1 1 6 6 . 7 1 1 . . 7 7 7 _
.
0 .
0 .
0 1 0K_ 1 % _0 4 7
C 1
R
1 1
R
4 2
1
.4 7
1
.
0 6
1
.
0 1
1
4 0
2
4 8
1
.4 9
1
.4 0
1
.4 5
1
.4 4
1
u
1
.
P P P C C C C 1 1 1 1 1 1 1 0
P P P P C C C C C C C
P P P P P P P
4
0
_
s
%
1 P C1 5 0 .1 u_ 50 V _Y 5V _ 06
_
K
0 PC 10 7 PR1 44 4
0 PD 3 0
m
1 _
V_ BAT 1 u _2 5 V_ 08 *1 0m il_s h or t_0 4 0
C A *
PIN 25th
a
5
1
1
FOR 2S CONNECTT OGND
r
R R B0 54 0 S2
PC 10 3 PC 1 04 PC1 1 3 P FOR 3S CONNECTN.C.
g Sheet 37 of 42 0 .1 u_ 5 0V _Y 5V _0 6 0 .1 u _5 0 V_ Y5 V_ 06 0 .1 u _5 0 V_ Y5 V_ 06 2

1
R
FOR 4S CONNECTT OVREFPIN
a
P
P R1 1 *0 _ 0 4
i AC_IN, Charg er VA
2 0 9 8 7 6 5
D
1 3 2 2 2 2 2
3 3 VA
VIN PU 6
2 B 1 X B
2 D
- L V - S
1 L
C T T N
L
L
24 PC 9 9 0 . 1u _ 5 0V _ Y 5V _ 06
c
VC C T U G E VIN 2 3
2 C U CT L 1 V DD 3
O P
i
3 -I N C1 O C C TL 1 22
PC 12 4 PC 1 23 PC1 2 2 PC 1 21
t
4 + INC 1 G ND 21 R 17 1 0 K _ 04
5 AC IN VR EF 2 0
0.1 u _ 50 V_ Y5 V_ 0 6 0 .1 u _5 0 V_ Y5 V_ 06 0.1 u _ 50 V_ Y5 V_ 0 6 0 .1 u _5 0 V_ Y5 V_ 06 TRER MAL PAD
6 AC OK RT 1 9 C
a 7
8
-I N E 3
CO MP1 E U
1 2
T T

C C
N
2
3
J M
C
M BAT T
O
S
A D J 1 1 C C 2 2 2 P P ADJ 3 1 7
18
33
VOL T _SEL
6
0
_
6
0
_
V
5
S G ND6
4
PR1 4 7 S MC_ BAT AC
A
m
N U
I
I N D O 0 4 9.9 K_ 1 %_ 0 4 D9
- O O + I CS G ND
- A C V
5
Y
_ _ BAV9 9R E CT IF IER
V
Y 0 %
1 C
e
PR1 6 4 M B3 9A1 3 2 9 1
1 2 3 4 5 6
0 1 1 1 1 1 1
_
5 _
S G N D6 4
0 V _ K S MD_ BAT AC
0 u
6 _ 5 1 2
. A
V D D3 TOTAL 6 1 0K_ 1 % _0 4 PC9 4 _ . CHARGE
h
%
1 u 0 9
3
1 1 0 0p _ 5 0V_ N PO_ 0 4 PR 1 40 PR1 4 9 D8
POWER R _
P K
1
.
0
CURRENT
0
1 K_1 % _ 04 BAV9 9R E CT IF IER
ADJ PC1 2 6 1 K_1 % _ 04 ADJ C
c
1
PR 15 8 B AT_ D ET AC
0 3 6 A
S
0 .01 u _ 50 V_ X7R _ 04 PC1 0 0 *2 2p _5 0V_ NPO _04 1 1 3
1 0 K_0 4 PC9 6 D7
.
C C 1
P P R
1 0 00 p _ 50 V_ X7R _ 04 PR 1 45 P PR1 5 2 BAV9 9R E CT IF IER
4
0 S G ND 6
A C _I N # 28 _
B
3 2 2K_ 1 % _0 4 SGN D6 S G N D6 S G N D6 2 2K_ 1 % _0 4 C
C 6
%
1 1 PC1 0 2 AC
C A B R _ 28 BAT _ VOL T A
PQ 30 P K 1 0 00 p _ 50 V_ X7R _ 04 PR 1 50
VA 0
2 D6
SG ND 6
PD1 1 PC 1 17 D TC 11 4 EUA 1 0 K_ 1% _ 0 4 SGN D6 BAV9 9R E CT IF IER
UD Z 1 6B
E
* 0.1 u _ 50 V_ Y5 V_ 0 6
V_ BAT
0.5V/1A TO T AL_ C UR
PIN 17th CONNECT
0.5V/1A CU R_ S E NS E TOBAT CONN.
E4120
PR1 3 8
5
1 02 K_ 1 %_ 0 4
PR 2 3 28 SMC _ BAT 4
28 SMD _ BAT 3
VOL T _ SEL
S YS5 V SYS5 V 28 BAT_ D ET 2
PQ2 1 PR 15 3 1
D J BAT TA2
AO3 4 0 9 3 0 0K _1 % _ 04 2 M_ 1 % _0 4
V _BAT S D BAT _ VOL T _ R PR1 3 9 * BT D-0 5 TI1 G
PR 14 8 PR 1 41 G
7 6.8 K_ 1 % _0 4
V C HG _ S E L 2 8 E5120Q
P R2 1 1 0 0K_ 1 % _0 4 1 0 0 K_1 % _ 04 S PQ2
G 5
2 0 0 K_ 1% _ 0 4 PQ1 9 A MT N7 0 02 Z H S3
PR1 5 1 PC1 0 9 CT L 1
MT DN 7 00 2 Z HS6 R 6 3 4
60 .4 K_ 1% _ 0 4 0 .1u _ 5 0V_ Y 5V_ 0 6 D D 3
2
P R2 2 PQ 1 9B
G 2 G 5 M TD N7 0 0 2Z H S6 R 1
* 1 0m _
il s h ort _0 4 28 C HG_ EN
S S
6- 21-D34B0- 105 J BAT TA1
1 1 4 B TD -0 5T C1 B
D
PJ 17
PQ 1 O PEN- 1m m P R 13 5 * 1 5 m i l _ sh o rt _ 06
2
G
SYS 5V
S
M T N7 00 2 Z HS 3 S G ND6
SY S5 V 3 1,3 2
VD D3 1 4 ,2 3, 25 ,2 8, 29 ,3 1 ,32
VA 31
VIN 1 2 ,3 0, 31 ,3 2, 33 ,3 4 ,35 ,3 6
B - 38 AC_IN, Charger
Schematic Diagrams
Click Board
CLICK BOARD

CVDD3 CVDD3 CVDD3 CVDD3
CR360 CR359 CR361 CR358

CC2 CC1 CC3
C5VS 0.1u_16V_Y5V_04 C5VS *0.1u_16V_Y5V_04 CVDD3 *0.1u_16V_Y5V_04 220_04 220_04 POWER ON 220_04 220_04
BAT LED
1
1 3
LED 1 3
CD27 CD26
CGND CGND CGND 2
Y G Y G
CJ_TP2 CJ_TP3 S S
CJ_TP1 RY-SP155HYYG4 RY-SP155HYYG4
1 1 1 2 4 2 4
B
CTP_DATA CTP_CLK CLED_PWR#
2 CTP_CLK 2 CTP_DATA 2 CLED_ACI N# .
3 3 3
CTPBUTTON_L CLED_BAT_FULL#
S
4 4 4
CTPBUTTON _R CLED_BAT_CHG#
5 5 c
85201-04051 CLED_PWR# CLED_BAT_FULL#
CGND
6
85201-06051
6
85201-06051 CLED_ACIN# CLED_BAT_CHG#
Sheet 38 of 42 h
Click Board
e
6- 20- 94A50-104 CGND CGND 6- 52- 55002- 04B 6- 52- 55002- 04B m
6- 20- 94AA0-104 6- 52- 55001- 040 6- 52-5 5001-040
6- 20- 94A70-104 6- 21- 91A00-106 6-21- 91A00- 106 6- 52- 55002- 042 6- 52-5 5002-042
6- 21- 91A10-106 6-21- 91A10- 106
a
6- 20- 94A70-104 6-20- 94A70- 104 t
E5120Q i
c
D
i
a
CSW1~4
21 43
g
r
a
LIFT RIGHT LIFT RIGHT m
KEY KEY KEY KEY
CSW1 CSW2 CSW3 CSW4

s
TJG-533-S-T/R TJG-533-S-T/R *TJG-533-S-T/R *TJG-533-S-T/R
1 2 1 2 1 2 1 2
3 4 CTPBUTTON_L 3 4 CTPBUTTON_R 3 4 CTPBUTTON_L 3 4 CTPBUTTON_R
5 6 5 6 5 6 5 6
CGND CGND CGND CGND
6-5 3-3150B- 245 6-53- 3150B- 245 6- 53- 3150B- 245 6- 53- 3150B- 245
6-53- 3050B- 240 6-53- 3050B- 240 6- 53- 3050B- 240 6- 53- 3050B- 240
6-53- 3050B- 241 6-53- 3050B- 241 6- 53- 3050B- 241 6- 53- 3050B- 241
CH3 CH1 CH4 CH2

2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MTH237D91 MTH237D91 MTH237D91 MTH237D91
CGND CGND CGND CGND CGND CGND CGND CGND
Click Board B - 39
Schematic Diagrams
Au di o B oar d/USB

USB PORT
A_U SBVC C AL 5 A _ US B V C C2
HCB1 6 0 8KF -12 1 T 25
60 mil
A_ U SBVCC A_U SBVC C
AU 1 AC 1 AC7
A _5 V 5 6 50mils +
F L G# V O UT 1 1 0 0u _ 6 .3V_ B_ A 0 .1u _ 1 6V_ Y 5V_ 0 4
50mils 2 7
VIN 1 V O UT 2
AC5 AC6 A J_ USB 1
AC9 3 8 A R1 0 * 1 0m i l _ sh o rt _ 04 1
VIN 2 V O UT 3 0. 1u _ 16 V_ Y5 V _ 0 4 0 .1u _ 16 V_ Y5 V_ 0 4 L61 AG ND V+
1 0u _ 1 0V_ Y 5V_ 0 8 4 1 AUSB_ PN2 4 3 AUSB_ PN2 _ R 2
EN # GND D ATA_ L
R T 97 1 5B GS AUSB_ PP2 1 2 AUSB_ PP2 _ R 3
AGN D AG ND AG ND A GND A GND *A W C M2 0 1 2F 2 S-1 6 1T0 3 D ATA_ H
1 2 3 4
4
6-02-09715-920 G ND
D D
N N
D D
A R1 1 * 1 0m i l _ sh o rt _ 04 N
G G N
G G
PI N SW
AP 1 2 3 4
D D
D D
US0 4 03 6 BCA0 8 1
N N N N
G
G G
G 6- 21-B49C0-104
6- 21-B49B0-104
s
AG ND
m TO M/B AUDIO JACK

a
r
g Sheet 39 of 42
a
i Au di o Bo ard/USB AMIC 1-R
AMIC _ SENSE
AL 4 F CM10 05KF -121 T03
5 AJ _ MIC1
4
3 R
D AMIC 1-L AL 6 F CM10 05KF -121 T03 2

6 L
c
1
i
AC1 0 AC 4 2SJ -T 3 51 -S2 3
A_ 5 V
t
AJ_ AU DIO1
10 0 p _5 0 V_ NPO_ 0 4 1 0 0p _ 5 0V_ N P O_ 0 4
MIC IN 6- 20-B2800-106
a A MIC1 -R 1
A MIC1 -L 2
3
BLACK
m
A HE A D P HO N E -R 4 AHP_ SEN SE A_ AUD G
A HE A D P HO N E -L 5
e
A MIC_ SEN SE 6 ASPK_ HP# 5 AJ _ HP1
A SPK_H P# 7 4
8
h
A HP_ SENSE A HE A D P HO NE -R AR3 6 8_ 0 4 AL 2 F CM 10 0 5K F -121 T 03 3 R
A US B _ P N2 9
A US B _ P P 2 10 A HE A D P HO NE -L AR5 6 8_ 0 4 AL 3 F CM 10 0 5K F -121 T 03 2
11 6
c
L
A SPKOU TR + 12 1
S
A SPKOU TR - 13
AR 9 AR 8 AC3 AC2 2SJ -T 3 51 -S2 3
.
14
8 7 21 3 -14 0 0 G *1 K_ 1 %_ 0 4 * 1K_ 1 % _0 4 1 00 p _ 50 V_ NPO _ 04 1 00 p _ 50 V_ NPO _0 4
HEADPHONE
B
A_AU DG AG ND
6- 20- 53A00- 114 BLACK 6-20- B2800-106
A_ AUD G
AL 7
A C1 4 0 . 1u _1 6 V _ Y 5V _ 04 F C M1 0 05 KF -1 2 1T 0 3
A S P K O UT R+ 1 2
A C1 5 0 . 1u _1 6 V _ Y 5V _ 04
A C1 3 0 . 1u _1 6 V _ Y 5V _ 04 AL8 AC 11 AJ _ SPKR1 J_SPK1

F C M1 0 05 KF -1 2 1T 0 3 1 0 0 0p _ 50 V_ X7R _ 04 ASPKO UT R+ _ R
A C1 6 0 . 1u _1 6 V _ Y 5V _ 04 A S P K O UT R- 1 2 ASPKO UT R-_ R 1 2 1
2
85 2 0 4-0 2 00 1
AC8 C4 5 5 PC B F o otp rin t =8 5 2 04 -0 2 R
AGN D A_ AUD G 1 80 p _ 50 V_ NPO _0 4 1 80 p _ 50 V_ NPO _ 04
A R1 * 1 0m i l _ sh ort _ 04
A_ AUD G 6- 20-43150-102
6- 20-43110-102
A H1 AH3
C 5 9D 59 C5 9 D5 9 AH 2 AH4
2 9 2 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
M T H2 76 D 11 1 MTH2 7 6 D1 1 1
A GN D AGN D AG ND AG ND
B - 40 Audi o Board/USB
Schematic Diagrams
Power Swit ch & LED Board

POWER SW & LED & HOT KEY

S _ 3 .3V S S _3 .3 V
POWER
LID SWITCH IC
SWITCH S D2
S _ 3 .3V S S _ 3 .3 V LED C
S R2 *B A V 99 R E CT IF IE R
S _ 3.3 V S S _ 3 .3V S _ 3 .3 V
SJ_SW1 22 0 _ 04
1 20mil S J _ S W 2
SR1 1 0 0 K _ 1% _0 4 AC
2 S M _B TN # 20mil 20mil 20mil Z4301 S U1
3 S W E B _W W W # 1 1 2 S LI D_ S W #
4 S W E B _E M A IL # 2 S M _B T N # S C6 VCC OU T
5 3 D A
S L ID_ S W # SWEB_WWW# N
6 4 S W E B _ E M A IL #
A A
*0 .1 u _1 0 V _ X7 R_ 0 4 SC2 G
S C1
7 S M GN D 5
SA P _ O N S L ID _ S W # M H2 4 8- A LF A - E S O
B
8 6 S D3 SD1
3
0 .1 u _1 6 V _ Y 5 V _0 4 *1 00 p _ 50 V _ NP O _ 04
9 S M GN D 7 SAP_ON S MG ND .
S _ V IN * HT -1 5 0N B -DT S MG ND S M GND
10 8 H T-1 5 0N B -DT
S
S M GN D S MG ND c
* 5 05 0 0-0 1 0 41 -0 0 1L 8 8 48 6 -0 80 1 6-52-56001-023 C C
6-20-94K10-108
6-52-56001-028
6-52-56000-020
6-52-56001-023
6-52-56001-028
S MGN D
Sheet 40 of 42 h
10 pin & 8 pin co-lay 6-52-56001-022 6-52-56000-020 6-02-00248-LC2 SU1, SU2
Power Switch &
e
S MG ND S M GN D
6-52-56001-022 6-02-00268-LC1 3 m
1 2
LED Board
FOR E5128Q FOR E4120Q/ E5120Q
a
t
i
c
D
i
a
6-53-3150B-245 6-53-3150B-245 6-53-3150B-245 S _ V IN 6-53-3150B-245
6-53-3050B-241 6-53-3050B-241 6-53-3050B-241 6-53-3050B-241
HOT KEY 6-53-3050B-240 6-53-3050B-240 6-53-3050B-240 6-53-3050B-240

g
r
a
POWER BUTTON WEB_WWW# WEB_EMAIL# SR3
AP_KEY# m
SPWR_SW1 S W W W _S W 1 S MA IL _ S W 1 * 10 0 K _ 1% _ 0 4 S A P _S W 1
T J G-5 3 3-S -T /R T J G-5 3 3-S -T /R TJ G-5 3 3 -S -T /R T J G-5 3 3 -S -T/R
1 2 S M_ B T N# 1 2 SWEB_WWW# 1 2 S W E B _E MA IL # 1 2 S A P _O N
s
3 4 3 4 3 4 3 4
5 6 5 6
SC4 5 6
S C3 5 6
S C5 SR5
PSW1~8 S R4 *4 7K _ 0 4
0 .1 u_ 1 6 V _Y 5 V _0 4 0.1 u _ 16 V _ Y 5 V _ 0 4 0 _ 04 0.1 u _1 6 V _ Y 5 V _ 04
3 1
4 2
S MGN D S M GN D S M GN D S MG N D S MG ND S MG ND S MG ND
S M GND
FOR E4120Q/E5120Q S MG ND
POWER BUTTON
SPWR_SW2 S M H1 S MH3 S MH 4
* TJ G- 53 3 -S -T /R S M H2 S M H5 2 9 2 9 2 9
1 2 S M_ B T N# H 7_ 0 D2 _ 3 H 7 _0 D 2_ 3 3 8 3 8 3 8
3 4 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
5 6
PSW1~8 M T H2 37 D 87 MT H2 3 7D 87 MT H2 3 7D 1 18
3 1 S MG N D S M GND S M GND S M GN D
4 2
6-53-3150B-245
S MGN D 6-53-3050B-240 S M GN D S MGN D
6-53-3050B-241
FOR E5128Q
Power Switch & LED Board B - 41
Schematic Diagrams
External ODD Board

O DD BOARD FOR E5120Q
QJ_ODD2 QJ_ODD1
S1 S1
S2 QJ_SATA_TXP1 S2
S3 QJ_SATA_TXN1 S3
s
S4 S4
S5 QJ_SATA_RXN1 S5
S6 QJ_SATA_RXP1 S6
m
S7 S7
a
r P1
Q GN D
QJ_ODD_D ETECT#
QGND
P1
g Sheet 41 of 42 P2
P3 Q_5VS Q_5VS
P2
P3
a
i External ODD
P4
P5
P6
QJ_SATA_ODD_ DA# P4
P5
P6
D Board 1-162-100562 242001-1
c
PIN PIN
i GND1~2 =WG ND QGND QGND GN D 1 ~3 =QGN D
t 6-21-1 4010-0 13

a 6-21-1 3A00- 013 6-21-1 4020-0 13
6-21-1 4030-0 13
m
e
h Q_5VS
c
S
. QC2 QC1
B 0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04
QGND
QH1
C237D91 QH4
C237D91 QH3
C67D67 QH2
C67D67
QGND QGND
B - 42 Extern al ODD Board
Schematic Diagrams
Sequence
E 5 1 2 0 Q D 0 2 P O W E R S E Q U E N C E
VCCRTC
RTCRST#
3 8 . 8 m s V C C R T C t o R T C R S T # 92/96
SPEC MIN 9mS
DD_ON#
8 7 0 u s ( D D _ O N # t o 5 V )
5V
8/18/2019 1 . 5 m s ( D D _ O N # t o 3 . 3 V ) clevo+6-71-w24h0-d02a.unlocked.pdf
3.3V
PWRBTN# 8 5 m s 1 5 0 m s
RSMRST# 2 0 m s ( P W R B T N # t o R S M R S T # )
SUS_PWR_ACK 1 u s ( R S M R S T # t o S U S _ P W R _ A C K )
9 8 m s ( R S M R S T # t o S U S C # )
SUSC#
B
1.5V (VDDQ) 2 . 1 7 m s ( S U S C # t o 1 . 5 V (V D D Q ) )
5 7 u s ( S U S C # t o S U S B # ) )
.
S
SUSB#
4 . 4 m s ( 1 . 5 V ( V D D Q ) t o D D R 1 . 5 V _ P W R G D )
DDR1.5V_PWRGD
c
9 2 0 u s ( S U S B # t o 5 V S )
Sheet 42 of 42 h
5VS
Sequence
e
3.3VS 1 . 5 2 m s ( S U S B # t o 3 . 3 V S ) m
4 . 7 5 m s ( S U S B # t o V T T _ M E M ( 0 . 7 5 V ) )
VTT_MEM(0.75V) a
5 . 7 5 m s ( S U S B # t o 1 . 8 V S )
1.8VS t
1 . 2 7 m s ( 1 . 8 V S t o 1 . 8 V S _ P W G D )
i
1.8VS_PWRGD
c
1.1VS_VTT_EN 1 . 2 7 m s ( 1 . 1 V S _ V T T _ E N t o 1 . 1 V S _ V T T ) D
1.1VS_VTT 8 . 4 m s ( S U S B # t o 1 . 1 V S _ V T T )
i
a
1.1VS_PWRGD 0 m s ( 1 . 1 V S _ V T T t o 1 . 1 V S _ P W R G D ) g
0 m s ( 1 . 1 V S _ V T T t o A L L _ S Y S _ P W R G D )
ALL_SYS_PWRGD
r
a
H_VTTPWRGD 2 m s ( A L L _ S Y S _ P W R G D t o H _ V T T P W R G D ) m
VGFX_VCORE_EN (DFGT_VR_EN) 8 . 4 7 m s ( S U S B # t o V G F X _ VC O R E _ E N )
s
VGFX_VID 0 m s ( V G F X _ V C O R E _ E N t o VG F X _ V I D )
VGFX_CORE
9 . 2 9 m s ( S U S B # t o V G F X _ C O R E )
VGFX_VORE_PG 0 m s ( V G F X _ V C O R E t o V G F X _ V O R E _ P G )
2 8 0 m s ( A L L _ S Y S _ P W R G D t o P M _ M P W R O K )
MEPWROK
SPEC 0.0001mS ~ 500mS
VCORE_ON 2 8 0 m s ( A L L _ S Y S _ P W R G D t o V C O R E _ O N )
SPEC MIN 99mS
VCORE
2 . 8 4 m s ( V C O R E _ _ O N t o V C O R E )
SPEC MAX 3mS
CLKEN# 1 2 0 u s ( V C O R E t o C L K E N # )
CLKIN_BCLK
1 . 2 m s ( C L K E N # t o C L K I N _ B C L K )
VCORE PG (DELAY_PWRGD) 6 . 4 8 m s ( V C O R E t o D E L A Y _ P W R G D )
SYS_PWRGD/SB_PWROK 2 9 7 . 7 2 m s
( S U S B # t o S Y S _ P W R G D / S B _ P W R O K )
SM_DRAMPWROK 3 7 . 7 m s ( V C O R E t o S M _ D R A M P W R O K )
6 8 m s
H_CPUPWRGD ( V C O R E t o H _ C P U P W R G D )
SPEC 0.05mS ~ 650mS
SUS_STATE# 1 . 6 4 m s
( H _ C P U P W R G D t o S U S _ S T A T E # )
SPEC 0.03mS ~ 2mS
PLT_RST# 2 3 0 u s
( S U S _ S T A T E # t o P L T _ R S T # )
SPEC MIN 60us
Sequence B - 43
Schematic Diagrams
s
m
a
r
g
a
i
D
c
i
t
a
m
e
h
c
S
.
B
B - 44
BIOS Update
Appendix C:Updating the FLASH ROM BIOS

BIOS Versio n
To upd ate the FLASH ROM BIOS you must:
Make sure you down-
94/96
• Download the BIOS update from the web site. load the latest correct
• Unzip the files onto a bootable CD/DVD/USB Flash Drive. clevo+6-71-w24h0-d02a.unlocked.pdf version of the BIOS ap-
8/18/2019 propriate for the com-
• Reboot your computer from an external CD/DVD/USB Flash Drive. puter model you are
• Use the flash tools to update the flash BIOS using the commands indicated below. working on.
• Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
You should only
• Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer.
download BIOS ver-
• After rebooting the computer you may restart the computer again and make any required changes to the default BIOS sions that are
settings.
C
V1.01.XX or higher as :
appropriate for your B
Download the BIOS computer model.
I
O
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel.
S
Note that BIOS versions
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files
U
are not backward com- p
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model patible and therefore d
(see sidebar for important information on BIOS versions ). you may not down- a
e
t
grade your BIOS to up-
older version after an
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive grading to a later ver-
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the sion (e.g if you upgrade
a BIOS to ver 1.01.05,
downloaded files.
you MAY NOT then go
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB back and flash the BIOS
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software). to ver 1.01.04).
Set the comput er to boot from th e external drive

1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2.
3. Use the “arrow
Use the keys
+” and “-” to highlight
keys to movetheboot
Boot menu.up and down the priority order.
devices
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
C - 1
BIOS Update
Use the flash too ls to update the BIOS

1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
8/18/2019 3. Type the following command at the DOS prompt: clevo+6-71-w24h0-d02a.unlocked.pdf
C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
e
t restarts.
a
d
p Restart the co mputer (booting from the HDD)
U
S 1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
O
I the HDD.
B
: 2. Press F2 as the computer restarts to enter the BIOS.
C 3.
4. Use theLoad
Select arrow keys Defaults
Setup to highlight
(or the
press F9 menu.
Exit ) and select “Yes” to confirm the selection.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
Your computer is now running normally with t he updated BIOS

You may now enter the BIOS and make any changes you require to the default settings.
C-2

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8/18/2019 clevo+6-71-w24h0-d02a.unlocked.

E5120Q/E5120Q-C, E5125/E5125-C, E5128Q, E5128Q-C

Ab out t hi s Manual

The following information is included:

Appendix A, Part Lists P

IMPORTANT SAFETY INSTRUCTIONS

This Comput er’s Optic al Device is a Laser Class 1 Produ ct

Instructions for Care and Operation

Use only approved brands of Unplug the power cord before

advisable to also re-

User’s Manual on CD/DVD

Note that you should al-

Figure 1 This will help prevent

Card Reader/LAN JMB251C ....................................................... B-26

Chapter 1: Intro duct ion

Specifications Processor Options BIOS

Intel® Core™ i7 Processor One 32Mb SPI Flash ROM

Memory Security (Kensington® Type) Lock Slot

Card Reader Environmental Spec

Embedded Multi-In-1 Card Reader Temperature

Communication Non-Operating: 10% - 90%

Built-In Gigabit Ethernet LAN Dimensions & Weight

Full Range AC/DC Adapter

Energy Star 5.0 Compliant

1 - 4 External Locator - Top View with LCD Panel Open

External Locato r - Fron t & Right Side Views Figure 2

External Locator - Front & Right Side Views 1 - 5

External Loc ator - Left Side & Rear View

Figure 5 REAR VIEW

1 - 6 External Locator - Left Side & Rear View

External Locator - Bottom View

External Locator - Bottom View 1 - 7

Figure 7 Mainb oard Overvi ew - Top (Key Parts)

1 - 8 Mainboard Overview - Top (Key Parts)

Mainbo ard Overview - Bottom (Key Parts) Figure 8

Mainboard Overview - Bott om (Key Parts) 1 - 9

Figure 9 Mainb oard Overview - Top (Connector s)

1 - 10 Mainboard Overview - Top (Connectors)

Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Overview - Bottom (Connectors) 1 - 11

This chapter provides step-by-step instructions for disassembling the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/

An example of these types of boxes are shown in the sidebar.

the same way. The pin1 side is usually not indicated.

To remove the Battery: To remove the Bluetooth Module:

To remove the Wireless LAN Module:

Removing the Battery Figure 1

Removing the Battery 2 - 5

Removing the Hard Disk Drive

You have all the CD-ROMs and

If you have access to the internet,

2 - 6 Removing the Hard Disk Drive

b. d. c. Grip the tab and slide the

Removing the Hard Disk Drive 2 - 7

2 - 8 Removing the Optical (CD/DVD) Device

Removing the System Memory (RAM) 2 - 9

2 - 10 Removing the System Memory (RAM)

Removing and Installing a Processor 2 - 11

6 The heat sink, and CPU area in

2 - 12 Removing and Installing a Processor

cated on the label. • 3 Screws

Removing and Installing a Processor 2 - 13

2 - 14 Removing the 3G Module

http://slidepdf.com/reader/full/clevo6-71-w24h0-d02aunlockedpdf Disassembly 38/96

1 0 u _ 6.3 V_ X5 R_ 0 6 1 0 u_ 6 .3 V_ X5 R _ 06 1 0 u_ 6 .3 V_ X5R _ 06 1 u _6 .3 V_ X5 R _ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 1u _ 6 .3 V_ X5 R _0 4