Compal La-F292p Dda30 r1.0

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME :DDA30
1
Port Map: 1
PCB NO : LA-F292P Kirkwood MLK Port Map as of 2017-04-13

BOM P/N :
X9 KBL UMA U42

Kabylake R
2017-11-14
2
REV : 1.0(A00) 2
@ : Nopop Component RTD3@ : Support RTD3 Component

EMI@ : EMI Component
@EMI@ : EMI Nopop Component NRTD3@ : No Support RTD3 Component
ESD@ : ESDComponent @RTD3@ : Reserve RTD3 Component
@ESD@ : ESD Nopop Component
RF@ : RF Component
@RF@ : RF Nopop Component
CXDP@ : XDP Component
3 3
CONN@ : Connector Component

ESPI@ : ESPI interface Component
MB PCB
Part Number Description
LPC@ : External ESPI Component (SHD)
DAB00025010 PCB 26B LA-F292P REV1 MB UMA AR 2
U42@ : KBL-R U42 Component
Layout Dell logo U22@ : KBL-R U22 Component
DS3@ : Support DS3 Component
4
NDS3@ : No Support DS3 Component 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2016 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
ALL RIGHT RESERVED
REV:X00 PWR CKT:0810 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
Size Document Number Rev
1.0
PWB: PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-F292P
Date: Tuesday, November 14, 2017 Sheet 1 of 60
A B C D E
A B C D E
Memory Down
Kirkwood MLK AR Block Diagram
Memory BUS (LPDDR3)
LPDDR3 x 2
4xSDP/DDP/QDP P20,P21
4x32b,1866MHz
eDP Lane x 4
1 EDP CONN Trough eDP Cable 1
P30
USB2.0[5]
UF Camera
P30
HDMI 1.4 HDMI
CONN P22
PCIE[1][2][3][4] USB2.0[9] SLGC55544BVTR USB2.0[9]_PS
USB POWER SHARE
P40 USB3.0 Conn
Lef t r ear TypeC USB3.0/USB2.0
DDI[1] INTEL USB
USB3.0[1] PS(Ext Port 1)
P40
P28
AR-DP DDI[2] USB2.0[2]
USB3.0/USB2.0 P23-24 USB3.0 Conn
Lef t fr ont TypeC USB3.0[3] (Ext Port 2) P41
P29 KABYLAKE_U/R MCP
USB2.0[6]
PD Solution Card reader
USB2.0/SMBus TPS65982D USB2.0/SMBus USB3.0[4] RTS5330 SD4.0
P25-26 P31 P31
2 2
USB2.0[8] Wacom G12T Touchscreen/Pen

SATA[1]/PCIE[8] PCIE[6] PCIE[5]
I2C[0,2] 10 pin conn(default).
P30
M.2,3042 Key B
Micro SIM M.2,3030 Key A
P33 WWAN/LTE/HCA
PCIex2 for 2nd SSD and WLAN+BT/WIGIG
Optane P33
P33
USB2.0[4]
USB2.0[7] 2nd Accelerometer
I2C
SW2_DP1
(MB) P45
USB/PCIE MUX
Magnetometer/
HD3SS3212 E-Compass
P32
Place on Sensor/B
Accelerometer &
PCIE[7] USB3.0[2] Gyroscope
LID SWITCH for
PAGE 6~19
Laptop mode P45
3 HD Audio I/F 3
LID SWITCH for
SATA[2]/PCIE[12][11][10][9] 0 ohm Place on RF module Tablet mode P45
SPI SAR Sensor
Smart Card TDA8034HN 0 ohm
USB2.0[10] W25Q128JVSIQ MEC5105 Semtech SX9310 USH CONN
USH TPM1.2 P45 P38
P8
ESPI
BCM58102
SPI 128M 4K sector INT.Speaker
RFID/NFC CPU&PCH XDP Port
W25Q128JVSIQ P35
P14
P8
Fingerprint SPI 128M 4K sector HDA Codec Universal Jack AUTOMATIC POWER
NB-2023-S CONN reserve
ALC3253 P35 P35 SWITCH(APS) P11
USH board P38
Dig. MIC
P30 DC/DC Interface
P44
Trough eDP Cable
Place on PWR/B
TPM1.2
NPCT650JB2YX & POWER ON/OFF
NPCT750JAAYX P38 SW & LED P43
M.2 2280
4 SSD Conn P39 4
KB/TP CONN
SMSC KBC P42
GPIO expander I2C
MEC5105
MCP23008 P37 DELL CONFIDENTIAL/PROPRIETARY
P36 FAN CONN
P37
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F292P
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 JUSB1-->Right 1 TYPEC Front Side
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

USB3.0-2 SSIC M.2 3042(LTE) 2 JUSB2-->Lef t
USB3.0-3 JUSB2-->Lef t 3 TYPEC Rear Side
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
D
USB3.0-4 SD Card Reader 4 M2 3042(WWAN) D
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 5 UF Camera
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

USB3.0-6 PCIE-2 6 SD Card Reader
Alpine Ridge-DP
PCIE-3 7 M.2 3030(BT)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 8 Touch Screen
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 M.2 3030(WLAN) 9 JUSB1-->Right
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 M.2 3030(WIGIG) 10 USH
PCIE-7 SATA-0
M.2 3042(SATA Cache or HCA)
PM TABLE PCIE-8 SATA-1
+5V_ALW
PCIE-9
(M-OFF)
+3.3V_ALW PCIE-10 M.2 2280 SSD
+3.3V_ALW_DSW +3.3V_CV2 +5V_RUN (PCIe4 or SATA)
+3.3V_M +3.3V_M PCIE-11 SATA-1*
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
power +VCC_CORE
C plane +RTC_CELL +2.5V_MEM +0.6V_DDR_VTT PCIE-12 SATA-2 C
+VCC_GT
+1.8V_PRIM +1.0V_VCCST +1.8V_RUN
+1.0VS_VCCIO
+1.0V_PRIM
+VCC_SA
+1.0V_PRIM_CORE
+5V_ALW 2
State
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
S0 ON ON ON ON ON
S3 ON ON OFF ON OFF
S5 S4/AC ON OFF OFF ON OFF
S5 S4/AC doesn't exist OFF OFF OFF OFF OFF
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
SIO_SLP_SUS# CPU PWR

SIO_SLP_S4#
SIO_SLP_S4# TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
Peripheral Device PWR
SY8210A
(PU200) TYPE-C Power
0.6V_DDR_VTT_ON RUN_ON
TPS22961 SIO_SLP_S0#
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER
SIO_SLP_S4#
TPS22961
(UZ21) +1.0V_VCCST
D D
SIO_SLP_SUS#
SY8286R
(PU301) +1.0V_PRIM
RUN_ON
CHARGER TPS62134C
ISL9538 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALW ON
(PU901) SYV828C
(PU102) TPS62134D SIO_SLP_SUS#
(PU402) +1.0V_PRIM_CORE
+5V_ALW2
RUN_ON 3.3V_TS_EN
EM5209 LP2301
(UZ4) +5V_RUN (QV8) +3.3V_TSP
BATTERY AUD_PWR_EN
EM5209
(@UZ5) +5V_RUN_AUDIO
USB_POWERSHARE_VBUS_EN
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALW ON
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR
ISL95857
(PU602) +3.3V_ALW
SIO_SLP_S4#
AP7361C
(PU503) +1.8V_MEM
for LPDDR3
SIO_SLP_SUS# RUN_ON
RT8097ALGE AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN
ISL95808 CSD97396 CSD97396 AO6405

(PU614) (PU612) (PU610) (QV1) EM5209 AUX_EN_WOWL
(UZ2) +3.3V_WLAN
IMVP_VR_ON
IMVP_VR_ON
IMVP_VR_ON
@SIO_SLP_WLAN#
EN_INVPWR
SIO_SLP_SUS#
+3.3V_ALW_PCH
B EM5209 @PCH_ALW_ON B
(UZ3)
RUN_ON 3.3V_CAM_EN#
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC LP2301A
+3.3V_RUN (QZ1) +3.3V_CAM
3.3V_WWAN_EN
EM5209
TYPE-C (UZ4) +3.3V_WWAN
AUD_PWR_EN
EM5209
+5V_ALW (@UZ5) +3.3V_RUN_AUDIO
TPS65982D
(UT5,UT11) +TBT_VBUS(5V~20V) G524B1T11U ENVCC_PCH
(UV24) +LCDVDD
TBT_PWR_EN
AOZ1336
+5V_ALW (UT4) +3.3V_TBT
+3.3V_TBT_SX AP2112K
(UT14) AP2204
+5V_TBT_VBUS (UT8,UT12) CV2_ON
TPS22967
(UZ18) +3.3V_CV2
USH/B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power rails
5 4 3 2 1
5 4 3 2 1
1K 2.2K
SMBUS Address [0x9a]
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
AW44 MEM_SMBCLK DDR_XDP_WAN_SMBCLK
53
MEM_SMBDATA
DMN66D0LDW-7 DDR_XDP_WAN_SMBDATA
BB43 51 XDP
DMN66D0LDW-7
499
PCH
499
+3.3V_ALW_PCH
D D
AY44 SML0_SMBCLK
BB39 SML0_SMBDATA
AW45 AW42
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
2.2K
E11 D8 2.2K
+3.3V_ALW 2.2K
+3.3V_TBT_FLASH
03 03 2.2K
00 D7 UPD2_SMBCLK B5
DMN66D0LDW-7 PD
00 E7 UPD2_SMBDAT A5 FW reflash KEYSCAN_SMBDAT
DMN66D0LDW-7
@2.2K 2.2K 2.2K
+3.3V_ALW +3.3V_CV2 +3.3V_RUN

@2.2K 2.2K 2.2K
01 B3 USH_SMBCLK
DMN66D0LDW-7
E5 USH_SMBDAT SAR
01
C DMN66D0LDW-7 C
M9
4.7K USH/B
L9 USH ALS
+3.3V_RUN
KBC 02
02
E10
C12
DAT_TP_SIO_I2C_CLK
DAT_TP_SIO_I2C_DATA
0
0
I2C_1_SCL TP
2.2K 0
2.2K I2C_1_SDA
0
2.2K +3.3V_ALW +3.3V_TBT_FLASH
2.2K
MEC 5105 04 C3 UPD1_SMBCLK

DMN66D0LDW-7 B5
B4 UPD1_SMBDAT PD
04 A5
DMN66D0LDW-7
2.2K
05 F7
05 B6
06 A12
2.2K
B N10 B
06 +3.3V_ALW
2.2K
EXPANDER_GPU_SMCLK
07 M4
M7 EXPANDER_GPU_SMDATA Expander IO
07
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
10
100 ohm 7
N2 PBAT_CHARGER_SMBCLK
100 ohm 6
BATTERY
10 M3 PBAT__CHARGER_SMBDAT CONN
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
UC1A CPU@ KBL-R U4+2
Rev_0.1
2 1 CPU_DP1_CTRL_CLK E55 C47
RC175 2.2K_0402_5% <23> CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <30>
2 1 CPU_DP1_CTRL_DATA <23> CPU_DP1_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <30>
RC178 2.2K_0402_5% <23> CPU_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <30>
2 1 CPU_DP2_CTRL_CLK <23> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <30> support QHD
D RC176 2.2K_0402_5% <23> CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 EDP_TXN2 <30> D
2 1 CPU_DP2_CTRL_DATA <23> CPU_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47 EDP_TXP2 <30>
RC177 2.2K_0402_5% <23> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47 EDP_TXN3 <30>
<23> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <30>
AR C50 E45
<23> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXN <30>
<23> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <30>
<23> CPU_DP2_N1 D52 DDI2_TXN[1] B52
<23> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
<23> CPU_DP2_N2 B50 DDI2_TXN[2] G50 CPU_DP1_AUXN
<23> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DP1_AUXP CPU_DP1_AUXN <23>
<23> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DP1_AUXP <23>
<23> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <23>
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <23>
DISPLAY SIDEBANDS RSVD F46 CPU_DP3_AUXP PAD~D @ T1
CPU_DP1_CTRL_CLK L13 RSVD PAD~D @ T2
<23> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9
<23> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <23>
CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <23> EDP_HPD 1 2
CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 RC1 100K_0402_5%
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
N11 GPP_E17/EDP_HPD EDP_HPD <30>
N12 GPP_E22 R12
<30> TS_INT# GPP_E23 EDP_BKLTEN R11 PANEL_BKLEN <30>
RC2 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <30>
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <30>
KBL-RU42_BGA1356 1 OF 20
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil, KBL-RU42_BGA1356.olb
Max length=100 mils.
C C
UC1I CPU@ KBL-R U4+2

Rev_0.1
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
B C31 E13 CSI2_COMP RC3 1 2 100_0402_1% B
D31 CSI2_DN4 CSI2_COMP B7 TBT_FORCE_PWR
C33 CSI2_DP4 GPP_D4/FLASHTRIG TBT_FORCE_PWR <23>
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2 MEM_CONFIG0

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 MEM_CONFIG1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 MEM_CONFIG2
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 MEM_CONFIG3
A29 GPP_F16/EMMC_DATA3 AN1 MEM_CONFIG4
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
+1.8V_PRIM
A A
1 2 MEM_CONFIG0 1 2
X76@ RC388 10K_0402_5% X76@ RC393 10K_0402_5%
1 2 MEM_CONFIG1 1 2
X76@ RC389 10K_0402_5% X76@ RC394 10K_0402_5%
1 2 MEM_CONFIG2 1 2 DELL CONFIDENTIAL/PROPRIETARY
X76@ RC390 10K_0402_5% X76@ RC395 10K_0402_5%
1 2 MEM_CONFIG3 1 2
X76@ RC391 10K_0402_5% X76@ RC396 10K_0402_5% Compal Electronics, Inc.
1 2 MEM_CONFIG4 1 2 Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
X76@ RC392 10K_0402_5% X76@ RC397 10K_0402_5% TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
CPU (1/14)
1.0
5 4 3 2 1
5 4 3 2 1
For LPDDR3
<20> DDR_A_DQS#[0..7] <21> DDR_B_DQS#[0..7]
<20> DDR_A_D[0..63] <21> DDR_B_D[0..63]

LPDDR3, Ballout for side by side(Non-Interleave) <20> DDR_A_DQS[0..7] <21> DDR_B_DQS[0..7]
D D
<20> DDR_A_CAA[0..9] <21> DDR_B_CAA[0..9]
KBL-R U4+2 <20> DDR_A_CAB[0..9] KBL-R U4+2 <21> DDR_B_CAB[0..9]

UC1B CPU@ UC1C CPU@
Rev_0.1 Rev_0.1
DDR_A_D0 AL71 AU53 DDR_A_CLK#0
DDR_A_D1 DDR0_DQ[0] DDR0_CKN[0] DDR_A_CLK0 DDR_A_CLK#0 <20> DDR_A_D16 Interleave / Non-Interleaved DDR_B_CLK#0
AL68 AT53 AF65 AN45
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 <21>
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
DDR_A_D4 AL70 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21>
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[2] AY56 DDR_A_CKE3 DDR_A_CKE2 <20> DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] DDR_A_CKE3 <20> DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 DDR_B_CKE2 <21>
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] DDR_B_CKE3 <21>
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[0] AT43 DDR_A_ODT0 <20> DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT0 <21>
DDR_A_D15 AU69 DDR0_DQ[14] DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 DDR_A_CAA0 DDR_A_D31 DDR1_DQ[14]/DDR0_DQ[30]
BA51 AH69
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_CAA1 DDR_A_D48 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4 DDR_B_CAA0
BB54 AT66 AY48
DDR_A_D32 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_CAA2 DDR_A_D49 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_CAA1
BB65 BA52 AU66 AP50
DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_CAA3 DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_CAA2
DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_CAA4 DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_CAA3
DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_CAA5 DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_CAA4
DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_CAA6 DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_CAA5
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_CAA7 DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_CAA6
DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_CAA8 DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_CAA7
DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_CAA9 DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_CAA8
DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU46 DDR_A_CAB0 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_CAA9
C DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAB1 DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43 DDR_B_CAB0 C
DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_CAB2 DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAB1
DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_CAB3 DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_CAB2
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_CAB4 DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_CAB3
DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_CAB5 DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_CAB4
DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_CAB6 DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_CAB5
DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_CAB7 DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_CAB6
DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_CAB8 DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_CAB7
DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_CAB9 DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_CAB8
DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_CAB9
DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46
DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] BA47
DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23]
DDR_B_D8 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] DDR_A_DQS1 DDR_B_D25 DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved DDR_A_DQS#2
AY35 AT70 AU33 AH66
DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
DDR_B_D10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR_B_D27 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS#3
DDR_B_D11 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#4 DDR_B_D28 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_A_DQS3
AW33 BA64 AR33 AG70
DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS4 DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS#6
DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#5 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS5 DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS#7
DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_B_DQS#0 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS7
DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS0 DDR_B_D48 AU27 DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#2
DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS#1 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS2
DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS1 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#3
DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS#4 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS3
DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS4 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS#5 DDR_B_D53 AN27 DDR1_DQ[52] AR25 DDR_B_DQS#6
DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS5 DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50
DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D56 AT22 DDR1_DQ[55] DDR1_DQSN[7] AR21 DDR_B_DQS7
B DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 PAD~D @ T260 DDR_B_D57 AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43 B
DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR PAD~D @ T261 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_ALERT# AP43 PAD~D @ T257
DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] AY67 DDR_B_D59 AT21 DDR1_DQ[58] DDR1_PAR AT13 PAD~D @ T258
DDR CH - A
DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA AY68
+DDR_VREF_CA DDR_B_D60 AN22 DDR1_DQ[59] DDR CH - B DRAM_RESET# AR18 SM_RCOMP0 PAD~D @ T259
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ +DDR_VREF_A_DQ DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[0] SM_RCOMP1
BA27 BA67 AP22 AT18
DDR_B_D46 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +DDR_VREF_B_DQ DDR_B_D62 DDR1_DQ[61] DDR_RCOMP[1] SM_RCOMP2
BA25 AP21 AU18
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR_VTT_CTRL DDR_B_D63 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2]
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL DDR1_DQ[63]
KBL-RU42_BGA1356 KBL-RU42_BGA1356
DDR1_PAR,DDR1_ALERT# for DDR4
+1.2V_MEM LPDDR3 COMPENSATION SIGNALS

UD5
1 5 1 2 SM_RCOMP0 RC5 1 2 200_0402_1%
NC VCC @ CD115 0.1U_0201_10V6K
DDR_VTT_CTRL 2 SM_RCOMP1 RC6 1 2 80.6_0402_1%
A 4
3 Y 0.6V_DDR_VTT_ON <49> SM_RCOMP2 1 2 162_0402_1%
RC7
GND 1 2
+3.3V_RUN
74AUP1G07SE-7 SOT353 RD83 100K_0402_5%
CHECK
CAD Note:
0.6V_DDR_VTT_ON (control 0.6V power EN) Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
CPU (2/14)
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
For Kirkwood
PCH EDS R0.7 p.235~236
2
UC1E CPU@ KBL-R U4+2
Rev_0.1
SPI - FLASH
SMBUS, SMLINK
MEM_SMBCLK 6 1
PCH_SPI_CLK AV2 R7 MEM_SMBCLK DDR_XDP_WAN_SMBCLK <14>
PCH_SPI_D1 AW3 SPI0_CLK GPP_C0/SMBCLK R8 MEM_SMBDATA CXDP@ QC2A
SPI0_MISO GPP_C1/SMBDATA
5
CXDP@ RC10 1 2 1K_0402_1% PCH_SPI_D0 AV3 R10 PCH_SMB_ALERT# DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO_XDP 1 2 1K_0402_1% PCH_SPI_D2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
CXDP@ RC11
<14> PCH_SPI_DO2_XDP PCH_SPI_D3 AU4 SPI0_IO2 R9 SML0_SMBCLK MEM_SMBDATA 3 4
D PCH_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_SMBDATA DDR_XDP_WAN_SMBDAT <14> D
PCH_SPI_CS#1 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 GPP_C5 CXDP@ QC2B
PCH_SPI_CS#2 AU1 SPI0_CS1# GPP_C5/SML0ALERT# DMN65D8LDW-7_SOT363-6 +3.3V_RUN
<38> PCH_SPI_CS#2 SPI0_CS2# SML1_SMBCLK
W3
GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <36>
SPI - TOUCH GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDATA <36> DDR_XDP_WAN_SMBDAT1 2
M2 GPP_B23/SML1ALERT#/PCHHOT# RC318 2.2K_0402_5%
M3 GPP_D1/SPI1_CLK DDR_XDP_WAN_SMBCLK1 2
J4 GPP_D2/SPI1_MISO RC319 2.2K_0402_5%
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2 AY13 ESPI_IO0_R RC3661 2 15_0402_5% +3.3V_ALW_PCH
M1 GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <36,37>
LPC RC3671 2 15_0402_5%
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <36,37> MEM_SMBCLK
RC3681 2 15_0402_5% ESPI_IO2 <36,37>
1 2
GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3691 2 15_0402_5% RC12 1K_0402_5%
C LINK GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_IO3 <36,37> MEM_SMBDATA 1 2
G3 GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <36,37> RC14 1K_0402_5%
<33> PCH_CL_CLK1 G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <36,37> SML1_SMBCLK 1 2
<33> PCH_CL_DATA1 G1 CL_DATA RC15 1K_0402_5%
<33> PCH_CL_RST1# CL_RST# AW9 ESPI_CLK EMI@ RC16 1 2 15_0402_5% SML1_SMBDATA 1 2
GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 @ RC22 1 2 22_0402_5% ESPI_CLK_5105 <36,37> RC17 1K_0402_5%
AW13 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# SML0_SMBCLK 1 2
GPP_A0/RCIN# GPP_A8/CLKRUN# RC347 499_0402_1%
AY11 SML0_SMBDATA 1 2
<36> ESPI_ALERT# GPP_A6/SERIRQ RC348 499_0402_1%
RC21 2 1 8.2K_0402_1%
+3.3V_1.8V_ESPI
C C
RF Request
ESPI_CLK_5105 1 2
RF@ CC316 82P_0402_50V8J
CLKRUN# 1 2
LPC@ RC27 8.2K_0402_5%
SOFTWARE TAA SML0_SMBCLK 1 2
@RF@ CC318 33P_0402_50V8J
SML1_SMBCLK 1 2 +3.3V_ALW_PCH
RPC1 @RF@ CC319 33P_0402_50V8J
PCH_SPI_D0_R1 1 8 PCH_SPI_D0_0_R MEM_SMBCLK 1 2
<38> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 2 7 PCH_SPI_CLK_0_R @RF@ CC320 33P_0402_50V8J PCH_SMB_ALERT# 1 2
<38> PCH_SPI_CLK_R1 PCH_SPI_D1_R1 3 6 PCH_SPI_D1_0_R RC23 2.2K_0402_5%
<38> PCH_SPI_D1_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R
+3.3V_SPI
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R TLS CONFIDENTIALITY
33_0804_8P4R_5%
2 1 PCH_SPI_D2_R1 Place close CPU side HIGH ENABLE
@ RC30 1K_0402_5%
LOW(DEFAULT) DISABLE
33_0402_5%
33_0402_5%
1
2 1 PCH_SPI_D3_R1
@EMI@
@EMI@
@ RC31 1K_0402_5% WEAK INTERNAL 20K PD

RC28
RC29
2 1 PCH_SPI_D3_R1
@ RC316 1K_0402_5%
2
PCH_SPI_D3_R1 @ RC407 1 2 33_0402_5% PCH_SPI_D3_1_R +3.3V_ALW_PCH

33P_0402_50V8J
33P_0402_50V8J
PCH_SPI_CLK_R1 @ RC408 1 2 33_0402_5% PCH_SPI_CLK_1_R

03/02:follow Intel MOW_2015WW06 PCH_SPI_D0_R1 @ RC409 1 2 33_0402_5% PCH_SPI_D0_1_R
@EMI@
@EMI@
1
B PCH_SPI_D1_R1 @ RC410 1 2 33_0402_5% PCH_SPI_D1_1_R B

GPP_C5
CC7
CC8
1 2
ESPI@RC25 4.7K_0402_5%
2
ACES_50696-0200M-P01
22
21 GND_2
+3.3V_SPI GND_1 EC interface
CC9 2 1 PCH_SPI_CS#1_R1 20
HIGH ESPI
1 2 @RC32 0_0402_5% PCH_SPI_CS#1 19 20 LOW(DEFAULT) LPC
2 1 PCH_SPI_D0_R1 18 19 WEAK INTERNAL 20K PD
128Mb Flash ROM 0.1U_0201_10V6K @ RC33 0_0402_5% PCH_SPI_D0 17 18
UC5 2 1 PCH_SPI_D1_R1 16 17
PCH_SPI_CS#0_R1 @ RC37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 @ RC34 0_0402_5% PCH_SPI_D1 15 16
PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R 2 1 PCH_SPI_CLK_R1 14 15
PCH_SPI_D2_R1 RC39 1 2 33_0402_5% PCH_SPI_D2_0_R 3 IO1 IO3 6 PCH_SPI_CLK_0_R @ RC35 0_0402_5% PCH_SPI_CLK 13 14 +3.3V_ALW_PCH
4 IO2 CLK 5 PCH_SPI_D0_0_R 2 1 PCH_SPI_CS#0_R1 12 13
GND IO0 @ RC36 0_0402_5% PCH_SPI_CS#0 11 12
W25Q128FVSIQ_SO8 2 1 PCH_SPI_D2_R1 10 11
@ RC38 0_0402_5% PCH_SPI_D2 9 10 GPP_B23 1 2
+3.3V_SPI 2 1 PCH_SPI_D3_R1 8 9 RC317 150K_0402_5%
@ RC40 0_0402_5% PCH_SPI_D3 7 8
@ CC10 6 7
+3.3V_SPI 6
1 2 5
128Mb Flash ROM +3.3V_ALW_PCH
4 5 EXI BOOT STALL BYPASS
0.1U_0201_10V6K 2 1 3 4
@ RC41 2 3 HIGH ENABLED
@ UC6 0_0402_5%
PCH_SPI_CS#1_R1 @ RC42 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 1 2 LOW(DEFAULT) DIABLED
PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R 1 WEAK INTERNAL PD
PCH_SPI_D2_R1 @ RC43 1 2 33_0402_5% PCH_SPI_D2_1_R 3 IO1 IO3 6 PCH_SPI_CLK_1_R JSPI1
4 IO2 CLK 5 PCH_SPI_D0_1_R CONN@
GND IO0
A W25Q128FVSIQ_SO8 A
CPU (3/14)
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN UC1F CPU@ KBL-R U4+2

Rev_0.1
LPSS ISH +3.3V_ALW_PCH
@ RC560 AN8 P2 MEM_INTERLEAVED

D 0_0201_5% ONE_DIMM# AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 D
2 1 PCH_3.3V_TS_EN 1 2 TPM_PIRQ#_R AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 AR_DET# RTD3_CIO_PWR_EN 1 2
<38> TPM_PIRQ# NRB_BIT GPP_B17/GSPI0_MISO GPP_D11
@ RC282 100K_0402_5% AR7 P1 RTD3@ RC559 10K_0402_5%
@ RC561 GPP_B18/GSPI0_MOSI GPP_D12
0_0201_5% AM5 M4 ISH_I2C0_SDA
2 1 SIO_EXT_SCI# 1 2 SIO_EXT_SCI# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 ISH_I2C0_SCL ISH_I2C0_SDA <45> +3.3V_RUN
RC237 10K_0402_5%
<30> PCH_3.3V_TS_EN GPP_B22
AP5
AN5
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_D6/ISH_I2C0_SCL
N1 ISH_I2C1_SDA
ISH_I2C0_SCL <45>
Only for Kirkwood
2 1 LPSS_UART2_RXD GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 ISH_I2C1_SCL ISH_I2C1_SDA <36,45>
PCH_TBT_PERST# AB1 GPP_D8/ISH_I2C1_SCL ISH_I2C1_SCL <36,45> ISH_I2C0_SDA 1 2
@ RC402 49.9K_0402_1%
2 1 LPSS_UART2_TXD <23> PCH_TBT_PERST# AB2 GPP_C8/UART0_RXD AD11 ISH_I2C2_SDA RC358 2.2K_0402_5%
@ RC403 49.9K_0402_1%
<37> SBIOS_TX TYPEC_CON_SEL1 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 ISH_I2C2_SCL ISH_I2C2_SDA <33> WWAN ISH_I2C0_SCL 1 2
TYPEC_CON_SEL2 AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <33>
RC359 2.2K_0402_5%
GPP_C11/UART0_CTS# ISH_I2C1_SDA 1 2
LPSS_UART2_RXD AD1 U1
9/24: Reserve for embedded locat i on,r ef er I nt el PDG 0. 9 @ RC360 1K_0402_5%
LPSS_UART2_TXD AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 ISH_UART0_RXD <33> ISH_I2C1_SCL 1 2
AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 ISH_UART0_TXD <33>
@ RC361 1K_0402_5%
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 ISH_UART0_RTS# <33> WLAN LCD_CBL_DET# 1 2
+3.3V_ALW_PCH GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <33>
RC287 100K_0402_5%
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 RTD3_CIO_PWR_EN SIO_EXT_WAKE# <36>
<30> TS_I2C_SDA U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 RTD3_CIO_PWR_EN <23>
2 1 SIO_EXT_WAKE# <30> TS_I2C_SCL GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 LCD_CBL_DET# <30> +1.8V_RUN
RC283 10K_0402_5% U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
2 1 LPSS_UART2_RXD <42> I2C1_SDA_TP U9 GPP_C18/I2C1_SDA AY8 ISH_GP0_D
<42> I2C1_SCK_TP GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 ISH_GP1_D ISH_GP0_D <45>
@ RC330 49.9K_0402_1%
2 1 LPSS_UART2_TXD I2C2_ALS_SDA AH9 GPP_A19/ISH_GP1 BB7 ISH_GP2_D ISH_GP1_D <45> ISH_I2C2_SDA 1 2
I2C2_ALS_CLK AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 ISH_GP3_D ISH_GP2_D <45>
@ RC331 49.9K_0402_1% @ RC363 1K_0402_5%
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 NB_MODE#_D ISH_GP3_D <45> ISH_I2C2_SCL 1 2
AH11 GPP_A22/ISH_GP4 AW7 LID_CL#_NB_C @ RC362 1K_0402_5%
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 LID_CL#_TAB_C @ RC5042 1 0_0402_5%
2 1 PCH_TBT_PERST# GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 @ RC5052 1 0_0402_5% LID_CL#_NB_D <45>
C AF11 LID_CL#_TAB_D <45> C
@ RC557 100K_0402_5%
AF12 GPP_F8/I2C4_SDA
2 1 PCH_TBT_PERST# GPP_F9/I2C4_SCL GPP_A GROUP is +1.8V
RC558 100K_0402_5% ISH_GP0 for Main Accelerometer (LCD Sesnor Board)
RTD3@ KBL-RU42_BGA1356 6 OF 20 ISH_GP1 for 2nd Accelerometer (MB) ISH_GP0_D 1 2
ISH_GP2 for E-Compass (MB) @ RC365 10K_0402_5%
ISH_GP3 for ALS (LCD Sesnor Board) ISH_GP1_D 1 2
ISH_GP4 for EC5105 (Tablet/NB mode) @ RC364 10K_0402_5%
+3.3V_RUN +1.8V_RUN +1.8V_RUN ISH_GP2_D 1 2
@ RC501 10K_0402_5%
+3.3V_RUN ISH_GP3_D 1 2
1
1
@ RC502 10K_0402_5%
RC512 @ RC510 @ +3.3V_ALW +1.8V_PRIM NB_MODE#_D 1 2
2 1 NRB_BIT 2.2K_0402_5% 2.2K_0402_5% @ RC349 10K_0402_5%
@ RC186 4.7K_0402_5%
2
2
1
1
6 1 I2C2_ALS_SDA RC506 @
NO REBOOT STRAP <45> I2C2_SDA_ALS
RC507 10K_0402_5%
+3.3V_RUN @ QC4A
HIGH No REBOOT DMN63D8LDW-7_SOT363-6 +1.8V_RUN
100K_0402_5%
LOW(DEFAULT) REBOOT ENABLE
2
2
1
2
G
Weak IPD
1
RC513 @
2.2K_0402_5% RC511 @ 1 3 NB_MODE#_D
<36> NB_MODE#
1
2.2K_0402_5%
S
5
RC509
2
S TR BSS138W 1N SOT-323-3 10K_0402_5%
2
3 4 I2C2_ALS_CLK
<45> I2C2_SCL_ALS QC3
2
@ QC4B @ RC5081 2 0_0402_5%
DMN63D8LDW-7_SOT363-6
B +3.3V_ALW_PCH B
2 1 GPP_B22
@ RC184 8.2K_0402_5% +3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCH +3.3V_ALW_PCH
2
BOOT BIOS Dest i nat i on(Bi t 10

) @ RC555 @ RC553
HIGH LPC 10K_0402_5% 10K_0402_5%
2
LOW(DEFAULT) SPI @ RC371 RC400 @
1
Internal 20k PD 10K_0402_5% 10K_0402_5%

TYPEC_CON_SEL1 TYPEC_CON_SEL2
1
1
+3.3V_RUN
MEM_INTERLEAVED AR_DET#
10K_0402_5%
@ RC556 @ RC554
2
@ RC267
10K_0402_5% 10K_0402_5%
2
1
1
10K_0402_5% 10K_0402_5%
ONE_DIMM# RC372 RC401
2
1
10K_0402_5%
DIMM TYPE AR_DET#

Vendor JAE FOXCON TBD TBD
RC268
TYPEC_CON_SEL1 LOW LOW HIGH HIGH HIGH Interleave HIGH NON AR

2
A A
TYPEC_CON_SEL2 LOW HIGH LOW HIGH LOW Non-Interleave LOW AR
DIMM Detect Compal Electronics, Inc.
HIGH 1 DIMM
LOW 2 DIMM BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (4/14)
1.0
5 4 3 2 1
5 4 3 2 1
For AR, Kirkwood
UC1H CPU@ KBL-R U4+2

Rev_0.1
SSIC / USB3
PCIE / USB3 / SATA
H8
USB3_1_RXN G8 USB3_PRX_DTX_N1 <40>
D H13 USB3_1_RXP C13 USB3_PRX_DTX_P1 <40> D
<23> PCIE_PRX_DTX_N1 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_DRX_N1 <40> -----> Ext USB3 Port 1 Charge
<23> PCIE_PRX_DTX_P1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_DRX_P1 <40>
<23> PCIE_PTX_DRX_N1 A17 PCIE1_TXN/USB3_5_TXN J6
<23> PCIE_PTX_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_RXN H6 USB3_PRX_DTX_N2 <32>
G11 USB3_2_RXP/SSIC_RXP B13 USB3_PRX_DTX_P2 <32>
<23> PCIE_PRX_DTX_N2 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_TXN A13 USB3_PTX_DRX_N2 <32> -----> M.2 3042(LTE)
<23> PCIE_PRX_DTX_P2 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_TXP USB3_PTX_DRX_P2 <32>
<23> PCIE_PTX_DRX_N2 C16 PCIE2_TXN/USB3_6_TXN J10
<23> PCIE_PTX_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN H10 USB3_PRX_DTX_N3 <41>
AR -----> H16 USB3_3_RXP B15 USB3_PRX_DTX_P3 <41>
<23> PCIE_PRX_DTX_N3 G16 PCIE3_RXN USB3_3_TXN A15 USB3_PTX_DRX_N3 <41> -----> Ext USB3 Port 2
<23> PCIE_PRX_DTX_P3 D17 PCIE3_RXP USB3_3_TXP USB3_PTX_DRX_P3 <41>
<23> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<23> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10 USB3_PRX_DTX_N4 <31>
G15 USB3_4_RXP C15 USB3_PRX_DTX_P4 <31> -----> Card Reader RTS5330
<23> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15 USB3_PTX_DRX_N4 <31>
<23> PCIE_PRX_DTX_P4 B19 PCIE4_RXP USB3_4_TXP USB3_PTX_DRX_P4 <31>
<23> PCIE_PTX_DRX_N4 A19 PCIE4_TXN AB9
<23> PCIE_PTX_DRX_P4 PCIE4_TXP USB2N_1 AB10 USB20_N1 <26>
F16 USB2P_1 USB20_P1 <26> -----> Typce-C port1(AR,Front Side)
<33> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6
<33> PCIE_PRX_DTX_P5 C19 PCIE5_RXP USB2N_2 AD7 USB20_N2 <41>
M.2 3030(WLAN) ---> <33> PCIE_PTX_DRX_N5 D19 PCIE5_TXN USB2P_2 USB20_P2 <41> -----> Ext USB Port 2(LEFT)
<33> PCIE_PTX_DRX_P5 PCIE5_TXP AH3
G18 USB2N_3 AJ3 USB20_N3 <25>
F18 PCIE6_RXN USB2P_3 USB20_P3 <25> -----> Typce-C port2(AR,Rear Side)
D20 PCIE6_RXP AD9
C20 PCIE6_TXN USB2N_4 AD10 USB20_N4 <33>
PCIE6_TXP USB2P_4 USB20_P4 <33> -----> M2 3042(WWAN)
F20 AJ1
<32> PCIE_PRX_DTX_N7 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <30>
C <32> PCIE_PRX_DTX_P7 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 <30> -----> Camera C
<32> PCIE_PTX_DRX_N7 A21 PCIE7_TXN/SATA0_TXN AF6
M.2 3042(SATA Cache <32> PCIE_PTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_N6 <31>
or/HCA)---> G21 USB2P_6 USB20_P6 <31> -----> Card Reader RTS5330
<33> PCIE_PRX_DTX_N8 F21 PCIE8_RXN/SATA1A_RXN AH1
<33> PCIE_PRX_DTX_P8 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_N7 <33>
<33> PCIE_PTX_DRX_N8 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <33> -----> M.2 3030(BT)
<33> PCIE_PTX_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <30>
<39> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <30> -----> LCD Touch
<39> PCIE_PRX_DTX_P9 B23 PCIE9_RXP AG1
<39> PCIE_PTX_DRX_N9 A23 PCIE9_TXN USB2N_9 AG2 USB20_N9 <40>
<39> PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9 USB20_P9 <40> -----> Ext USB Port 1 Charge(RIGHT)
F25 AH7
<39> PCIE_PRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8 USB20_N10 <38> +3.3V_ALW_PCH
<39> PCIE_PRX_DTX_P10 D23 PCIE10_RXP USB2P_10 USB20_P10 <38> -----> USH
<39> PCIE_PTX_DRX_N10 C23 PCIE10_TXN AB6 1 2 113_0402_1%
USBCOMP RC44
<39> PCIE_PTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID @ RC3371 2 0_0402_5% 10K_8P4R_5%
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC338 1 2 1K_0402_5% USB_OC1# 1 8
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC3# 2 7
PCIE_RCOMPP A9 USB_OC0# 3 6
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <40> USB_OC2# 4 5
<14> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# <41>
M2 2280 SSD ---> <14> CPU_XDP_PREQ# HDD_FALL_INT BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# Reserve RPC3
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
<39> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
<39> PCIE_PRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 M3042_DEVSLP <33>
<39> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2_DEVSLP <39>
<39> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 SATAGP0
<39> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 M3042_PCIE#_SATA +3.3V_RUN
<39> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 m2280_PCIE_SATA# M3042_PCIE#_SATA <36> 10K_8P4R_5%
NEED DOUBLE CHECK
B <39> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 m2280_PCIE_SATA# <39> M2280_PCIE_SATA# 1 8 B
<39> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 2 7
SATALED#
GPP_E8/SATALED# SATALED# <33,39,43> SATAGP0 3 6
SATALED# 4 5
RPC4
M3042_PCIE#_SATA 1 2
RC551 10K_0402_5%
M3042_PCIE#_SATA 1 2
@ RC552 10K_0402_5%
1.8V?
+1.8V_RUN
HDD_FALL_INT 1 2
@ RC370 10K_0402_5%
12/17:INT1 is PP mode, depop RC370,double check.
A A
CPU (5/14)
1.0
5 4 3 2 1
5 4 3 2 1
UC1J CPU@ KBL-R U4+2

Rev_0.1 Close to CPU
For UMA CONFIG
<33> CLK_PCIE_N0
D42
CLKOUT_PCIE_N0
CLOCK SIGNALS
KBL-U / KBL-R U4+2
RSVD_E3/XTAL24_IN
RSVD_C7/XTAL24_OUT
E3
C7
XTAL24_IN_U42_CPU
XTAL24_OUT_U42_CPU
XTAL24_IN_U22_CPU
U42@
U42@
RC417
RC418
1
1
2
2
33_0402_5%
33_0402_5%
XTAL24_IN_U42
XTAL24_OUT_U42
XTAL24_IN_U22
For KBL-R U22 U22@ CC21
C42 E37 U22@ RC419 1 2 0_0402_5% 1 2
<33> CLK_PCIE_P0 @RF@ RC3732 1 0_0402_5% CLKREQ_PCIE#0_R AR10 CLKOUT_PCIE_P0 XTAL24_IN/NC_2 E35 XTAL24_OUT_U22_CPU 1 2 XTAL24_OUT_U22
WWAN---> U22@ RC420 0_0402_5%
<33> CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0# XTAL24_OUT/NC_1
+3.3V_RUN RC189 2 1 10K_0402_5% 15P_0402_50V8J
2
1M_0402_1%
U22@ RC46
B42
<33> CLK_PCIE_N1 CLKOUT_PCIE_N1
3
4
A42 F43 CLK_ITPXDP_N @ RC297 1 2 0_0402_5%
<33> CLK_PCIE_P1 @RF@ RC3742 1 0_0402_5% CLKREQ_PCIE#1_R AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P 1 2 0_0402_5% CLK_ITPXDP_N_R <14>
WLAN---> @ RC298 U22@ YC1
<33> CLKREQ_PCIE#1 2 1 10K_0402_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <14>
+3.3V_RUN RC47 24MHZ_12PF_X3G024000DC1H
D41 BA17 SUSCLK
1
2
D C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <33,39> D
@ RC50 2 1 10K_0201_1% CLKREQ_PCIE#2_R AT8 CLKOUT_PCIE_P2 XTAL24_IN_U22 U22@ CC22
WIGIG---> +3.3V_RUN GPP_B7/SRCCLKREQ2# XTAL24_OUT_U22 1 2
<23> CLKREQ_PCIE#2_R D40
<39> CLK_PCIE_N3 C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
+1.0V_CLK5 For Skylake,YC1 24 MHz (50 Ohm ESR) 15P_0402_50V8J
<39> CLK_PCIE_P3 @RF@ RC3762 1 0_0402_5% CLKREQ_PCIE#3_R AT10 CLKOUT_PCIE_P3 XCLK_BIASREF For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
M.2 SDD---> RC52 2.7K_0402_1%
<39> CLKREQ_PCIE#3 2 1 10K_0402_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 1 2
+3.3V_RUN RC59 For Skylake, pop RC52,depop RC324 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
B40 RTCX1 AM20 PCH_RTCX2 @ RC324 59_0402_1% For Cannonlake, pop RC324,depop RC52
A40 CLKOUT_PCIE_N4 RTCX2 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
@ RC51 2 1 10K_0402_5% CLKREQ_PCIE#4_R AU8 CLKOUT_PCIE_P4 AN18 SRTCRST# RC56 1 2 20K_0402_5%
LAN---> +3.3V_RUN +RTC_CELL_PCH
<23> CLK_PCIE_N5
<23> CLK_PCIE_P5
E40
E38
GPP_B9/SRCCLKREQ4#
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
SRTCRST#
RTCRST#
AM16
PCH_RTCRST# <36>
CC24 1 2 1U_0402_6.3V6K For KBL-R U42 U42@
CC338
1 2
AR ---> @RF@ RC3782 1 0_0402_5% CLKREQ_PCIE#5_R AU7
<23> CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5# PCH_RTCRST#
U42@RC415
+3.3V_RUN RC190 2 1 10K_0402_5% RC57 1 2 20K_0402_5% 12P_0402_50V8J
2
1M_0402_1%
3
4
CC25 1 2 1U_0402_6.3V6K
PCH_PLTRST# U42@YC3
KBL-RU42_BGA1356 10 OF 20 24MHZ_12PF_X3G024000DC1H
1
2
@ RC2441 2 0_0402_5% 1 2
+3.3V_ALW_DSW PCH_PLTRST#_EC <37> 1 2 XTAL24_IN_U42 U42@
CC339
XTAL24_OUT_U42 1 2
+3.3V_ALW_PCH PCH_PLTRST# 1 2
2 1 LAN_WAKE# PLTRST_TPM# <38> SHORT PADS~D
@ RC60 0_0402_5% For Skylake,YC3 24 MHz (50 Ohm ESR) 12P_0402_50V8J
RC323 10K_0402_5% @ CMOS1
PCH_PLTRST#_AND 1 2
CMOS1 must take care short & touch risk on layout placement
5
2 1 PCH_PCIE_WAKE# @ RC325 0_0402_5% CC23

RC67 1K_0402_5% 1 PCH_RTCX1 1 2
P
B 4 PCH_PLTRST#_AND PCH_RTCX2
2 O PCH_PLTRST#_AND <23,30,33,38,39>
15P_0402_50V8J
A
G
+1.0V_VCCST UC7
1
C TC7SH08FU_SSOP5~D @ RC65 @DS3@ RC441 C
3
2
2 1 VCCST_PWRGD SIO_SLP_SUS# 1 2 YC2
100K_0402_5% <18> VCCDSW_EN_GPIO PCH_PRIM_EN <17,44,50,51,52>
RC71 1K_0402_5% RC54 32.768KHZ_12.5PF_9H03200042
0_0402_5% 10M_0402_5% ESR MAX=50k ohm
2
2
+3.3V_ALW_PCH @ RC445 NDS3@ DC1 NDS3@ RC442
1 2 2 1 VCCDSW_EN_Q 1 2 CC26
1
2 1 ME_SUS_PWR_ACK <36> VCCDSW_EN 1 2 PCH_RTCX2_R 1 2
@ RC74 10K_0402_5% 0_0402_5% RB751S-40 SOD-523 0_0402_5% @ RC296 0_0402_5%
10/6 depop, prevent singal step. 12P_0402_50V8J
NDS3@ DC2
2 1 PCH_PWROK 1 2
<42,48> ALW_PWRGD_3V_5V +3.3V_ALW_DSW
@RC411 10K_0402_5%
RB751S-40 SOD-523 8/21 can change to 10K for merge to RP
PCH_BATLOW# 1 2
RC439RC440RE536RC215RC441RC442 RC72 8.2K_0402_5%
AC_PRESENT 1 2
H_CPUPWRGD VCCST_PWRGD RC243 10K_0402_5%
Support DS3 V X V X V X +RTC_CELL_PCH
100P_0402_50V8J
ESD@ CC300
100P_0402_50V8J
ESD@ CC301
1
No Support DS3 X V X V X V
INTRUDER# 1 2
RC69 1M_0402_5%
2
KBL-R U4+2
'V' mean POP, 'X' mean DE-POP
UC1K CPU@
Rev_0.1 +3.3V_ALW_PCH
SYSTEM POWER MANAGEMENT
AT11 SIO_SLP_S0# MPHYP_PWR_EN 1 2
GPP_B12/SLP_S0# AP15 SIO_SLP_S0# <17,38,51>
ESD Request:place near CPU side @ RC387 100K_0201_5%
PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S3# <23,36,37> VRALERT# 1 2
SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,36,49,52>
@ RC73 10K_0402_5%
B PCH_RSMRST#_AND AY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <36> 1 2 B
<14,42> PCH_RSMRST#_AND RSMRST# AN15 @ RC344 10K_0402_5%
H_CPUPWRGD_R@ RC77 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <36>
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <36>
RC78 1 2 60.4_0402_1% VCCST_PWRGD_CPU B65 BB17 +3.3V_ALW
<14,36,37> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_WLAN# <36,44> 1 2
SUSCLK
B6 GPD6/SLP_A# SIO_SLP_A# <36> @ RC48 1K_0402_5% SIO_SLP_LAN# 1 2
<14,36> SYS_PWROK PCH_PWROK BA20 SYS_PWROK BA15 @ RC68 10K_0402_5%
<53> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 SIO_PWRBTN# <14,36>
<36> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# AC_PRESENT <36>
@ RC444 1 2 0_0402_5% ME_SUS_PWR_ACK_R AR13 GPD0/BATLOW# JAPS1
<36> ME_SUS_PWR_ACK 1 2 SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK 1
<36> SUSACK# GPP_A15/SUSACK# +3.3V_ALW_PCH SIO_SLP_S3# 1
@ RC443 0_0402_5% AU11 PME# 2
BB15 GPP_A11/PME# AP16 INTRUDER# PAD~D @ T115 3 2
<23,36,37> PCH_PCIE_WAKE# +3.3V_ALW
AM15 WAKE# INTRUDER# SIO_SLP_S5# 4 3
<36> LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 MPHYP_PWR_EN SIO_SLP_S4# 5 4
+3.3V_1.8V_PGPPA AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# SIO_SLP_A# 6 5
<30> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# 7 6
SUSACK#_R +3.3V_ALW 7
1 2 connect to VCCMPHYGTAON_1P0 enable pin 8
@ RC550 1K_0402_5% 2 1 KBL-RU42_BGA1356 11 OF 20 PCH_RTCRST# 9 8
RC311 10K_0402_5% 10 9
11 10
SYS_RESET# <37,43> POWER_SW#_MB 12 11
SYS_RESET# 13 12
13
0.1U_0402_25V6
@ESD@ CC302
14
1 2 +3.3V_RUN SIO_SLP_S0# 15 14
RC215 15
1
@ RC290 0_0402_5% 16
16
10K_0402_5%
17
POP NO Support Deep sleep 17
2
18
DE-POP Support Deep sleep
2
+3.3V_RUN 18
@RC291
XDP_DBRESET# 19
PCH_DPWROK 1 2 PCH_RSMRST#_AND <14> XDP_DBRESET# 20 GND
GND
5
RC215 0_0402_5%
1
A NDS3@ +3.3V_RUN 1 A
P
B CVILU_CF4218FH0R0-05-NH
1
SYS_RESET#_R 1 SYS_RESET#
0.01UF_0402_25V7K
100K_0402_1%
1 4 2 ESD Request:place near CPU side

@ RC75 2 1 ME_RESET# 2 O RC224 1K_0402_5% CONN@
A
G
CC266
RC220
10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

2 1 74AHC1G09GW_TSSOP5
3
2 @ RC227 8.2K_0402_5%
2

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
CPU (6/14)
1.0
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCSTG
PCH_JTAG_TDI 1 2
RC81 51_0402_5%
PCH_JTAG_TDO 1 2
RC82 100_0402_5%
PCH_JTAG_TMS 1 2
UC1D CPU@ KBL-R U4+2 RC130 51_0402_5%
Rev_0.1
H_CATERR# D63
A54 CATERR#
D <36> PECI_EC 1 2 PROCHOT#_R C65 PECI D
<36,53,56> PROCHOT# PROCHOT# JTA G
RC84 499_0402_1% H_THERMTRIP# C63 CPU_XDP_TCLK 2 1 XDP_JTAGX
<37> H_THERMTRIP# A65 THERMTRIP# @ RC328 0_0402_5%
SKTOCC# B61 CPU_XDP_TCLK
CPU MISC PROC_TCK CPU_XDP_TCLK <14>
C55 D60 CPU_XDP_TDI
<14> XDP_OBS0_R D55 BPM#[0] PROC_TDI A61 CPU_XDP_TDO CPU_XDP_TDI <14>
<14> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TDO C60 CPU_XDP_TMS CPU_XDP_TDO <14>
T10 @ PAD~D XDP_OBS3_R BPM#[2] PROC_TMS CPU_XDP_TRST# CPU_XDP_TMS <14>
C56 B59
T11 @ PAD~D BPM#[3] PROC_TRST# CPU_XDP_TRST# <14> 1 2
+1.0V_VCCST SIO_EXT_SMI# A6 B56 PCH_JTAG_TCK @ RC86 51_0402_5%
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 PCH_JTAG_TDI PCH_JTAG_TCK <14>
2 1 H_CATERR# <30> TOUCH_SCREEN_PD# TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
<36,42> TOUCHPAD_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
@ RC79 49.9_0402_1%
2 1 H_THERMTRIP# <30> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
RC80 1K_0402_5% CPU_POPIRCOMP AT16 PCH_TRST# A59 XDP_JTAGX 1 2
PCH_POPIRCOMP PROC_POPIRCOMP JTAGX +1.0V_VCCSTG
AU16 @ RC87 1K_0402_5%
+1.0V_VCCSTG EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP
2 1 PROCHOT# OPC_RCOMP
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC83 1K_0402_5%
RC88
RC89
RC90
RC91
Service Mode Switch:
+3.3V_RUN Add a switch to ME_FWP signal to unlock the ME region and
2
RPC5 allow the ent ir e r egi on of t he SPI f l ash to be updat ed us i ng FP.T
8 1 TOUCHPAD_INTR#
7 2 +3.3V_ALW_PCH
6 3 CAM_MIC_CBL_DET#
5 4 ME_FWP 2 1 ME_FWP_SW
0_0402_5% @ RC221
2
10K_8P4R_5% PT,ST pop RC222 and SW1; MP pop RC221
@ RC222
C 2 1 CONTACTLESS_DET# 1K_0402_5% C
RC278 10K_0402_5%
2 1 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# PU changes to Module Side @ SW1
1
@ RC272 10K_0402_5% (Not confirm yet?) 20160311
2 1 AUD_PWR_EN 1
RC279 10K_0402_5% ME_FWP_SW 2
2 1 IR_CAM_DET# 3
<36> ME_FWP
RC345 100K_0402_5%
2 1 HOST_SD_WP# 4 G
RC292 10K_0402_5% 5
G
+3.3V_ALW_PCH ME_FWP PCH has internal 20K PD. SSAL120100_3P
2 1 SIO_EXT_SMI# (suspend power rail)
RC346 10K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE
UC1G CPU@ KBL-R U4+2
2 1 KB_DET# Rev_0.1
RC288 10K_0402_5%
LOW = ENABLE (DEFAULT) -->Pin3 & Pin2 short
AUDIO
HIGH = DISABLE (ME can update) -->Pin1 & Pin2 short
RC92 1 2 33_0402_5% HDA_SYNC BA22
<35> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
EMI@ RC93 33_0402_5%
<35> HDA_BIT_CLK_R 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
RC94 33_0402_5% SDIO / SDXC
<35> HDA_SDOUT_R ME_FWP_SWRC223 1 2 BA21 HDA_SDO/I2S0_TXD
1K_0402_5%
<35> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_MIC_CBL_DET# <30>
RC95
<35> HDA_RST#_R J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 TBT_CIO_PLUG_EVENT#
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 TBT_CIO_PLUG_EVENT# <23>
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET# +3.3V_ALW_PCH
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 HOST_SD_WP# CONTACTLESS_DET# <38>
AK7 GPP_G5/SD_CD# W8 AUD_PWR_EN HOST_SD_WP# <31> PANEL_SIZE_DET 1 2
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 SPK_DET# AUD_PWR_EN <35>
1 10K_0402_5% RC503
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP SPK_DET# <35>
B RF@ CC27 AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
47P_0402_50V8J GPP_A16/SD_1P8_SEL
2
IR_CAM_DET# H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
<30> IR_CAM_DET# PANEL_SIZE_DET D7 GPP_D19/DMIC_CLK0 SD_RCOMP
<30> PANEL_SIZE_DET GPP_D20/DMIC_DATA0
Close to RC93
KB_DET# D8 AF13
<42> KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
HDA_SDOUT_R GPP_D18/DMIC_DATA1
AW5
<35> SPKR GPP_B14/SPKR
1
RF@ CC334
82P_0402_50V8J KBL-RU42_BGA1356 7 OF 20
2 PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX H_THERMTRIP# PROCHOT#
0.1U_0402_25V6
@ESD@ CC303
0.1U_0402_25V6
@ESD@ CC304
0.1U_0402_25V6
@ESD@ CC305
0.1U_0402_25V6
@ESD@ CC312
0.1U_0402_25V6
@ESD@ CC310
Close to RC94
1
RF Request. Place near CPU side (Intel MOW)
2
HDA_RST# HDA_SDIN0 HDA_SDOUT
+3.3V_ALW_PCH +3.3V_ALW_PCH
2 1 SPKR 2 1 HDA_SDOUT
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% 1 1 1 ESD request,Place near CPU side.

RF@ CC331
RF@ CC332
RF@ CC333
2 2 2
A TOP SWAP STRAP Flash Descriptor Security override A
HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Internal 20k PD
CPU (7/14)
1.0
5 4 3 2 1
5 4 3 2 1
<14> CFG[0..19]
D D
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S CPU@ KBL-R U4+2
Rev_0.1 UC1T CPU@ KBL-R U4+2
RESERVED SIGNALS-1 Rev_0.1
2 1 CFG0 SPARE
@ RC113 10K_0402_1% CFG0 E68 BB68 1/5 2014WW52 MOW reserve to support
2 1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 Cannonlake-U PCH compatibility AW69 F6
CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6
@ RC112 10K_0402_1% close UC1.U11/U12 and <400mil
2 1 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 C11
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
@ RC110 10K_0402_1%
C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 RSVD_AW48 RSVD_B11 A11
CFG5
CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12
1U_0402_6.3V6K
CFG8 F71 H11 F52
HIGH(DEFAULT) No stall(Normal Operat i on) CFG9 G69 CFG[8] 1 RSVD_H11 RSVD_F52
LOW stall CFG[9]
CC222
CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T128
CFG12 H70 CFG[11] TP6 PAD~D @ T129 2 KBL-RU42_BGA1356 20 OF 20
CFG13 G71 CFG[12] @
CFG14 H69 CFG[13] D5
CFG15 G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C 2 1 CFG4 CFG[19] AW1 C
RC109 1K_0402_5% 2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 1 ITP_PMODE E8 RSVD_E1 E2
+1.0V_PRIM_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
BA68 BB3
T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
U42@ 1 2 F65 AW71
ZVM# for SKYLAKE-U 2+3e
G65 VSS_F65 RSVD_TP AW70 PAD~D @ T113
RC436 0_0402_5%
B VSS_G65 RSVD_TP PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# +1.0V_VCCST
@ RC120 100K_0402_5%
For Skylake , RC120 depop

KBL-RU42_BGA1356 19 OF 20 For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
A A
CPU (8/14)
1.0
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
@ RC2161 2 0_0603_5% +1.0V_PRIM_XDP CXDP@

CPU XDP XDP_PRSNT_PIN1 1
RC121
2 CFG3
0_0402_5%
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 +1.0V_PRIM_XDP CC30
1 2 2 1
<10> CPU_XDP_PREQ#
CPU_XDP_PREQ# 3 1 2 4 CFG17 UC8
CPU_XDP_PRDY# 5 3 4
0.1U_0201_10V6K
0.1U_0201_10V6K
6 CFG16 0.1U_0201_10V6K
<10> CPU_XDP_PRDY# 7 5 6
@ CC28
@ CC29
1 1 8 14
CFG0 9 7 8 10 CFG8 VCC
CFG1 11 9 10 12 CFG9 TDO_XDP 2 3 CPU_XDP_TDO <12>
13 11 12 14 1A 1B
D 2 2 CFG2 15 13 14 16 CFG10 D
CFG3 17 15 16 18 CFG11 1
19 17 18 20 1OE
CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 19 20 22 CFG19 TDI_XDP 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R 1 2 0_0402_5% XDP_OBS1 23 21 22 24 CFG18 2A 2B
CXDP@ RC240
<12> XDP_OBS1_R 25 23 24 26
Place near CFG4 27 25 26 28 CFG12 4
JXDP1 CFG5 29 27 28 30 CFG13 2OE
RC5 need to close to JCPU1 31 29 30 32 XDP_TMS 9 8 CPU_XDP_TMS <12>
CFG6 33 31 32 34 CFG14 3A 3B
@ RC123 1 2 1K_0402_5% CFG7 35 33 34 36 CFG15
<11,36,37> VCCST_PWRGD 37 35 36 38 10
<11,42> PCH_RSMRST#_ANDCXDP@ RC1241 2 H_VCCST_PWRGD_XDP 39 37 38 40 3OE
41 39 40 42 CLK_ITPXDP_P_R <11> TRST#_XDP 12 11
1K_0402_5% CPU_XDP_TRST# <12>
FIVR_EN <11,36> SIO_PWRBTN# 43 41 42 CLK_ITPXDP_N_R <11> 4A 4B
@ RC2171 2 0_0402_5% 44
CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 43 44 46 ITP_PMODE
RESET_OUT#_R 47 45 46 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC1281 2 0_0402_5% 48 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP 49 47 48 <36> RUNPWROK 4OE GND
@ RC1291 2 0_0402_5% 50
<11,36> SYS_PWROK 51 49 50 52 TDO_XDP 15
<8> DDR_XDP_WAN_SMBDAT 53 51 52 54 TRST#_XDP GND PAD
<8> DDR_XDP_WAN_SMBCLK 55 53 54 56 TDI_XDP
<12> PCH_JTAG_TCK CPU_XDP_TCLK 57 55 56 58 XDP_TMS
<12> CPU_XDP_TCLK 74CBTLV3126BQ_DHVQFN14_2P5X3
59 57 58 60
61 59 60 PCH_SPI_DO2_XDP <8>
61
62 63
GND GND
E-T_6601K-Y61N-04L
CONN@ +1.0V_VCCSTG
+1.0VS_VCCIO
CPU_XDP_TMS 1 2
2 1 FIVR_EN_R RC131 51_0402_5%
C RC132 150_0402_5% +3.3V_ALW_PCH +3.3V_ALW_DSW CPU_XDP_TDI 1 2 C
+1.0V_VCCST RC134 51_0402_5%
1.5K_0402_5%
1.5K_0402_5%
CPU_XDP_TDO
CXDP@ RC133
1 2
2
2
FIVR_EN
@ RC241
2 1 RC135 100_0402_5%
@ RC218 150_0402_5%
2 1 FIVR_EN CPU_XDP_TRST# 1 2
@ RC219 10K_0402_5% Place near JXDP1.48 @ RC136 51_0402_5%
1
1
CPU_XDP_TCLK 1 2
XDP_DBRESET# SIO_PWRBTN# RC139 51_0402_5%
PCH_SPI_DO_XDP
0.1U_0402_25V6
CXDP@ CC32
0.1U_0402_25V6
RESET_OUT#_R
1
0.1U_0402_25V6
CC269
@
1
+3.3V_RUN Place near JXDP1.41
1
XDP_TMS
@ CC33
1 2
2
@ RC228
PCH_JTAG_TMS <12>
0_0402_5%
2
2 1 XDP_DBRESET# TDI_XDP 1 2
2
@ RC229
PCH_JTAG_TDI <12>
RC137 3K_0402_5% 0_0402_5%
+1.0V_PRIM_XDP TDO_XDP 1 2
@ RC230 PCH_JTAG_TDO <12>
0_0402_5%
2 1 CPU_XDP_PREQ#
@ RC138 51_0402_5%
Place near JXDP1.47
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

B B
0.1U_0402_25V6
@ESD@ CC306
0.1U_0402_25V6
@ESD@ CC307
0.1U_0402_25V6
@ESD@ CC308
1
1
2
2
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
A A
CPU (9/14)
1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L CPU@ KBL-R U4+2 BSC(Backside cap) : Place on secondary side, underneath the package
Rev_0.1
CPU POWER 1 OF 4
A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
100_0402_1%
VCC_AM33 VCC_K37
2
AM35 K38
RC140
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
1
+VCC_CORE_G0 K32 E32 VCCSENSE
T122@ PAD~D RSVD VCC_SENSE VCCSENSE <53>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <53>
T123@ PAD~D RSVD
1
H_CPU_SVIDALRT#
100_0402_1%
B63
AB62 VIDALERT# A63 VIDSCLK
VCCOPC_AB62 VIDSCK VIDSCLK <53>
RC141
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
Remove (not support 2+3e) VCC_OPC_1P8_G61
20160303 AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE +1.0V_VCCSTG_R@ RC143 1 2 0_0603_5%
+1.0V_VCCSTG
AE62
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
C C
RF Request
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache) VIDSCLK 1 2
@RF@ CC321 33P_0402_50V8J
Place close CPU side
B B
+1.0V_VCCST
SVID ALERT
56_0402_1%
2
RC152
CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
1
2 1 H_CPU_SVIDALRT#
<53> VIDALERT_N
220_0402_5% RC153
+1.0V_VCCST
SVID DATA
2
100_0402_1%
CAD Note: Place the PU resistors close to CPU

RC157
RC208close to CPU 300 - 1500mils

1
A VIDSOUT A
<53> VIDSOUT
CPU (10/14)
1.0
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

+VCC_GT_+VCC_CORE
+VCC_GT
UC1M CPU@ KBL-R U4+2

D Rev_0.1 D
CPU POWER 2 OF 4
A48 KBL-U / KBL-R U4+2 N70

A53 VCCGT/VCCCORE_5 VCCGT N71
J43 VCCGT/VCCCORE_6 VCCGT R63
K48 VCCGT/VCCCORE_49 VCCGT R69
K50 VCCGT/VCCCORE_57 VCCGT R70
1 2 K52 VCCGT/VCCCORE_58 VCCGT R71
+VCC_GT VCCGT/RSVD_6 VCCGT
@ RC437 0_0402_5% T62
A58 VCCGT U65
+VCC_GT VCCGT VCCGT
A62 U68
A66 VCCGT VCCGT U71
AA63 VCCGT VCCGT W63
AC64 VCCGT VCCGT W70
AC65 VCCGT VCCGT W71
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)
AC66 VCCGT VCCGT Y62 +VCC_GT_+VCC_CORE
AC67 VCCGT VCCGT
AC68 VCCGT KBL-U / KBL-R U4+2 AK42
AC69 VCCGT VCCGTX_AK42/VCCCORE_12 AK43
C J53 VCCGT VCCGTX_AK46/VCCCORE_15 AK48 C
J55 VCCGT VCCGTX_AK48/VCCCORE_16 AK50
J56 VCCGT VCCGTX_AK50/VCCCORE_17 AL43
J58 VCCGT VCCGTX_AL43/VCCCORE_21 AL46
J60 VCCGT VCCGTX_AL46/VCCCORE_22 AL50
K53 VCCGT VCCGTX_AL50/VCCCORE_23 AM48
K55 VCCGT VCCGTX_AM48/VCCCORE_29 AM50
K56 VCCGT VCCGTX_AM50/VCCCORE_30 AM52
K58 VCCGT VCCGTX_AM52/VCCCORE_31 AK52 1 2
VCCGT VCCGTX_AK52/RSVD_5 +VCC_GT
K60 @ RC438 0_0402_5%
L62 VCCGT AK53
L63 VCCGT VCCGTX_AK53 AK55
+VCC_GTUS Reserve for soldering
L68 VCCGT VCCGTX_AK70 AL53
+VCC_GT L69 VCCGT VCCGTX_AL53 AL56
L70 VCCGT VCCGTX_AL56 AL60
L71 VCCGT VCCGTX_AL60 AM53
M62 VCCGT VCCGTX_AM53 AM56
100_0402_1%
VCCGT VCCGTX_AM56
2
N63 AM58
RC161
N64 VCCGT VCCGTX_AM58 AU58

N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
1
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<53> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
<53> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
B B
RC163
2
A A
CPU (11/14)
1.0
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM +VCC_SFR_OC
+VCCPLL_OC source 1 2
@ RZ119 0_0402_5%
+1.2V_MEM_CPUCLK +1.2V_MEM
UZ26
@ RC2311 2 0_0402_5% VDDQ: 8.45A 1
+1.2V_MEM 2 1 2 VIN1
CZ102 1U_0402_6.3V6K VIN2
7 6 1 2
D PSC VIN thermal VOUT CZ103 0.1U_0201_10V6K D
3
+5V_ALW VBIAS
VCCSTG_EN
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 2 4 5
@ RZ120 0_0402_5% ON GND
1 1 1 1
CC176
CC177
CC178
CC179
+3.3V_ALW TPS22961DNYR_WSON8
+1.0VS_VCCIO @ CZ104
2 2 2 2 UC1N CPU@ KBL-R U4+2 1 2
Rev_0.1
5
CPU POWER 3 OF 4 0.1U_0402_10V7K
AU23 AK28 1
P
AU28 VDDQ_AU23 VCCIO AK30 <11,44,50,51,52> PCH_PRIM_EN B 4
PSC AU35 VDDQ_AU28 VCCIO AL30 2 O
VDDQ_AU35 VCCIO <11,17,36,49,52> SIO_SLP_S4# A
G
AU42 AL42
BB23 VDDQ_AU42 VCCIO AM28 @ UZ34
3
VDDQ_BB23 VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 BB32 AM30 TC7SH08FU_SSOP5~D

VDDQ_BB32 VCCIO
CC294
CC295
CC296
BB41 AM42 +VCC_SA

+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
2 2 2 VDDQ_BB51 VCCSA AK25
PSC VCCSA G23
AM40 VCCSA G25
VDDQC VCCSA G27
VCCSA +1.0VS_VCCIO
10U_0402_6.3V6M
A18 G28
VCCST VCCSA J22
1 VCCSA
CC297
A22 J23
VCCSTG_A22 VCCSA J27
100_0402_1%
VCCSA
2
AL23 K23
2 VCCPLL_OC VCCSA K25
RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 +1.0VS_VCCIO
C PSC VCCPLL_K21 VCCSA K30 C
1
VCCSA
AM23 VCCIO_SENSE
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <51> PSC
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <51>
1U_0402_6.3V6K
1
H21
BSC VSSSA_SENSE
CC195
H20
VCCSA_SENSE
1
100_0402_1%
100_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 1 1 1 1
RC166
RC167
CC252
CC253
CC250
CC251
+VCC_SFR_OC
1U_0402_6.3V6K
1 1 2
+VCC_SA 2 2 2 2
CC199
RC168 100_0402_1%
2
+1.0V_VCCST
2@ PSC
2.2P_0402_50V8C
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
RF@ CC322
1 VSA_SEN- <53>
CC288
2 VSA_SEN+ <53>
CC202
S0 S0Ix S3
2
2
SIO_SLP_S0# HIGH LOW LOW
SIO_SLP_S3# HIGH HIGH LOW

RF Request
AND HIGH LOW LOW
B B
+1.0V_VCCST source +1.0V_VCCSTG source

+1.0V_VCCSTG +1.0V_VCCST
1 2
@ RZ151 0_0603_5%
pop option with UZ19
1
+1.0V_PRIM
PJP2
UZ19 PAD-OPEN1x1m
+1.0V_PRIM PJP1 2 1 1
UZ21 2 1 CZ105 1U_0402_6.3V6K 2 VIN1
+1.0V_VCCST VIN2
2 1 1
2
CZ100 1U_0402_6.3V6K 2 VIN1 +5V_ALW 7 6 +1.0V_VCCSTG_C1 2
VIN2 PAD-OPEN1x1m VIN thermal VOUT CZ106 0.1U_0201_10V6K
+5V_ALW 7 6 +1.0V_VCCST_C 1 2 3
VIN thermal VOUT CZ101 0.1U_0201_10V6K VBIAS
3 +3.3V_ALW 4 5
VBIAS ON GND
4 5
<11,17,36,49,52> SIO_SLP_S4# ON GND TPS22961DNYR_WSON8
4.4mohm/6A
5
TPS22961DNYR_WSON8
1 TR=12.5us@Vin=1.05V
VCCSTG_EN
P
<11,38,51> SIO_SLP_S0# B 4
4.4mohm/6A 2 O
TR=12.5us@Vin=1.05V <36,37,44,51> RUN_ON
UZ35 A G
TC7SH08FU_SSOP5~D
3
A A
@ RZ320 1 2 0_0402_5%
CPU (12/14)
1.0
5 4 3 2 1
5 4 3 2 1
close UC1.AL1 and <120mil

+1.0V_MPHYGT
+1.0V_PRIM +1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
close UC1.Y16 and <400mil
PCH PWR +3.3V_PGPPB
+1.0V_SRAM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 close UC1.AG15 and <120mil @ RC3091 2 0_0603_5%
+3.3V_PGPPC +3.3V_PGPPE
@ CC205
@ CC206
CC203
CC204
1U_0402_6.3V6K
1
+1.0V_APLLEBB
@ CC265
UC1O CPU@ KBL-R U4+2 close UC1.T16 and <400mil
2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.0V_MPHYAON Rev_0.1 1 1
@ CC207
@ CC208
CPU POWER 4 OF 4 @ RC3101 2 0_0603_5%
@ RC2991 2 0_0603_5% AB19 Must be +1.8V 2
D AB20 VCCPRIM_1P0 AK15 D
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2 2
P18 AG15
+1.0V_CLK6 VCCPRIM_1P0 VCCPGPPB Y16
close UC1.AF18 and <400mil VCCPGPPC
AF18 Y15 +3.3V_1.8V_PGPPG
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
@ RC3001 2 0_0402_5% AF19 T16 close UC1.AD15 and <400mil
V20 VCCPRIM_CORE VCCPGPPE AF16
VCCPRIM_CORE VCCPGPPF +1.8V_PGPPF
1U_0402_6.3V6K
V21 AD15 1
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG +3.3V_ALW_PCH
CC326
+1.0V_DTS
AL1 V19
@ RC3011 2 0_0402_5% DCPDSW_1P0 VCCPRIM_3P3_V19
K17 T1 +1.8V_PRIM 2
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
1U_0402_6.3V6K
L1 1
VCCMPHYAON_1P0
@ CC209
+1.0V_CLK1 AA1 close UC1.AA1 and <400mil
+1.0V_MPHYGT N15 VCCATS_1P8
VCCMPHYGT_1P0_N15 +RTC_CELL_PCH
1U_0402_6.3V6K
@ RC3021 2 0_0402_5% N16 AK17
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH 1 2
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
VCCMPHYGT_1P0_N17
CC212
P15 AK19 close UC1.V19 and <120mil
+1.0V_CLK3 P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2
47U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
1 1 1 1
@ CC210
@ RC3031 2 0_0402_5% K15 BB10 +DCPRTC
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
CC211
CC270
CC213
L15 close UC1.BB10 and <120mil
VCCAMPHYPLL_1P0
0.1U_0201_10V6K
A14 1
2 2 VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_APLL VCCAPLL_1P0
CC214
K19
VCCCLK2 +1.0V_CLK2
AB17
+1.8V_PRIM +1.0V_PRIM VCCPRIM_1P0_AB17 2
+1.8V_PGPPF Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
@ RC3041 2 0_0402_5% AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18
AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
+3.3V_1.8V_PGPPG VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5 RF Request
AJ19 A10
C +3.3V_VCCHDA VCCHDA VCCCLK6 +1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB C
@ RC234 1 2 0_0402_5% close UC1.A10 and <120mil
+1.0V_SRAM
1U_0402_6.3V6K
AJ16 AN11 CORE_VID0 <51> 1
+3.3V_SPI VCCSPI GPP_B0/CORE_VID0
@ CC216
close UC1.AF20 and <400mil AN13 CORE_VID1 <51>
+3.3V_ALW_PCH AF20 GPP_B1/CORE_VID1
AF21 VCCSRAM_1P0
+3.3V_ALW_PCH VCCSRAM_1P0 2
1.2P_0402_50V8C
1.2P_0402_50V8C
1.2P_0402_50V8C
1U_0402_6.3V6K
@ RC2351 2 0_0402_5% T19

1 VCCSRAM_1P0 Take care!!! Note1 on Page 19 1 1 1
@ CC217
T20
+1.0V_PRIM VCCSRAM_1P0
RF@ CC323
RF@ CC324
RF@ CC325
+3.3V_1.8V_PGPPA AJ21
2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21 2 2 2
LPC@ RC211 1 2 0_0402_5% AK20
VCCPRIM_1P0_AK20
+3.3V_1.8V_ESPI N18
+1.8V_PRIM VCCAPLLEBB_1P0
PJP4 close UC1.N18 and <120mil
1U_0402_6.3V6K
ESPI@ RC212 1 2 0_0402_5% 1 2 1 KBL-RU42_BGA1356 15 OF 20

CC218
PAD-OPEN1x1m
+3.3V_ALW_PCH +3.3V_PGPPB
2
@ RC3051 2 0_0402_5% Must be +1.8V for eSPI I/F
+3.3V_PGPPC +1.0V_PRIM +1.0V_CLK5 +3.3V_ALW_PCH
close UC1.AK17 and <120mil
@ RC3061 2 0_0402_5% +3.3V_ALW_DSW +3.3V_ALW_PCH
+1.0V_MPHYGT +1.0V_AMPHYPLL @ RC1711 2 0_0402_5%
close UC1.K15, UC1.L15 and <100mil close UC1.K15 and <120mil
+3.3V_PGPPD +3.3V_ALW
47U_0805_6.3V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
1 2 close UC1.L19 and <100mil 1 1 1
@ CC221
CC223
@ RC1691 2 0_0603_5% NDS3@ RC440 0_0402_5%
CC224
@ RC3071 2 0_0402_5% close UC1.K15 and <120mil
47U_0805_6.3V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
1 1 1 1 2
B 2 2 2 B
@ CC219
@ RC214 0_0402_5%
+3.3V_PGPPE
@ CC281
@ CC264
DS3@ QC7
LP2301ALT1G_SOT23-3
@ RC3081 2 0_0402_5% 2 2 2
1 2 +3.3V_ALW_DSW_R 1 3
S
@DS3@RC439 0_0402_5%
499K_0402_1%
8/28 schematic review
1
22U_0603_6.3V6M
@ CC279
22U_0603_6.3V6M
@ CC280
1 1
G
2
RC432
DS3@
+1.0V_APLL 2 2
2
+3.3V_ALW_PCH +1.0V_PRIM
+1.0V_MPHYGT source
100K_0402_5%
+3.3V_VCCHDA
2
0.1U_0402_25V6K
49.9K_0402_1%
RC431
DS3@
LC1 1 2 FBMA-11-100505-750A10T 0402 LC2 1 2 FBMA-11-100505-750A10T 0402
RC433
DS3@
0.1U_0201_10V6K
0.1U_0201_10V6K
@
47U_0805_6.3V6M
CC340
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1
RF@ CC215
CC313
RF@ CC335
@ CC225
CC314
1
+1.0V_PRIM +1.0V_MPHYGT
PJP3
2
2 2 2 2 2 1 2
RC439RC440RE536RC215RC441RC442
L2N7002WT1G_SC-70-3
PAD-OPEN1x3m
Support DS3 V X V X V X
close UC1.AJ19 and <400mil close UC1.V15 and <100mil Pop PJP35 & Depop UZ20/RZ83/CZ84
1
D
QC6
DS3@
No Support DS3 X V X V X V 2
VCCDSW_EN_GPIO <11>
G
S
3
+1.0V_PRIM +1.0V_CLK4 +1.0V_PRIM +1.0V_CLK2
'V' mean POP, 'X' mean DE-POP
A A
@ RC1731 2 0_0402_5% @ RC1701 2 0_0402_5%

47U_0805_6.3V6M
47U_0805_6.3V6M
close UC1.N20 and <100mil 1 1

@ CC226
@ CC220
2
close UC1.K19 and <100mil 2 Compal Electronics, Inc.
CPU (13/14)
1.0
5 4 3 2 1
5 4 3 2 1
Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

CPU@
CPU@ UC1Q KBL-R U4+2
UC1P KBL-R U4+2 Rev_0.1 CPU@ R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
Rev_0.1 GND 2 OF 3 UC1R KBL-R U4+2
GND 1 OF 3 Rev_0.1
AT63 BA49 GND 3 OF 3
A5 AL65 AT68 VSS VSS BA53 F8 L18
A67 VSS VSS AL66 AT71 VSS VSS BA57 G10 VSS VSS L2
A70 VSS VSS AM13 AU10 VSS VSS BA6 G22 VSS VSS L20
AA2 VSS VSS AM21 AU15 VSS VSS BA62 G43 VSS VSS L4
AA4 VSS VSS AM25 AU20 VSS VSS BA66 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU32 VSS VSS BA71 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU38 VSS VSS BB18 G5 VSS VSS N13
AB15 VSS VSS AM45 AV1 VSS VSS BB26 G52 VSS VSS N19
AD13 VSS VSS AM68 AW10 VSS VSS BB55 G63 VSS VSS P17
AD16 VSS VSS AM71 AW12 VSS VSS BB6 G66 VSS VSS P19
AD19 VSS VSS AM8 AW14 VSS VSS BB60 H15 VSS VSS P20
AD20 VSS VSS AN20 AW16 VSS VSS BB64 H18 VSS VSS P21
AD21 VSS VSS AN23 AW18 VSS VSS BB67 H71 VSS VSS R13
AD62 VSS VSS AN28 AW21 VSS VSS BB70 J11 VSS VSS R6
AD8 VSS VSS AN30 AW23 VSS VSS C1 J13 VSS VSS T15
AE64 VSS VSS AN32 AW26 VSS VSS C25 J25 VSS VSS T17
AE65 VSS VSS AN33 AW28 VSS VSS C5 J28 VSS VSS T18
AE66 VSS VSS AN35 AW30 VSS VSS D10 J32 VSS VSS T2
AE69 VSS VSS AN40 AW36 VSS VSS D18 J42 VSS VSS U10
AF1 VSS VSS AN42 AW38 VSS VSS D22 J8 VSS VSS U63
AF10 VSS VSS AN58 AW41 VSS VSS D25 K16 VSS VSS U64
AF15 VSS VSS AN63 AW43 VSS VSS D26 K18 VSS VSS U66
AF17 VSS VSS AP10 AW45 VSS VSS D30 K22 VSS VSS U67
AF63 VSS VSS AP23 AW51 VSS VSS D44 K64 VSS VSS V16
AG16 VSS VSS AP28 AW53 VSS VSS D45 K65 VSS VSS V17
AG17 VSS VSS AP32 AW55 VSS VSS D47 K66 VSS VSS V18
AG18 VSS VSS AP35 AW57 VSS VSS D48 K67 VSS VSS W13
C AG21 VSS VSS AP58 AW62 VSS VSS D6 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW64 VSS VSS D62 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW66 VSS VSS D66 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW8 VSS VSS D69 L17 VSS VSS Y21
AH63 VSS VSS AR11 AY66 VSS VSS E11 VSS VSS
AH64 VSS VSS AR15 B10 VSS VSS E15
AH67 VSS VSS AR16 B14 VSS VSS E18
AJ15 VSS VSS AR20 B18 VSS VSS E21
AJ18 VSS VSS AR23 B22 VSS VSS E46 KBL-RU42_BGA1356 18 OF 20
AK11 VSS VSS AR42 B39 VSS VSS E56
AK22 VSS VSS AR48 B58 VSS VSS F1
AK69 VSS VSS AR53 BA1 VSS VSS F23
AK8 VSS VSS AR55 BA10 VSS VSS F27
AL2 VSS VSS AR58 BA14 VSS VSS F28
AL35 VSS VSS AT2 BA23 VSS VSS F35
AL48 VSS VSS AT35 F68 VSS VSS F40
AL55 VSS VSS AT42 VSS VSS BA41
AL58 VSS VSS AT56 VSS
B AL64 VSS VSS AT58 B
VSS VSS
A A
CPU (14/14)
1.0
5 4 3 2 1
5 4 3 2 1
UD1 X76@ UD2 X76@

For LPDDR3
A3 P9 DDR_A_D3 A3 P9 DDR_A_D37 +0.6V_DDR_VTT
+1.8V_MEM VDD1 DQ0 DDR_A_D7 +1.8V_MEM VDD1 DQ0 DDR_A_D36
A4 N9 A4 N9
A5 VDD1 DQ1 N10 DDR_A_D5 A5 VDD1 DQ1 N10 DDR_A_D38 DDR_A_CAA0 RD1 2 1 68_0402_1%
A6 VDD1 DQ2 N11 DDR_A_D2 A6 VDD1 DQ2 N11 DDR_A_D34 DDR_A_CAA1 RD2 2 1 68_0402_1%
A10 VDD1 DQ3 M8 DDR_A_D0 A10 VDD1 DQ3 M8 DDR_A_D32 DDR_A_CAA2 RD3 2 1 68_0402_1%
U3 VDD1 DQ4 M9 DDR_A_D1 U3 VDD1 DQ4 M9 DDR_A_D39 DDR_A_CAA3 RD4 2 1 68_0402_1%
U4 VDD1 DQ5 M10 DDR_A_D4 U4 VDD1 DQ5 M10 DDR_A_D33 DDR_A_CAA4 2 1 <7> DDR_A_DQS#[0..7]
RD5 68_0402_1%
U5 VDD1 DQ6 M11 DDR_A_D6 U5 VDD1 DQ6 M11 DDR_A_D35 DDR_A_CAA5 RD6 2 1 68_0402_1%
VDD1 DQ7 DDR_A_D26 VDD1 DQ7 DDR_A_D42 DDR_A_CAA6 <7> DDR_A_D[0..63]
U6 F11 U6 F11 RD7 2 1 68_0402_1%
U10 VDD1 DQ8 F10 DDR_A_D28 U10 VDD1 DQ8 F10 DDR_A_D43 DDR_A_CAA7 RD8 2 1 68_0402_1%
VDD1 DQ9 DDR_A_D30 VDD1 DQ9 DDR_A_D40 DDR_A_CAA8 <7> DDR_A_DQS[0..7]
F9 F9 RD9 2 1 68_0402_1%
DQ10 F8 DDR_A_D31 DQ10 F8 DDR_A_D44 DDR_A_CAA9 RD10 2 1 68_0402_1%
DQ11 DDR_A_D27 DQ11 DDR_A_D46 DDR_A_CAB0 <7> DDR_A_CAA[0..9]
+1.2V_MEM A8 E11 +1.2V_MEM A8 E11 RD11 2 1 68_0402_1%
D
A9 VDD2 DQ12 E10 DDR_A_D29 A9 VDD2 DQ12 E10 DDR_A_D47 DDR_A_CAB1 RD12 2 1 68_0402_1%
D
D4 VDD2 DQ13 E9 DDR_A_D25 D4 VDD2 DQ13 E9 DDR_A_D41 DDR_A_CAB2 2 1 <7> DDR_A_CAB[0..9]
RD13 68_0402_1%
D5 VDD2 DQ14 D9 DDR_A_D24 D5 VDD2 DQ14 D9 DDR_A_D45 DDR_A_CAB3 RD14 2 1 68_0402_1%
D6 VDD2 DQ15 T8 DDR_A_D9 D6 VDD2 DQ15 T8 DDR_A_D52 DDR_A_CAB4 RD15 2 1 68_0402_1%
G5 VDD2 DQ16 T9 DDR_A_D12 G5 VDD2 DQ16 T9 DDR_A_D48 DDR_A_CAB5 RD16 2 1 68_0402_1%
H5 VDD2 DQ17 T10 DDR_A_D14 H5 VDD2 DQ17 T10 DDR_A_D55 DDR_A_CAB6 RD17 2 1 68_0402_1%
H6 VDD2 DQ18 T11 DDR_A_D15 H6 VDD2 DQ18 T11 DDR_A_D54 DDR_A_CAB7 RD18 2 1 68_0402_1%
H12 VDD2 DQ19 R8 DDR_A_D8 H12 VDD2 DQ19 R8 DDR_A_D53 DDR_A_CAB8 RD19 2 1 68_0402_1%
J5 VDD2 DQ20 R9 DDR_A_D13 J5 VDD2 DQ20 R9 DDR_A_D49 DDR_A_CAB9 RD20 2 1 68_0402_1%
J6 VDD2 DQ21 R10 DDR_A_D11 J6 VDD2 DQ21 R10 DDR_A_D51
K5 VDD2 DQ22 R11 DDR_A_D10 K5 VDD2 DQ22 R11 DDR_A_D50
K6 VDD2 DQ23 C11 DDR_A_D16 K6 VDD2 DQ23 C11 DDR_A_D63 +0.6V_DDR_VTT
K12 VDD2 DQ24 C10 DDR_A_D20 K12 VDD2 DQ24 C10 DDR_A_D62
L5 VDD2 DQ25 C9 DDR_A_D22 L5 VDD2 DQ25 C9 DDR_A_D56 DDR_A_CS#0 RD21 1 2 80.6_0402_1%
P4 VDD2 DQ26 C8 DDR_A_D18 P4 VDD2 DQ26 C8 DDR_A_D60 DDR_A_CS#1 RD22 1 2 80.6_0402_1%
P5 VDD2 DQ27 B11 DDR_A_D17 P5 VDD2 DQ27 B11 DDR_A_D58 DDR_A_ODT0 RD23 1 2 80.6_0402_1%
P6 VDD2 DQ28 B10 DDR_A_D21 P6 VDD2 DQ28 B10 DDR_A_D59 DDR_A_CKE0 RD24 1 2 80.6_0402_1%
U8 VDD2 DQ29 B9 DDR_A_D23 U8 VDD2 DQ29 B9 DDR_A_D61 DDR_A_CKE1 RD25 1 2 80.6_0402_1%
U9 VDD2 DQ30 B8 DDR_A_D19 U9 VDD2 DQ30 B8 DDR_A_D57 DDR_A_CKE2 RD79 1 2 80.6_0402_1%
VDD2 DQ31 VDD2 DQ31 DDR_A_CKE3 RD80 1 2 80.6_0402_1%
A11 R2 DDR_A_CAA0 A11 R2 DDR_A_CAB0

+1.2V_MEM VDDQ CA0 DDR_A_CAA1 +1.2V_MEM VDDQ CA0 DDR_A_CAB1 +0.6V_DDR_VTT
C12 P2 C12 P2
E8 VDDQ CA1 N2 DDR_A_CAA2 E8 VDDQ CA1 N2 DDR_A_CAB2
E12 VDDQ CA2 N3 DDR_A_CAA3 E12 VDDQ CA2 N3 DDR_A_CAB3 DDR_A_CLK#0 RD26 1 2 37.4_0402_1%
G12 VDDQ CA3 M3 DDR_A_CAA4 G12 VDDQ CA3 M3 DDR_A_CAB4 DDR_A_CLK0 RD27 1 2 37.4_0402_1%
H8 VDDQ CA4 F3 DDR_A_CAA5 H8 VDDQ CA4 F3 DDR_A_CAB5
H9 VDDQ CA5 E3 DDR_A_CAA6 H9 VDDQ CA5 E3 DDR_A_CAB6
H11 VDDQ CA6 E2 DDR_A_CAA7 H11 VDDQ CA6 E2 DDR_A_CAB7 +0.6V_DDR_VTT
J9 VDDQ CA7 D2 DDR_A_CAA8 J9 VDDQ CA7 D2 DDR_A_CAB8
J10 VDDQ CA8 C2 DDR_A_CAA9 J10 VDDQ CA8 C2 DDR_A_CAB9 DDR_A_CLK#1 RD30 1 2 37.4_0402_1%
K8 VDDQ CA9 K8 VDDQ CA9 DDR_A_CLK1 RD33 1 2 37.4_0402_1%
K11 VDDQ K11 VDDQ
L12 VDDQ L10 DDR_A_DQS0 L12 VDDQ L10 DDR_A_DQS4
VDDQ DQS0 DDR_A_DQS3 VDDQ DQS0 DDR_A_DQS5
N8
N12 VDDQ DQS1
G10
P10 DDR_A_DQS1
N8
N12 VDDQ DQS1
G10
P10 DDR_A_DQS6 Follow CRB 544250
VDDQ DQS2 DDR_A_DQS2 VDDQ DQS2 DDR_A_DQS7
C
R12
U11 VDDQ DQS3
D10 R12
U11 VDDQ DQS3
D10 CA - 68 ohm C
VDDQ
L11 DDR_A_DQS#0
VDDQ
L11 DDR_A_DQS#4
CS/CKE/ODT - 80.6 ohm
+1.2V_MEM
F2
VDDCA
DQS0#
DQS1#
G11 DDR_A_DQS#3
DDR_A_DQS#1 +1.2V_MEM
F2
VDDCA
DQS0#
DQS1#
G11 DDR_A_DQS#5
DDR_A_DQS#6
CLK - 37.4 ohm
G2 P11 G2 P11 Total
H3 VDDCA DQS2# D11 DDR_A_DQS#2 H3 VDDCA DQS2# D11 DDR_A_DQS#7
L2 VDDCA DQS3# L2 VDDCA DQS3# VDD :8x0.1uF,16x1uF,5x10uF
M2 VDDCA M2 VDDCA VDDCA: 8x1uF,3x10uF
VDDCA VDDCA +1.8V_MEM
For VDD1
DM0
L8
DM0
L8 VDD2:12x1uF,5x10uF
G8 G8 VDD1:8x1uF,5x10uF
A1 DM1 P8 A1 DM1 P8
A2 NC DM2 D8 A2 NC DM2 D8 VTT:8x1uF,2x22uF
A12 NC DM3 A12 NC DM3
NC NC
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
A13 A13 1 1 1 1 1 1 1
B1 NC B3 RD28 1 2 243_0402_1% B1 NC B3 RD31 1 2 243_0402_1%
NC ZQ0 NC ZQ0
CD41
CD42
CD43
CD52
CD74
CD75
CD76
B13 B4 RD29 1 2 243_0402_1% B13 B4 RD32 1 2 243_0402_1%
C4 NC ZQ1 C4 NC ZQ1
K9 NC K9 NC 2 2 2 2 2 2 2
R3 NC K3 DDR_A_CKE0 R3 NC K3 DDR_A_CKE2
T1 NC CKE0 K4 DDR_A_CKE1 DDR_A_CKE0 <7> T1 NC CKE0 K4 DDR_A_CKE3 DDR_A_CKE2 <7>
NC CKE1 DDR_A_CKE1 <7> NC CKE1 DDR_A_CKE3 <7>
T13 T13
U1 NC U1 NC
U2 NC L3 DDR_A_CS#0 U2 NC L3 DDR_A_CS#0
NC CS0# DDR_A_CS#1 DDR_A_CS#0 <7> NC CS0# DDR_A_CS#1
U12 L4 U12 L4
U13 NC CS1# DDR_A_CS#1 <7> U13 NC CS1#
NC NC
J3 DDR_A_CLK0 J3 DDR_A_CLK1 +1.2V_MEM
CK DDR_A_CLK#0 DDR_A_CLK0 <7> CK DDR_A_CLK#1 DDR_A_CLK1 <7> For VDD2
P3 J2 P3 J2
VSSCA CK# DDR_A_CLK#0 <7> VSSCA CK# DDR_A_CLK#1 <7>
M4 M4
J4 VSSCA J4 VSSCA
G4 VSSCA J8 DDR_A_ODT0 G4 VSSCA J8 DDR_A_ODT0
VSSCA ODT DDR_A_ODT0 <7> VSSCA ODT
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
G3 G3 1 1 1 1 1 1 1 1 1
F4 VSSCA F4 VSSCA
VSSCA VSSCA
CD31
CD32
CD33
CD30
CD68
CD69
CD70
CD71
CD72
D3 J11 D3 J11
VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA 2 2 2 2 2 2 2 2 2
T12 B2 T12 B2
B
T6 VSSQ VSS B5 T6 VSSQ VSS B5 B
R6 VSSQ VSS C5 R6 VSSQ VSS C5
P12 VSSQ VSS E4 P12 VSSQ VSS E4
VSSQ VSS 1 VSSQ VSS 1
N6 E5 CD10 N6 E5 CD11
M12 VSSQ VSS F5 M12 VSSQ VSS F5
M6 VSSQ VSS H2 0.047U_0402_16V7K M6 VSSQ VSS H2 0.047U_0402_16V7K
L9 VSSQ VSS J12 +VREFCA 2 L9 VSSQ VSS J12 +VREFCA 2
K10 VSSQ VSS K2 K10 VSSQ VSS K2
H10 VSSQ VSS L6 +VREFDQ_A H10 VSSQ VSS L6 +VREFDQ_A
VSSQ VSS VSSQ VSS +1.2V_MEM
For VDDCA
G9 M5 1 G9 M5 1
G6 VSSQ VSS N4 CD20 G6 VSSQ VSS N4 CD21
F12 VSSQ VSS N5 F12 VSSQ VSS N5
F6 VSSQ VSS R4 0.047U_0402_16V7K F6 VSSQ VSS R4 0.047U_0402_16V7K
E6 VSSQ VSS R5 2 E6 VSSQ VSS R5 2
VSSQ VSS VSSQ VSS
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
D12 T2 D12 T2 1 1 1 1 1 1
VSSQ VSS VSSQ VSS
CD5
CD6
CD1
CD2
CD3
CD4
C6 T3 C6 T3
B12 VSSQ VSS T4 B12 VSSQ VSS T4
B6 VSSQ VSS T5 B6 VSSQ VSS T5
VSSQ VSS VSSQ VSS 2 2 2 2 2 2
LPDDR3_FBGA178 LPDDR3_FBGA178
+0.6V_DDR_VTT +1.2V_MEM
For VDDQ
+DDR_VREF_CA +1.2V_MEM +VREFCA +DDR_VREF_A_DQ +1.2V_MEM +VREFDQ_A
For VTT
1
22U_0603_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD55
CD60
CD61
CD62
CD66
CD36
CD37
CD38
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD16
CD17
CD18
CD19
RD34 RD35
8.2K_0402_1% 8.2K_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2
A RD36 RD37 A
1 2 1 2
1 5.11_0402_1% 1 10_0402_1%
CD39 CD40
1
0.022U_0402_25V7K 0.022U_0402_25V7K
2 2 RD39
RD38
1
RD40
8.2K_0402_1%
RD41 8.2K_0402_1% DELL CONFIDENTIAL/PROPRIETARY
2
24.9_0402_1% 24.9_0402_1%
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LPDDR3
1.0
5 4 3 2 1
5 4 3 2 1
UD3 X76@ UD4 X76@

For LPDDR3
A3 P9 DDR_B_D15 A3 P9 DDR_B_D44
+1.8V_MEM VDD1 DQ0 DDR_B_D11 +1.8V_MEM VDD1 DQ0 DDR_B_D45 +0.6V_DDR_VTT
A4 N9 A4 N9
A5 VDD1 DQ1 N10 DDR_B_D8 A5 VDD1 DQ1 N10 DDR_B_D43
A6 VDD1 DQ2 N11 DDR_B_D9 A6 VDD1 DQ2 N11 DDR_B_D46 DDR_B_CAA0 RD42 2 1 68_0402_1%
A10 VDD1 DQ3 M8 DDR_B_D14 A10 VDD1 DQ3 M8 DDR_B_D41 DDR_B_CAA1 RD43 2 1 68_0402_1%
U3 VDD1 DQ4 M9 DDR_B_D10 U3 VDD1 DQ4 M9 DDR_B_D42 DDR_B_CAA2 RD44 2 1 68_0402_1%
VDD1 DQ7 DDR_B_D18 VDD1 DQ7 DDR_B_D51 DDR_B_CAA5 <7> DDR_B_DQS#[0..7]
U6 F11 U6 F11 RD47 2 1 68_0402_1%
U10 VDD1 DQ8 F10 DDR_B_D19 U10 VDD1 DQ8 F10 DDR_B_D50 DDR_B_CAA6 RD48 2 1 68_0402_1%
VDD1 DQ9 DDR_B_D21 VDD1 DQ9 DDR_B_D49 DDR_B_CAA7 <7> DDR_B_D[0..63]
F9 F9 RD49 2 1 68_0402_1%
DQ10 F8 DDR_B_D17 DQ10 F8 DDR_B_D53 DDR_B_CAA8 RD50 2 1 68_0402_1%
DQ11 DDR_B_D23 DQ11 DDR_B_D54 DDR_B_CAA9 <7> DDR_B_DQS[0..7]
+1.2V_MEM A8 E11 +1.2V_MEM A8 E11 RD51 2 1 68_0402_1%
D
A9 VDD2 DQ12 E10 DDR_B_D16 A9 VDD2 DQ12 E10 DDR_B_D55 DDR_B_CAB0 RD52 2 1 68_0402_1%
D
D4 VDD2 DQ13 E9 DDR_B_D20 D4 VDD2 DQ13 E9 DDR_B_D52 DDR_B_CAB1 2 1 <7> DDR_B_CAA[0..9]
RD53 68_0402_1%
D5 VDD2 DQ14 D9 DDR_B_D22 D5 VDD2 DQ14 D9 DDR_B_D48 DDR_B_CAB2 RD54 2 1 68_0402_1%
D6 VDD2 DQ15 T8 DDR_B_D3 D6 VDD2 DQ15 T8 DDR_B_D29 DDR_B_CAB3 2 1 <7> DDR_B_CAB[0..9]
RD55 68_0402_1%
G5 VDD2 DQ16 T9 DDR_B_D0 G5 VDD2 DQ16 T9 DDR_B_D24 DDR_B_CAB4 RD56 2 1 68_0402_1%
H5 VDD2 DQ17 T10 DDR_B_D2 H5 VDD2 DQ17 T10 DDR_B_D26 DDR_B_CAB5 RD57 2 1 68_0402_1%
H6 VDD2 DQ18 T11 DDR_B_D4 H6 VDD2 DQ18 T11 DDR_B_D27 DDR_B_CAB6 RD58 2 1 68_0402_1%
H12 VDD2 DQ19 R8 DDR_B_D1 H12 VDD2 DQ19 R8 DDR_B_D25 DDR_B_CAB7 RD59 2 1 68_0402_1%
J5 VDD2 DQ20 R9 DDR_B_D6 J5 VDD2 DQ20 R9 DDR_B_D28 DDR_B_CAB8 RD60 2 1 68_0402_1%
J6 VDD2 DQ21 R10 DDR_B_D5 J6 VDD2 DQ21 R10 DDR_B_D31 DDR_B_CAB9 RD61 2 1 68_0402_1%
K5 VDD2 DQ22 R11 DDR_B_D7 K5 VDD2 DQ22 R11 DDR_B_D30
K6 VDD2 DQ23 C11 DDR_B_D33 K6 VDD2 DQ23 C11 DDR_B_D57
K12 VDD2 DQ24 C10 DDR_B_D38 K12 VDD2 DQ24 C10 DDR_B_D63 +0.6V_DDR_VTT
L5 VDD2 DQ25 C9 DDR_B_D34 L5 VDD2 DQ25 C9 DDR_B_D56
P4 VDD2 DQ26 C8 DDR_B_D37 P4 VDD2 DQ26 C8 DDR_B_D60 DDR_B_CS#0 RD62 1 2 80.6_0402_1%
P5 VDD2 DQ27 B11 DDR_B_D39 P5 VDD2 DQ27 B11 DDR_B_D58 DDR_B_CS#1 RD63 1 2 80.6_0402_1%
P6 VDD2 DQ28 B10 DDR_B_D35 P6 VDD2 DQ28 B10 DDR_B_D59 DDR_B_ODT0 RD64 1 2 80.6_0402_1%
U8 VDD2 DQ29 B9 DDR_B_D32 U8 VDD2 DQ29 B9 DDR_B_D61 DDR_B_CKE0 RD65 1 2 80.6_0402_1%
U9 VDD2 DQ30 B8 DDR_B_D36 U9 VDD2 DQ30 B8 DDR_B_D62 DDR_B_CKE1 RD66 1 2 80.6_0402_1%
VDD2 DQ31 VDD2 DQ31 DDR_B_CKE2 RD81 1 2 80.6_0402_1%
DDR_B_CKE3 RD82 1 2 80.6_0402_1%
A11 R2 DDR_B_CAA0 A11 R2 DDR_B_CAB0
+1.2V_MEM VDDQ CA0 DDR_B_CAA1 +1.2V_MEM VDDQ CA0 DDR_B_CAB1
C12 P2 C12 P2
E8 VDDQ CA1 N2 DDR_B_CAA2 E8 VDDQ CA1 N2 DDR_B_CAB2 +0.6V_DDR_VTT
E12 VDDQ CA2 N3 DDR_B_CAA3 E12 VDDQ CA2 N3 DDR_B_CAB3
G12 VDDQ CA3 M3 DDR_B_CAA4 G12 VDDQ CA3 M3 DDR_B_CAB4 DDR_B_CLK#0 RD67 1 2 37.4_0402_1%
H8 VDDQ CA4 F3 DDR_B_CAA5 H8 VDDQ CA4 F3 DDR_B_CAB5 DDR_B_CLK0 RD68 1 2 37.4_0402_1%
H9 VDDQ CA5 E3 DDR_B_CAA6 H9 VDDQ CA5 E3 DDR_B_CAB6
H11 VDDQ CA6 E2 DDR_B_CAA7 H11 VDDQ CA6 E2 DDR_B_CAB7
J9 VDDQ CA7 D2 DDR_B_CAA8 J9 VDDQ CA7 D2 DDR_B_CAB8 +0.6V_DDR_VTT
J10 VDDQ CA8 C2 DDR_B_CAA9 J10 VDDQ CA8 C2 DDR_B_CAB9
K8 VDDQ CA9 K8 VDDQ CA9 DDR_B_CLK#1 RD69 1 2 37.4_0402_1%
K11 VDDQ K11 VDDQ DDR_B_CLK1 RD74 1 2 37.4_0402_1%
L12 VDDQ L10 DDR_B_DQS1 L12 VDDQ L10 DDR_B_DQS5
N8 VDDQ DQS0 G10 DDR_B_DQS2 N8 VDDQ DQS0 G10 DDR_B_DQS6
VDDQ DQS1 DDR_B_DQS0 VDDQ DQS1 DDR_B_DQS3
N12
R12 VDDQ DQS2
P10
D10 DDR_B_DQS4
N12
R12 VDDQ DQS2
P10
D10 DDR_B_DQS7 Follow CRB 544250
VDDQ DQS3 VDDQ DQS3
C U11
VDDQ
U11
VDDQ CA - 68 ohm C
F2 DQS0#
L11
G11
DDR_B_DQS#1
DDR_B_DQS#2 F2 DQS0#
L11
G11
DDR_B_DQS#5
DDR_B_DQS#6
CS/CKE/ODT - 80.6 ohm
+1.2V_MEM +1.2V_MEM
G2 VDDCA
VDDCA
DQS1#
DQS2#
P11 DDR_B_DQS#0
DDR_B_DQS#4
G2 VDDCA
VDDCA
DQS1#
DQS2#
P11 DDR_B_DQS#3
DDR_B_DQS#7
CLK - 37.4 ohm
H3 D11 H3 D11
L2 VDDCA DQS3# L2 VDDCA DQS3#
M2 VDDCA M2 VDDCA
VDDCA L8 VDDCA L8
DM0 G8 DM0 G8
A1 DM1 P8 A1 DM1 P8 +1.8V_MEM
NC DM2 NC DM2 For VDD1
A2 D8 A2 D8
A12 NC DM3 A12 NC DM3
A13 NC A13 NC
B1 NC B3 RD70 1 2 243_0402_1% B1 NC B3 RD72 1 2 243_0402_1%
NC ZQ0 NC ZQ0
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
@ CD112
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
B13 B4 RD71 1 2 243_0402_1% B13 B4 RD73 1 2 243_0402_1% 1 1 1 1 1 1 1
NC ZQ1 NC ZQ1
CD111
CD110
CD103
CD104
CD106
CD107
C4 C4
K9 NC K9 NC
R3 NC K3 DDR_B_CKE0 R3 NC K3 DDR_B_CKE2
T1 NC CKE0 K4 DDR_B_CKE1 DDR_B_CKE0 <7> T1 NC CKE0 K4 DDR_B_CKE3 DDR_B_CKE2 <7> 2 2 2 2 2 2 2
NC CKE1 DDR_B_CKE1 <7> NC CKE1 DDR_B_CKE3 <7>
T13 T13
U1 NC U1 NC
U2 NC L3 DDR_B_CS#0 U2 NC L3 DDR_B_CS#0
NC CS0# DDR_B_CS#1 DDR_B_CS#0 <7> NC CS0# DDR_B_CS#1
U12 L4 U12 L4
U13 NC CS1# DDR_B_CS#1 <7> U13 NC CS1#
NC NC
J3 DDR_B_CLK0 J3 DDR_B_CLK1
CK DDR_B_CLK#0 DDR_B_CLK0 <7> CK DDR_B_CLK#1 DDR_B_CLK1 <7>
P3 J2 P3 J2
VSSCA CK# DDR_B_CLK#0 <7> VSSCA CK# DDR_B_CLK#1 <7> +1.2V_MEM
M4 M4 For VDD2
J4 VSSCA J4 VSSCA
G4 VSSCA J8 DDR_B_ODT0 G4 VSSCA J8 DDR_B_ODT0
G3 VSSCA ODT DDR_B_ODT0 <7> G3 VSSCA ODT
F4 VSSCA F4 VSSCA
VSSCA VSSCA
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
@ CD102
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
D3 J11 D3 J11 1 1 1 1 1 1 1 1 1
VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B
CD100
CD101
CD98
CD105
CD109
CD108
CD113
CD114
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA
T12 B2 T12 B2 2 2 2 2 2 2 2 2 2
B
T6 VSSQ VSS B5 T6 VSSQ VSS B5 B
R6 VSSQ VSS C5 R6 VSSQ VSS C5
P12 VSSQ VSS E4 P12 VSSQ VSS E4
N6 E5 CD46 N6 E5 CD47
M12 VSSQ VSS F5 M12 VSSQ VSS F5
M6 VSSQ VSS H2 0.047U_0402_16V7K M6 VSSQ VSS H2 0.047U_0402_16V7K
L9 VSSQ VSS J12 +VREFCA 2 L9 VSSQ VSS J12 +VREFCA 2
K10 VSSQ VSS K2 K10 VSSQ VSS K2
H10 VSSQ VSS L6 +VREFDQ_B H10 VSSQ VSS L6 +VREFDQ_B
G9 VSSQ VSS M5 G9 VSSQ VSS M5
G6 N4 CD53 G6 N4 CD54 For VDDCA
F12 VSSQ VSS N5 F12 VSSQ VSS N5 +1.2V_MEM
F6 VSSQ VSS R4 0.047U_0402_16V7K F6 VSSQ VSS R4 0.047U_0402_16V7K
E6 VSSQ VSS R5 2 E6 VSSQ VSS R5 2
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 VSSQ VSS T3 C6 VSSQ VSS T3
VSSQ VSS VSSQ VSS
10U_0402_6.3V6M
10U_0402_6.3V6M
@ CD78
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
B12 T4 B12 T4 1 1 1 1 1 1
VSSQ VSS VSSQ VSS
CD83
CD81
CD82
CD79
CD80
B6 T5 B6 T5
VSSQ VSS VSSQ VSS
LPDDR3_FBGA178 LPDDR3_FBGA178 2 2 2 2 2 2
+DDR_VREF_B_DQ +1.2V_MEM +VREFDQ_B +0.6V_DDR_VTT For VTT +1.2V_MEM For VDDQ

1
RD75
22U_0603_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
@ CD96
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD63
CD56
CD57
CD58
CD64
CD93
CD90
CD99
CD92
CD97
CD89
CD95
CD86
CD91
CD85
CD84
CD87
CD88
CD94
8.2K_0402_1%
2
A RD76 A
1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 10_0402_1%
CD67
1
0.022U_0402_25V7K
2 RD77
1
RD78 8.2K_0402_1% DELL CONFIDENTIAL/PROPRIETARY

2
24.9_0402_1%
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LPDDR3
1.0
5 4 3 2 1
5 4 3 2 1
For passive level shifter from PS8339
+5V_RUN @ RV314 1 2 0_0201_5%
+5V_ALW @ RV313 1 2 0_0201_5%

+VHDMI_IN
0.1U_0201_10V6K
1
D D
1
CV39
+VHDMI_VCC
2
IN
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0402_10V6M
1
CV41
GND
OUT
@
CV40
2
2
3
HDMI connector
EMI@ LV31 1 2 4.3NH_LQG15HS4N3S02D_0.3NH
HDMI_L_TX_P2 JHDMI1
@EMI@ LV3 HDMI_RD_HPD 19
HP_DET
2
1 2 HDMI_TX_P2 1 4 EMI@ 18
<23> AR_DP1_P0 1 4 17 +5V
CV31 0.1U_0201_25V6K RV26
+3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC_GND
360_0402_5% SDA
1 2 HDMI_TX_N2 2 3 HDMI_CTRL_CLK 15
<23> AR_DP1_N0 2 3 14 SCL
CV32 0.1U_0201_25V6K
1
HCM1012GH900BP_4P HDMI_L_TX_N2 2 1 HDMI_CEC 13 Reserved
EMI@ LV32 1 2 4.3NH_LQG15HS4N3S02D_0.3NH 10K_0402_5% @ RV19 HDMI_L_CLKN 12 CEC
11 CK-
HDMI_L_CLKP 10 CK_shield
EMI@ LV33 1 2 4.3NH_LQG15HS4N3S02D_0.3NH HDMI_L_TX_N0 9 CK+
HDMI_L_TX_P1 8 D0-
@EMI@ LV6 HDMI_L_TX_P0 7 D0_shield
D0+
2
1 2 HDMI_TX_P1 1 4 EMI@ HDMI_L_TX_N1 6
<23> AR_DP1_P1 1 4 D1-
CV33 0.1U_0201_25V6K RV29 5
HDMI_L_TX_P1 4 D1_shield 20
360_0402_5% D1+ GND1
HDMI_TX_N1 HDMI_L_TX_N2
C <23> AR_DP1_N1
CV34
1 2
0.1U_0201_25V6K
2
2 3
3 3
2 D2- GND2
21
22 C
1
HCM1012GH900BP_4P HDMI_L_TX_N1 HDMI_L_TX_P2 1 D2_shield GND3 23
EMI@ LV34 1 2 4.3NH_LQG15HS4N3S02D_0.3NH D2+ GND4
CONCR_099A3AC19JBLCNF
CONN@
EMI@ LV35 1 2 4.3NH_LQG15HS4N3S02D_0.3NH
HDMI_L_TX_P0
@EMI@ LV9 LINK 099BKAC19YBLCNF DONE
2
1 2 HDMI_TX_P0 1 4 EMI@
<23> AR_DP1_P2 1 4
CV35 0.1U_0201_25V6K RV32
360_0402_5%
1 2 HDMI_TX_N0 2 3
<23> AR_DP1_N2 2 3
CV36 0.1U_0201_25V6K
1
HCM1012GH900BP_4P HDMI_L_TX_N0
EMI@ LV36 1 2 4.3NH_LQG15HS4N3S02D_0.3NH +3.3V_ALW
EMI@ LV37 1 2 15NH_LQG15HS15NJ02D_450MA_5%

HDMI_L_CLKP
1
@EMI@ LV12
2
1 2 HDMI_CLKP 1 4 EMI@ RV312
<23> AR_DP1_P3 1 4
CV37 0.1U_0201_25V6K RV35 10K_0201_5%
360_0402_5%
1 2 HDMI_CLKN 2 3
<23> AR_DP1_N3
2
CV38 0.1U_0201_25V6K 2 3
1
HCM1012GH900BP_4P HDMI_L_CLKN
DISPLAY_HPD_EC# <36>
1 2
EMI@ LV38 15NH_LQG15HS15NJ02D_450MA_5%
1
D
HDMI_RD_HPD 2 QV6
G L2N7002WT1G_SC-70-3
S
3
B +3.3V_RUN
B
1M_0402_5%
2
RV20
2
G
1
3 1 HDMI_RD_HPD 1 2
<23> AR_DP1_HPD
S
RV21 20K_0402_5%
QV5 HDMI_TX_P2 RV10 1 2 470_0402_1% HDMI_OB

L2N7002WT1G_SC-70-3 HDMI_TX_N2 RV11 1 2 470_0402_1%
HDMI_TX_P1 RV12 1 2 470_0402_1%
HDMI_TX_N1 RV13 1 2 470_0402_1%
HDMI_TX_P0 RV14 1 2 470_0402_1%
HDMI_TX_N0 RV15 1 2 470_0402_1%
HDMI_CLKP RV16 1 2 470_0402_1%
HDMI_CLKN RV17 1 2 470_0402_1%
+3.3V_RUN
1
D
RV18 1 2 10K_0402_5% 2 QV4
+3.3V_RUN
G L2N7002WT1G_SC-70-3
S
3
QV3A +VHDMI_VCC
2
1 6 HDMI_CTRL_CLK 1 2
<23> AR_DP1_CTRL_CLK
RV316 2.2K_0402_5%
5
A <23> AR_DP1_CTRL_DATA
4 3 HDMI_CTRL_DATA 1
RV315
2
2.2K_0402_5%
A
QV3B
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
+3.3V_TBT_LC For kirkwood
+3.3V_TBT_FLASH_R +3.3V_TBT_LC +3.3V_TBTA_FLASH
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
RT5
RT6
RT7
RT8
@ RT9 2 1 0_0402_5% +3.3V_ALW_PCH
0.1U_0201_10V6K
1
2
2
TBT_JTAG_TDI
3.3K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
3.3K_0402_5%
1
TBT_JTAG_TMS
CT1
0_0402_5% 2 1 @ RT10
TBT_JTAG_TCK
TBT_JTAG_TDO TBT_CIO_PLUG_EVENT# RT391 1 2 10K_0402_5%
RT1
RT2
RT3
RT4
2
1
1
Rework Debug Pin1 +3.3V_TBT_LC, Pin6 GND
UT2 TBT_PERST# 1 2 PCH_PLTRST#_AND Intel review for back-driver
TBT_ROM_CS# PCH_PLTRST#_AND <11,30,33,38,39>
D
TBT_ROM_HOLD#
8
7 VCC CS#
1
2 TBT_ROM_DO
NRTD3@ RT419 0_0402_5% 20160627 D
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP# 1 2 PCH_TBT_PERST# +3.3V_TBT

TBT_ROM_DI CLK WP#(IO2) PCH_TBT_PERST# <9>
5 4 @RTD3@ RT420 0_0402_5%
DI(IO0) GND
W25Q80DVSSIG_SO8 TBT_RESET_N_EC @ RT11 1 2 10K_0402_5%
Reserve for TBT RTD3 Support 20170726
UT1A
CT2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P1 Y23 V23 PCIE_PRX_C_DTX_P1 CT6 1 2 0.22U_0201_6.3V6K
<10> PCIE_PTX_DRX_P1 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_DTX_P1 <10>
CT3 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N1 Y22 V22 PCIE_PRX_C_DTX_N1 CT7 1 2 0.22U_0201_6.3V6K AR_DP1_CTRL_DATA RT12 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N1 <10> AR_DP1_CTRL_CLK RT13 1 2 2.2K_0402_5%
CT4 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P2 T23 P23 PCIE_PRX_C_DTX_P2 CT8 1 2 0.22U_0201_6.3V6K DPSNK0_DDC_CLK @ RT14 1 2 2.2K_0402_5%
PCIe GEN3
<10> PCIE_PTX_DRX_P2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N2 T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_C_DTX_N2 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P2 <10> DPSNK0_DDC_DATA
CT5 CT9 @ RT15 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N2 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N2 <10> DPSNK1_DDC_CLK @ RT336 1 2 2.2K_0402_5%
CT123 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P3 M23 K23 PCIE_PRX_C_DTX_P3 CT127 1 2 0.22U_0201_6.3V6K SNK0_CONFIG1 @ RT337 1 2 2.2K_0402_5% Need to check 20160310
<10> PCIE_PTX_DRX_P3 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N3 M22 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_C_DTX_N3 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P3 <10>
CT124 CT128
<10> PCIE_PTX_DRX_N3 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N3 <10>
SNK0_DDC_data/clk – connect to 2k PU only if
CT125 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P4 H23 F23 PCIE_PRX_C_DTX_P4 CT129 1 2 0.22U_0201_6.3V6K SRC0 is connected and support HDMI (a.i HDMI
<10> PCIE_PTX_DRX_P4 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_DTX_P4 <10>
CT126 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N4 H22 F22 PCIE_PRX_C_DTX_N4 CT130 1 2 0.22U_0201_6.3V6K or DP++ connector). Otherwise can be 100k PD.
<10> PCIE_PTX_DRX_N4 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N4 <10>
TBT_PERST# SNK1_DDC_data – connect to 100k PD. If SRC0
V19 L4
<11> CLK_PCIE_P5 T19 PCIE_REFCLK_100_IN_P PERST_N support HDMI, connect as SNK0_CFG1 to GPU
<11> CLK_PCIE_N5
AC5 PCIE_REFCLK_100_IN_N N16 TBT_PCIE_RBIAS 1 2
and/or appropriate AUX/DDC demux control
<11> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS RT34 3.01K_0402_1% SNK1_DDC_clk – connect to 100k PD.
CT10 1 2 0.1U_0201_10V6K CPU_DP1_P0_C AB7 R2 AR_DP1_P0 +3.3V_TBT_SX
<6> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P AR_DP1_N0 AR_DP1_P0 <22>
CT11 1 2 0.1U_0201_10V6K AC7 R1
<6> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N AR_DP1_N0 <22> AR_DP1_P0 1 2 AR_DP1_N0
CT12 1 2 0.1U_0201_10V6K CPU_DP1_P1_C AB9 N2 AR_DP1_P1 @ CT201 1P_0201_50V8C PCIE_WAKE#_AR RTD3@ RT455 1 2 10K_0402_5%
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P AR_DP1_N1 AR_DP1_P1 <22> AR_DP1_P1 AR_DP1_N1
CT13 1 2 0.1U_0201_10V6K AC9 N1 1 2
SOURCE PORT 0
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N AR_DP1_N1 <22> TBTA_I2C_INT
@ CT202 1P_0201_50V8C RT16 1 2 10K_0402_5%
SINK PORT 0
CT14 1 2 0.1U_0201_10V6K CPU_DP1_P2_C AB11 L2 AR_DP1_P2 AR_DP1_P2 1 2 AR_DP1_N2 TBTB_I2C_INT RT17 1 2 10K_0402_5%
CT15 1 2 0.1U_0201_10V6K AC11 L1 @ CT203 1P_0201_50V8C
<6> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N AR_DP1_N2 <22> AR_DP1_P3 AR_DP1_N3 TBT_I2C_SDA
1 2 RT18 1 2 2.2K_0402_5%
CT16 1 2 0.1U_0201_10V6K CPU_DP1_P3_C AB13 J2 AR_DP1_P3 CT204 1P_0201_50V8C TBT_I2C_SCL RT19 1 2 2.2K_0402_5%
CT17 1 2 0.1U_0201_10V6K AC13 J1
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N AR_DP1_N3 <22>
<6> CPU_DP1_AUXP CT18 1 2 0.1U_0201_10V6K CPU_DP1_AUXP_C Y11 W19 Closr UT1 TDOCK_BATLOW# RT20 1 2 10K_0402_5%
CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
C <6> CPU_DP1_AUXN CT19 1 2 0.1U_0201_10V6K W11
DPSNK0_AUX_N DPSRC_AUX_N
Y19 Intel Review TBT_SRC_CFG1 RT338 1 2 10K_0402_5% C
CPU_DP1_HPD AA2
DPSNK0_HPD DPSRC_HPD
G1 AR_DP1_HPD
AR_DP1_HPD <22>
request
<6> CPU_DP1_HPD TBT_CIO_PLUG_EVENT# @ RT371 1
1 2 DPSNK0_DDC_CLK Y5 N6 TBT_DP_RBIAS 1 2
20160324 RTD3_CIO_PWR_EN_R RT372 1
2 10K_0402_5%
2 10K_0402_5% Intel review request
<6> CPU_DP1_CTRL_CLK DPSNK0_DDC_DATA DPSNK0_DDC_CLK DPSRC_RBIAS
<6> CPU_DP1_CTRL_DATA
@ RT341 1
@ RT342
2 0_0402_5%
0_0402_5%
R4
DPSNK0_DDC_DATA U1 TBT_I2C_SDA
RT35 14K_0402_1%~D @RTD3@ for TBT RTD3
<6> CPU_DP2_P0
CT186 1 2 0.1U_0201_10V6K CPU_DP2_P0_C AB15 GPIO_0 U2 TBT_I2C_SCL TBT_I2C_SDA <25,26>
TBT_I2C_SCL <25,26>
20170810
CT187 1 2 0.1U_0201_10V6K CPU_DP2_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_ROM_WP# NRTD3@ TBTA_LSRX RT21 1 2 1M_0402_5%
LC GPIO
<6> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT PCIE_WAKE#_AR RT421 1 2 0_0402_5% TBTA_LSTX 1 2
RT22 1M_0201_5%
CT183 1 2 0.1U_0201_10V6K CPU_DP2_P1_C AB17 GPIO_3 W1 PCIE_WAKE#_AR @ PCIE_WAKE# <33,37,39> TBTA_HPD RT23 1 2 100K_0402_5%
<6> CPU_DP2_P1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# PI3WVR31313A has internal PD 120Kohm CPU_DP1_HPD
CT180 1 2 0.1U_0201_10V6K AC17 W2 RT422 1 2 0_0402_5% RT24 1 2 100K_0402_5%
<6> CPU_DP2_N1 DPSNK1_ML1_N GPIO_5 AR_DP1_CTRL_DATA TBT_CIO_PLUG_EVENT# <12> PCH_PCIE_WAKE# <11,36,37> RTD3_CIO_PWR_EN_R NRTD3@
Y1 @RTD3@ RT25 1 2 100K_0402_5%
CT185 1 2 0.1U_0201_10V6K CPU_DP2_P2_C AB19 GPIO_6 Y2 AR_DP1_CTRL_CLK AR_DP1_CTRL_DATA <22> RT454 1 2 0_0402_5% RTD3_USB_PWR_EN RT26 1 2 100K_0402_5%
SINK PORT 1
<6> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1 AR_DP1_CTRL_CLK <22> CLKREQ_PCIE#2_R <11> TBT_FORCE_PWR
CT179 1 2 0.1U_0201_10V6K AC19 AA1 RT27 1 2 10K_0402_5%
<6> CPU_DP2_N2 DPSNK1_ML2_N GPIO_8 TBTB_I2C_INT_R @ RT409 1 TBTB_I2C_INT TBT_TMU_CLK_OUT
J4 2 0_0402_5% RT28 1 2 100K_0402_5%
CPU_DP2_P3_C POC_GPIO_0 TBTA_I2C_INT_R @ RT410 1 2 0_0402_5% TBTA_I2C_INT TBTB_I2C_INT <26> PI3WVR31310 has internal PD 120Kohm CPU_DP2_HPD
CT182 1 2 0.1U_0201_10V6K AB21 E2
5/24 Change RT29 1 2 100K_0402_5%
POC GPIO
<6> CPU_DP2_P3 CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN TBTA_I2C_INT <25>
CT181 1 2 0.1U_0201_10V6K AC21 D4
<6> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR
H4
CT178 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C Y12 POC_GPIO_3 F2 TDOCK_BATLOW# TBT_FORCE_PWR <6> TBT_SRC_CFG1 @ RT30 1 2 1M_0402_5%
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SIO_SLP_S3# TBTB_LSTX
<6> CPU_DP2_AUXN CT184 1 2 0.1U_0201_10V6K W12 D2 RT31 1 2 1M_0402_5%
DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN_R 1 SIO_SLP_S3#
2 <11,36,37> TBTB_LSRX RT32 1 2 1M_0402_5%
CPU_DP2_HPD Y6 POC_GPIO_6 @ RT392 0_0402_5% RTD3_CIO_PWR_EN <9> TBTB_HPD RT33 1 2 100K_0402_5%
<6> CPU_DP2_HPD DPSNK1_HPD E1 TEST_EN 1 2
DPSNK1_DDC_CLK Y8 TEST_EN RT36 100_0402_5%
Misc
SNK0_CONFIG1 N4 DPSNK1_DDC_CLK AB5 TEST_PWRGD 1 2

DPSNK1_DDC_DATA TEST_PWR_GOOD RT37 100_0402_5%
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N_EC
DPSNK_RBIAS RESET_N TBT_RESET_N_EC <25,26,36> AR_DP1_CTRL_DATA
RT38 14K_0402_1% @ RT124 1 2 100K_0402_5%
TBT_JTAG_TDI Y4 D22 XTAL_25_IN 1 2 XTAL_25_IN_R AR_DP1_CTRL_CLK @ RT125 1 2 100K_0402_5%
TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT @ RT394 1 2 0_0402_5% XTAL_25_OUT_R DPSNK0_DDC_CLK @ RT126 1 2 100K_0402_5%
TBT_JTAG_TCK T4 TMS XTAL_25_OUT @ RT40 0_0402_5% DPSNK0_DDC_DATA @ RT127 1 2 100K_0402_5%
TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI DPSNK1_DDC_CLK RT128 1 2
TDO MISC EE_DI TBT_ROM_DO
YT1
SNK0_CONFIG1
100K_0402_5% Need to check 20160310
AC4 3 1 RT129 1 2 100K_0402_5%
1 2 TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS# OUT IN
RT39 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK 4 2
RSENSE EE_CLK GND GND
1 1
A15 B7 20PF 30PPM FL2500123Z
<29> TBTB_RX2P B15 PA_RX1_P PB_RX1_P A7 TBTA_RX2P <28>
CT20 CT21
<29> TBTB_RX2N PA_RX1_N PB_RX1_N TBTA_RX2N <28>
B 27P_0402_50V8J 27P_0402_50V8J B
A17 A9 2 2
<29> TBTB_TX2P B17 PA_TX1_P PB_TX1_P B9 TBTA_TX2P <28>
<29> TBTB_TX2N PA_TX1_N PB_TX1_N TBTA_TX2N <28>
A19 A11
<29> TBTB_TX1P B19 PA_TX0_P PB_TX0_P B11 TBTA_TX1P <28>
<29> TBTB_TX1N PA_TX0_N PB_TX0_N TBTA_TX1N <28>
TBT PORTS
B21 A13
<29> TBTB_RX1P PA_RX0_P PB_RX0_P TBTA_RX1P <28>
A21 B13 SWAP 0524
Port A
PORT B
<29> TBTB_RX1N PA_RX0_N PB_RX0_N TBTA_RX1N <28>

Type C SWAP 0524 Y15 Y16
<26> TBTB_AUXP W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 TBTA_AUXP <25>
<26> TBTB_AUXN PA_DPSRC_AUX_N PB_DPSRC_AUX_N TBTA_AUXN <25>
E20 E19
<26> TBTB_USB20_P PA_USB2_D_P PB_USB2_D_P TBTA_USB20_P <25>
D20 D19
<26> TBTB_USB20_N PA_USB2_D_N PB_USB2_D_N TBTA_USB20_N <25>
TBTB_LSTX A5 B4 TBTA_LSTX
<26> TBTB_LSTX TBTB_LSRX PA_LSTX PB_LSTX TBTA_LSRX TBTA_LSTX <25> Reserve for TBT RTD3 Support 20170808
POC
POC
A4 B5
<26> TBTB_LSRX TBTB_HPD PA_LSRX PB_LSRX TBTA_HPD TBTA_LSRX <25>
M4 G2 support TBT RTD3 & non TBT RTD3
<26,36> TBTB_HPD PA_DPSRC_HPD PB_DPSRC_HPD TBTA_HPD <25,36>
2 1 TBTB_USB2_RBIAS H19 F19 TBTA_USB2_RBIAS 1 2 RTD3@
RT41 499_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT42 499_0201_1% CT237
AC23 D6 Reserve for TBT RTD3 Support 20170807 +3.3V_ALW
THERMDA MONDC_SVR 0.1U_0402_25V6
AB23 support TBT RTD3 & non TBT RTD3 RTD3@ RT456 0_0402_5%
THERMDA A23 CLKREQ_PCIE#2_R 1 2 1 2
V18 ATEST_P B23 RTD3@ UT32
PCIE_ATEST ATEST_N +3.3V_ALW CT238 PCH_PCIE_WAKE# 1 2 1 5 RTD3@
AC1 E18 NO V+
TEST_EDM DEBUG USB2_ATEST
0.1U_0402_25V6 @RTD3@ RT445
PCIE_WAKE#
0_0402_5%
PCIE_WAKE#_AR_R
RT441
PCIE_WAKE#_AR
1 2 1 2 3 4 1 2
L15 W13 UT33 RTD3@ RT448 0_0402_5% NC COM
N15 FUSE_VQPS_64 MONDC_DPSNK_0 PCH_TBT_PERST# 1 2 1 5 RTD3@ 6 2 0_0402_5%
FUSE_VQPS_128 NO V+ <23,36> RTD3 SELECT IN GND
2
W18 RTD3@ RT444 0_0402_5% RT443 RTD3@
MONDC_DPSNK_1
1
C23 PCH_PLTRST#_AND 1 2 3 4 TBT_PERST#_R 1 2 TBT_PERST# RTD3@ TS5A3159ADCKR_SC70-6 RT440
C22 MONDC_CIO_0 AB2 RTD3@ RT446 0_0402_5% NC COM RT449 RTD3@
MONDC_CIO_1 MONDC_DPSRC 1M_0402_5%
6 2 0_0402_5% 10K_0402_5%
<23,36> RTD3 SELECT IN GND IN NC NO
2
ALPINE-RIDGE_BGA337 RTD3@
1
1
RTD3@ TS5A3159ADCKR_SC70-6 RT442
2
RT447 RTD3@ 1M_0402_5%
10K_0402_5% L COM X
A
1
IN NC NO A
2
H X COM
L COM X
H X COM
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT TBT-AR-DP(1/2) DP, PCIE
5 4 3 2 1
A B C D E
For Steamboat 12/14 &kirkwood,For AR
+0.9V_TBT_DP +0.9V_TBT_USB
1U_0201_6.3V6M +3.3V_ALW
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
PJP6
+3.3V_VDD_PIC @ +3.3V_TBT_SX +3.3V_TBT
1 1 1 1 1 1 1 1 1 1 2 1 2
CT25
CT26
CT27
CT28
CT29
CT30
CT31
CT32
CT33
1 @ RT48 0_0603_5% VCC3P3_SVR:3.3V @ 0.6A max 1
PAD-OPEN1x1m +3.3V_TBT_LC 1 2
@ RT49 0_0603_5%
2 2 2 2 2 2 2 2 2 +3.3V_TBT_S0
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CT44
CT45
CT46
CT47
1 1 1 1 1 1 1
CT41
CT42
<BOM Structure> CT43

2 2 2 2 2 2 2
R13
+0.9V_TBT_PCIE +0.9V_TBT_CIO +0.9V_TBT_DP
R6
H9
F8
UT1B
L8 A2 VCC0P9_SVR:0.9V @ 1.8A max
VCC3P3_SX
VCC3P3_S0
VCC3P3A
VCC3P3_LC
L11 VCC0P9_DP VCC3P3_SVR A3
VCC0P9_DP VCC3P3_SVR Minimum of 4vias must be used
L12 B3
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
M8 VCC0P9_DP VCC3P3_SVR +0.9V_TBT_SVR
T11 VCC0P9_DP
1 1 1 1 1 1 1 VCC0P9_DP
CT34
CT35
CT36
CT37
CT38
CT39
CT40
T12 L9
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L6 VCC0P9_DP VCC0P9_SVR M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
2 2 2 2 2 2 2
CT48
CT49
CT50
CT51
CT52
CT53
CT54
V11 E13
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_TBT_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE
N19 VCC0P9_ANA_PCIE_1 C1 +TBT_SVR_IND LT1 1 2 0.6UH_MND-04ABIR60M-XGL_20%
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
VCC0P9_ANA_PCIE_2 SVR_IND
CT55
CT56
CT57
M18 D1 1 1 1
+0.9V_TBT_USB N18 VCC0P9_ANA_PCIE_2 SVR_IND Share Same GND plane
VCC
VCC0P9_ANA_PCIE_2 with SVR_VSS of AR
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
+0.9V_TBT_CIO VCC0P9_USB SVR_VSS B2 Intel review request
SVR_VSS
R8
R9 VCC0P9_CIO +0.9V_TBT_LVR_OUT
Change 10U*4 to
SVR_VSS:Minimum of 4 vias must be used.
2
R11 VCC0P9_CIO
VCC0P9_CIO
47U*3 2
R12 F18 20160324
1U_0201_6.3V6M
1U_0201_6.3V6M
VCC0P9_CIO VCC0P9_LVR H18
10U_0402_6.3V6M
10U_0402_6.3V6M
+3.3V_RUN +3.3V_TBT +VCC3V3_ANA_PCIE L16 VCC0P9_LVR J11
+VCC3V3_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
CT59
CT60
CT61
CT62
H11
1U_0201_6.3V6M
1U_0201_6.3V6M
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
PJP5 A6 V5
@ 1 1 VSS_ANA VSS_ANA 2 2 2 2
CT63
CT64
1 2 A8 V6
A10 VSS_ANA VSS_ANA V8
PAD-OPEN1x1m A12 VSS_ANA VSS_ANA V9
2 2 A14 VSS_ANA VSS_ANA V15
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B16 VSS_ANA VSS_ANA Y9
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
GND
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
3 3
F9 VSS_ANA VSS_ANA AC16
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
+3.3V_TBT_S0 change pn to SHI0000N600 +3.3V_TBT H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
1 2 H12 VSS_ANA VSS E6
LT2 1UH_LQM18NN1R0K00D_10% H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
47U_0603_6.3V6M
47U_0603_6.3V6M
1U_0402_6.3V6K
VSS_ANA VSS
CT67
1 1 H16 H5
VSS_ANA VSS
1
CT68
CT69
H20 H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
2
2 2 J19 VSS_ANA VSS J13

J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
4 4
PROPRIETARY NOTE:
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT TBT-AR-SP(2/2) PWR,VSS
A B C D E
5 4 3 2 1
+3.3V_VDD_PIC
For Non-AR port1
2
1 6 UPD1_SMBUS_CLK_Q
<36> UPD2_SMBCLK
@ QT1A
@ RT58 1 2 0_0402_5%
5
4 3 UPD1_SMBUS_DAT_Q
<36> UPD2_SMBDAT
@ QT1B
@ RT59 1 2 0_0402_5%
D D
5/24 Change ROM From TBTA to TBTB

@ RT60 1 2 0_0402_5% UPD1_SMBINT#_R
<36> UPD2_SMBINT#
5/24 Del FLASH Conn.
+TBTA_Vbus_1
1
@ RT397
+5V_ALW
PJP8 0_0402_5%
TI is 1x47uf+1x0.1uf
2 1
2
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
PAD-OPEN 1x3m
1 1 1 1
CT75
CT76
CT77
CT78
2 2 2 2
+TBTA_LDO_BMC 5/24 Change RT63 to @

+VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
+VCC1V8A_TBTA_LDO
RT65 @ 1 2 0_0402_5%
+TBTA_SENSE
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
2.2U 16V K X5R 0402
2.2U 16V K X5R 0402
2.2U 16V K X5R 0402

1 1 1
TI is 3x1uf +3.3V_ALW 1 2
+5V_ALW_PDA
CT71
CT72
CT73
+3.3V_TBTA_FLASH @ RT450 0_0402_5%
1 2
1U_0402_10V6K
2 2 2 1
CT74
@ RT451 0_0402_5% RT63 1 @ 2 0_0402_5%
C C
2
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
10K_0402_1% UT5
RT76 F1
VIN_3V3
VDDIO
LDO_1V8A
PP_CABLE
PP_5V0
PP_5V0
PP_5V0
PP_5V0
SENSEP
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
I2C_ADDR
1
PD1_GPIO8 D1
<23,26> TBT_I2C_SDA I2C_SDA1 +TBTA_Vbus_1
D2
<23,26> TBT_I2C_SCL
1
+3.3V_TBTA_FLASH C1 I2C_SCL1
<23> TBTA_I2C_INT I2C_IRQ1_N TI has 1x1uf
RT377
43K_0402_1% +3.3V_ALW
3.3K_0402_5% 2 1 RT66 @ UPD1_SMBUS_DAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
3.3K_0402_5% 2 1 RT67 @ UPD1_SMBUS_CLK_Q B5 I2C_SDA2 H11
2
1
UPD1_SMBINT#_R I2C_SCL2 VBUS
CT82
10K_0402_5% 2 1 RT68 @ B6 J10
1U_0603_25V6K
I2C_IRQ2_N VBUS J11
10U_0603_6.3V6M
1U_0402_10V6K
MUX1_FLIP_SEL_R VBUS 1 1
CT83
0_0402_5% 2 1 @ RT69 B2 K11
2
EN_PD_HV_1_R GPIO0 VBUS
CT84
0_0402_5% 2 1 @ RT70 C2
<57> EN_PD_HV_1 PD1_GPIO2 GPIO1
1M_0402_5% 2 1 RT71 D10
0_0402_5% 2 1 @ RT72 AC1_DISC#_R G11 GPIO2 2 2
<56,57> AC1_DISC# TBTA_HPD_R GPIO3
0_0402_5% 2 1 @ RT73 C10
<23,36> TBTA_HPD OTG_ID1 GPIO4
0_0402_5% 2 1 @ RT74 E10 H2
0_0402_5% 2 1 @ RT75 PD1_GPIO6 G10 GPIO5 VOUT_3V3
0_0402_5% 2 1 @ RT339 PD1_GPIO7 D7 GPIO6
PD1_GPIO8 H6 GPIO7
5/24 Change GPIO8 G1
RT218 2 1 100K_0402_5% TBTA_ROM_CLK_PD A3 LDO_3V3
RT219 2 1 100K_0402_5% TBTA_ROM_DI_PD B4 SPI_CLK
0_0402_5% 2 1 @ RT401 PD1_USB20_P RT220 2 1 100K_0402_5% TBTA_ROM_DO_PD A4 SPI_MOSI
<10> USB20_P3 PD1_USB20_N TBTA_ROM_CS#_PD SPI_MISO
0_0402_5% 2 1 @ RT402 CHECK +3.3V_TBTA_FLASH RT221 2 1 3.3K_0402_0.5% B3 K6 TBTA_TOP_P <28>
<10> USB20_N3 SPI_SS_N C_USB_TP L6 TBTA_TOP_N <28>
0_0402_5% 2 1 @ RT403 PD1_USB20_P PD1_USB20_P L5 C_USB_TN
<23> TBTA_USB20_P PD1_USB20_N PD1_USB20_N USB_RP_P
0_0402_5% 2 1 @ RT404 K5
<23> TBTA_USB20_N UART_MOSI USB_RP_N
1 2
<26> UART_MOSI_R @ RT345 0_0402_5% RT83 @ 2 1 0_0402_5% E2 K7
UART_MISO UART_TX C_USB_BP TBTA_BOT_P <28>
1 2 F2 L7 TBTA_BOT_N <28>
<26> UART_MISO_R UART_RX C_USB_BN
@ RT346 0_0402_5%
0_0402_5% 2 1 @ RT84 F4
Reserve Share ROM solution 0_0402_5% 2 1 @ RT85 G4 SWD_DATA
Because TPS65982D has internal ROM SWD_CLK L9 @ RT395 1 2 0_0402_5% @ RT104 1 2 0_0402_5%
UART_MOSI C_CC1 L10 TBTA_CC1 <28>
2 1 @ RT396 1 2 0_0402_5% @ RT105 1 2 0_0402_5%
C_CC2 WHEN TBTA_CC2 <28>
@ RT81 100K_0402_5% CONNECT BUSPOWERZ TO GND,
2 1 UART_MISO RT86 2 1 1M_0402_5% TBTA_MRESET E11 CT86 1 2 1000P_0402_50V7K
MRESET
CONNECT ALSO RPD_Gn to C_CCn
B @ 1M_0402_5% RT82 B
DIV = R2/(R1+R2) K9 CT85 1 2 1000P_0402_50V7K
Factory Device Description TBTA_LSTX 1 2 TBTA_LSTX_R L4 RPD_G1 K10
Configuration <23> TBTA_LSTX TBTA_LSRX @ RT87 1 2 0_0402_5% TBTA_LSRX_R K4 TBT_LSTX/R2P RPD_G2 TI has 2x220pf +3.3V_TBTA_FLASH
DIV_min DIV_max <23> TBTA_LSRX TBT_LSRX/P2R
@ RT88 0_0402_5%
UFP only MUX1_FLIP_SEL/MUX1_USB_SEL control by: TBTA_LSTX 1 2 TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%
5V @0.9A Sink capability with "Ask for Max/" for GPIO: Pop RT69,RT90;Depop RT375,RT376 TBTA_LSRX @ RT89 1 2 0_0402_5% TBTA_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTA_DBG_CTL2 RT107 1 2 10K_0402_5%
0.00 0.08 0 anything from 0.9 -3.0A I2C:Depop RT69,RT90;pop RT375,RT376 @ RT90 0_0402_5% DIG_AUD_N/DEBUG4 DEBUG_CTL2
TBT Alternate Modes not supported
DisplayPort Alternate Modes not supported @ RT375 1 2 0_0402_5% UPD1_SMBUS_CLK_Q 1 2 TBTA_DEBUG1 L2
TI VID supported UPD1_SMBUS_DAT_Q @ RT92 1 TBTA_DEBUG2 DEBUG1
@ RT376 1 2 0_0402_5% 2 0_0402_5% K2
@ RT93 0_0402_5% DEBUG2
UFP only K8 TBTA_SBU1_R 1 2
5V @0.9A Sink capability with "Ask for Max/" for TBTA_AUXP_C C_SBU1 TBTA_SBU1 <28>
Route in pass through manner so AUX can be snooped by 546 <23> TBTA_AUXP CT80 1 2 0.1U_0201_10V6K J1 @ RT108 0_0402_5%
0.10 0.18 1 anything from 0.9 -3.0A CT81 1 2 0.1U_0201_10V6K TBTA_AUXN_C J2 AUX_P L8 TBTA_SBU2_R 1 2
TBT Alternate Modes not supported <23> TBTA_AUXN AUX_N C_SBU2 @ RT109
TBTA_SBU2 <28>
0_0402_5%
DisplayPort Alternate Modes -Sink, C and D pin configuration +3.3V_TBTA_FLASH
TI VID supported F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R @ RT110 1 2 0_0402_5%
UFP only +3.3V_TBTA_FLASH RESET_N TBT_RESET_N_EC <23,26,36>
HRESET
0.20 0.28 2 5V @3.0A Source capability 2 1 TBTA_AUXN_C TBTA_ROSC G2
TBT Alternate Modes not supported 100K_0201_5% RT95 R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
DisplayPort Alternate Modes not supported

15K_0402_1%
SS
0.1U_0402_25V6
1
2
TI VID supported TBTA_AUXP_C @
CT205
2 1
0_0402_5%
RT100
100K_0201_5% RT96 TPS65982DCZQZR_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT98
UFP only
0.30 0.38 3 5V @3.0A Source capability 2
6/20 PN:SA0000AX700
2

1
DisplayPort Alternate Modes -Sink, C and D pin configuration

TI VID supported +VCC1V8D_TBTA_LDO 1 2
100K_0402_5%
@ RT97 0_0402_5%
0_0402_5%
DRP 1
1
5V @0.9-3.0A Sink capability
RT101
@ RT103
CT87
0.40 0.48 5V @3.0A Source capability @ RT99
4 TBT Alternate Modes not supported 0.22U_0402_16V7K
DisplayPort Alternate Modes not supported 0_0402_5% 2
2
2
TI VID supported
Accepts data and power role swaps, but does not
2
initiate.
DRP
A 5V @0.9-3.0A Sink capability
Need Link TPS65982D A
5V @3.0A Source capability
0.50 0.58 5 TBT Alternate Modes not supported
DisplayPort Alternate Modes - Source, C, D, and E
pin configurations.
TI VID supported
Accepts power role swaps but will not initiate.
Accepts data role swap to UFP and can initiate.
DRP
0.60 0.68 6
pin configurations.
TI VID supported
Accepts power role swaps but will not initiate. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Accepts data role swap to DFP and can initiate. BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
[Type C]PD Controller TI
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles. PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-F292P 1.0

5 4 3 2 1
5 4 3 2 1
DIV = R2/(R1+R2)
Factory Device Description +3.3V_TBTB_FLASH +3.3V_TBTB_FLASH
+3.3V_VDD_PIC
For Non-AR port2 kirkwood
DIV_min DIV_max Configuration
2
.1U_0402_16V7K
2
2
UPD2_SMBUS_CLK_Q
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
CT70
UFP only 1 6
1
5V @0.9A Sink capability with "Ask for Max/" for <36> UPD1_SMBCLK
0.00 0.08 0 anything from 0.9 -3.0A @ QT2A
RT50
RT51
RT52
RT53
2
DisplayPort Alternate Modes not supported @ RT150 1 2 0_0402_5%
TI VID supported 6/1 PN:SA000095R10
5
UT6
UFP only 8 1 TBTB_ROM_CS#_PD_R
5V @0.9A Sink capability with "Ask for Max/" for TBTB_ROM_HOLD#_PD 7 VCC CS# 2 TBTB_ROM_DO_PD_R 4 3 UPD2_SMBUS_DAT_Q
anything from 0.9 -3.0A TBTB_ROM_CLK_PD_R HOLD#(IO3) DO(IO1) TBTB_ROM_WP#_PD <36> UPD1_SMBDAT
0.10 0.18 1 6 3
TBT Alternate Modes not supported TBTB_ROM_DI_PD_R 5 CLK WP#(IO2) 4 @ QT2B
DisplayPort Alternate Modes -Sink, C and D pin configuration DI(IO0) GND DMN66D0LDW-7_SOT363-6
TI VID supported @ RT151 1
W25Q80DVSSIG_SO8 2 0_0402_5%
D D
UFP only
0.20 0.28 2 5V @3.0A Source capability TBTB_ROM_CLK_PD_R @ RT54 2 1 0_0402_5% TBTB_ROM_CLK_PD
TBT Alternate Modes not supported TBTB_ROM_DI_PD_R @ RT55 2 1 0_0402_5% TBTB_ROM_DI_PD @ RT156 1 2 0_0402_5% UPD2_SMBINT#_R
TBTB_ROM_DO_PD_R <36> UPD1_SMBINT#
DisplayPort Alternate Modes not supported @ RT56 2 1 0_0402_5% TBTB_ROM_DO_PD
TI VID supported TBTB_ROM_CS#_PD_R @ RT57 2 1 0_0402_5% TBTB_ROM_CS#_PD
UFP only
0.30 0.38 3 5V @3.0A Source capability
DisplayPort Alternate Modes -Sink, C and D pin configuration +TBTB_Vbus_1
TI VID supported 5/24 Change ROM From TBTA to TBTB
DRP
0.40 0.48 5V @3.0A Source capability
4 TBT Alternate Modes not supported +5V_ALW
1
DisplayPort Alternate Modes not supported @ RT398
TI VID supported
Accepts data and power role swaps, but does not PJP10
TI is 1x47uf+1x0.1uf 0_0402_5%
initiate.
2 1
2
DRP
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
5V @0.9-3.0A Sink capability PAD-OPEN 1x3m
1 1 1 1
CT142
CT143
CT144
CT145
0.50 0.58 5 TBT Alternate Modes not supported
pin configurations. 2 2 2 2
TI VID supported
Accepts power role swaps but will not initiate.
Accepts data role swap to UFP and can initiate. 5/24 Change RT159 to non@
DRP
5V @0.9-3.0A Sink capability +TBTB_LDO_BMC
5V @3.0A Source capability +VCC1V8D_TBTB_LDO @RT160 1 2 0_0402_5%
0.60 0.68 6 TBT Alternate Modes not supported +VCC1V8A_TBTB_LDO
DisplayPort Alternate Modes - Source, C, D, and E @RT161 1 2 0_0402_5%
+TBTB_SENSE
pin configurations.
HV_GATE1_B
HV_GATE2_B
TI is 3x1uf +3.3V_VDD_PIC +3.3V_VDD_PIC_PDB
2.2U 16V K X5R 0402
2.2U 16V K X5R 0402
2.2U 16V K X5R 0402

TI VID supported
Accepts power role swaps but will not initiate. 1 1 1 +3.3V_ALW
Accepts data role swap to DFP and can initiate. 1
2
+5V_ALW_PDB
CT147
CT148
CT149
@ RT452 0_0402_5%
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles. 1 2
1U_0402_10V6K
1
2 2 2
CT150
@ RT453 0_0402_5% 2 1
C C
@ RT159 0_0402_5%
+3.3V_TBTB_FLASH
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
UT11
F1
VIN_3V3
VDDIO
LDO_1V8A
PP_CABLE
PP_5V0
PP_5V0
PP_5V0
PP_5V0
SENSEP
HV_GATE1
HV_GATE2
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
2
I2C_ADDR
D1
10K_0201_1% <23,25> TBT_I2C_SDA I2C_SDA1 +TBTB_Vbus_1
D2
+3.3V_TBTB_FLASH <23,25> TBT_I2C_SCL I2C_SCL1
RT172 C1
<23> TBTB_I2C_INT I2C_IRQ1_N TI has 1x1uf
1
PD2_GPIO8 +3.3V_ALW
@ RT162 2 1 3.3K_0402_5% UPD2_SMBUS_DAT_Q A5 +3.3V_PDB_VOUT +3.3V_TBTB_FLASH
1
@ RT163 2 1 3.3K_0402_5% UPD2_SMBUS_CLK_Q B5 I2C_SDA2 H11
1
1 10K_0402_5% UPD2_SMBINT#_R I2C_SCL2 VBUS
CT151
RT378 for TI strap pin @ RT164 2 B6 J10
1U_0603_25V6K
I2C_IRQ2_N VBUS
43K_0201_1% need double check J11
1U_0201_6.3V6M
10U_0402_6.3V6M
MUX2_FLIP_SEL_R VBUS 1 1
CT152
@ RT165 2 1 0_0402_5% B2 K11
2
EN_PD_HV_2_R GPIO0 VBUS
CT153
@ RT166 2 1 0_0402_5% C2
2
<57> EN_PD_HV_2 PD2_GPIO2 GPIO1

RT167 2 1 1M_0402_5% D10
@ RT168 2 1 0_0402_5% AC2_DISC#_R G11 GPIO2 2 2
<56,57> AC2_DISC# TBTB_HPD_R GPIO3
@ RT169 2 1 0_0402_5% C10
<23,36> TBTB_HPD OTG_ID2 GPIO4
@ RT170 2 1 0_0402_5% E10 H2
@ RT171 2 1 0_0402_5% PD2_GPIO6 G10 GPIO5 VOUT_3V3
@ RT340 2 1 0_0402_5% PD2_GPIO7 D7 GPIO6
PD2_GPIO8 H6 GPIO7
PD2_USB20_P GPIO8: USB_TYPEC_FAULT# GPIO8
0_0201_5% 2 1 @ RT405 G1
<10> USB20_P1 PD2_USB20_N TBTB_ROM_CLK_PD LDO_3V3
0_0201_5% 2 1 @ RT406 A3
<10> USB20_N1 TBTB_ROM_DI_PD SPI_CLK
B4
0_0201_5% 2 1 @ RT407 PD2_USB20_P 5/24 Change TBTB_ROM_DO_PD A4 SPI_MOSI
<23> TBTB_USB20_P PD2_USB20_N TBTB_ROM_CS#_PD SPI_MISO
0_0201_5% 2 1 @ RT408 B3 K6 TBTB_TOP_P <29>
<23> TBTB_USB20_N SPI_SS_N C_USB_TP L6
PD2_USB20_P C_USB_TN TBTB_TOP_N <29>
L5
PD2_USB20_N K5 USB_RP_P
UART_MISO_R USB_RP_N
<25> UART_MISO_R
@ RT178 2 1 0_0402_5% E2 K7 TBTB_BOT_P <29>
UART_MOSI_R F2 UART_TX C_USB_BP L7
<25> UART_MOSI_R UART_RX C_USB_BN TBTB_BOT_N <29>
@ RT180 2 1 0_0402_5% F4
2 1 UART_MOSI_R @ RT181 2 1 0_0402_5% G4 SWD_DATA TI has 2x220pf
SWD_CLK TBTB_CC1 <29>
@ 100K_0402_5% RT343 L9
2 1 UART_MISO_R C_CC1 L10
@ 1M_0402_5% RT344 C_CC2 WHEN CONNECT BUSPOWERZ TO GND,
820P_0402_50V7K
820P_0402_50V7K
TBTB_MRESET TBTB_CC2 <29>
B RT182 2 1 1M_0402_5% E11 CONNECT ALSO RPD_Gn to C_CCn 1 1 B
MRESET
CT154
CT155
K9 @ RT197 1 2 0_0402_5%
TBTB_LSTX @ RT183 1 2 0_0201_5% TBTB_LSTX_R L4 RPD_G1 K10 @ RT198 1 2 0_0402_5%
<23> TBTB_LSTX TBTB_LSRX @ RT184 1 2 0_0201_5% TBTB_LSRX_R K4 TBT_LSTX/R2P RPD_G2 +3.3V_TBTB_FLASH 2 2
<23> TBTB_LSRX TBT_LSRX/P2R
TBTB_LSTX @ RT185 1 2 0_0201_5% TBTB_DEBUG3 L3 E4 TBTB_DBG_CTL1 RT199 1 2 10K_0402_5%

TBTB_LSRX @ RT186 1 2 0_0201_5% TBTB_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTB_DBG_CTL2 RT200 1 2 10K_0402_5%
DIG_AUD_N/DEBUG4 DEBUG_CTL2
@ RT384 1 2 0_0402_5% UPD2_SMBUS_CLK_Q 1 2 TBTB_DEBUG1 L2

@ RT383 1 2 0_0402_5% UPD2_SMBUS_DAT_Q @ RT188 1 2 0_0402_5% TBTB_DEBUG2 K2 DEBUG1
@ RT189 0_0402_5% DEBUG2
K8 TBTB_SBU1_R @ RT201 1 2 0_0201_5%
TBTB_AUXP_C C_SBU1 TBTB_SBU1 <29>
CT156 1 2 0.1U_0201_10V6K J1
<23> TBTB_AUXP TBTB_AUXN_C AUX_P TBTB_SBU2_R
CT157 1 2 0.1U_0201_10V6K J2 L8 @ RT202 1 2 0_0402_5%
<23> TBTB_AUXN AUX_N C_SBU2 TBTB_SBU2 <29>
+3.3V_TBTB_FLASH
F10
BUSPOWER_N F11 TBTB_RESET_N_EC_R @ RT203 1 2 0_0402_5%
+3.3V_TBTB_FLASH RESET_N TBT_RESET_N_EC <23,25,36>
HRESET
2 1 TBTB_AUXN_C TBTB_ROSC G2
100K_0402_5% RT204 R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
15K_0402_1%
SS
2
2 1 TBTB_AUXP_C @
0_0201_5%
RT194
100K_0402_5% RT205 TPS65982DCZQZR_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT192
6/20 PN:SA0000AX700
2
1
+VCC1V8D_TBTB_LDO 1 2
100K_0402_5%
@ RT191 0_0201_5%
0_0402_5%
1
1
RT195
@ RT196
CT158
@ RT193
0.22U_0402_16V7K
0_0201_5% 2
2
2
A A
Need Link TPS65982D
[Type C]PD Controller TI-2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-F292P 1.0

5 4 3 2 1
5 4 3 2 1
For kirkwood
+5V_ALW
D D
UT7 +3.3V_VDD_PIC
DT1 +5V_PD_VDD
2 1 9
+5V_TBT_VBUS GND 1
DA2J10100L SOD323 8 OUT
DT2 IN 2
NC
1
2 1 7
@ NC 3
ADJ/NC 32.4K_0402_1%
0.1U_0201_10V6K
1U_0402_10V6K
2.2U_0402_10V6M
0.1U_0402_25V6K
DA2J10100L SOD323 1 1 6 1
NC
1
RT393 4 RT389 @
GND
CT88
CT89
CT91
CT92
100K_0402_5% 1 2 5
2
RT111 100K_0402_5% EN
2
2 2 AP7361C-FGE-7_U-DFN3030-8_3X3 2
2
1
1
CT90
1U_0402_6.3V6K RT390
2
10.2K_0402_1%
+TBTA_VBUS_1
place near UT7
2
UT8
1
VCC
1U_0603_25V6-K~D
DT3 1
1 2+5V_TBTA_VBUS_D3
VOUT
CT94
2
DA2J10100L SOD323 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
2
+TBTB_VBUS_1
UT12
1
VCC
1U_0603_25V6-K~D
DT38 1
1 2 +5V_TBTB_VBUS_D3
VOUT
CT167
2
DA2J10100L SOD323 GND
AP2204R-5.0TRG1_SOT89-3 2
B B
A A
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD [Type C]PD Power-2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
LA-F292P 1.0

5 4 3 2 1
5 4 3 2 1
For NON AR Config

Rear Side
D D
Check ,FROM PWR PAGE

+TBTA_VBUS +TBTA_VBUS
RF Request
JUSBC1 +TBTA_VBUS
A1 B12
GND GND +TBTA_VBUS
CT95 1 2 0.22U_0201_6.3V6K TBTA_TX1P_C A2 B11 TBTA_RX1P
<23> TBTA_TX1P SSTXP1 SSRXP1 TBTA_RX1P <23>
CT96 1 2 0.22U_0201_6.3V6K TBTA_TX1N_C A3 B10 TBTA_RX1N
<23> TBTA_TX1N SSTXN1 SSRXN1 TBTA_RX1N <23>
2 1 A4 B9 1 2
CT99 0.47U_0201_25V VBUS VBUS CT100 0.47U_0201_25V
2
TBTA_CC1 A5 B8 TBTA_SBU2
<25> TBTA_CC1 CC1 SUB2 TBTA_SBU2 <25>
ESD@ DT4
TBTA_TOP_P_R TBTA_BOT_N_R
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
@EMI@ RT120 1 2 0_0402_5% A6 B7 @EMI@ RT122 1 2 0_0402_5% AZ4024-02S_SOT23-3
<25> TBTA_TOP_P TBTA_TOP_N_R DP1 DN2 TBTA_BOT_P_R TBTA_BOT_N <25> 1 1
@EMI@ RT121 1 2 0_0402_5% A7 B6 @EMI@ RT123 1 2 0_0402_5%
C <25> TBTA_TOP_N DN1 DP2 TBTA_BOT_P <25> C
Bottom
TBTA_SBU1 A8 B5 TBTA_CC2
<25> TBTA_SBU1 SUB1 CC2 TBTA_CC2 <25> 2 2
TOP
2 1 A9 B4 1 2
0.47U_0201_25V CT101 VBUS VBUS CT102 0.47U_0201_25V
1
TBTA_RX2N A10 B3 TBTA_TX2N_C 0.22U_0201_6.3V6K 2 1 CT98
<23> TBTA_RX2N TBTA_RX2P A11 SSRXN2 SSTXN2 B2 TBTA_TX2P_C TBTA_TX2N <23>
0.22U_0201_6.3V6K 2 1 CT97
<23> TBTA_RX2P SSRXP2 SSTXP2 TBTA_TX2P <23>
A12 B1
GND GND
1 4
GND GND
2 3
5 GND GND 6
GND GND
JAE_DX07SD24JJ2R1300~D
CONN@
20160628
ESD@ DT5 ESD@ DT13

TBTA_TX1P_C 1 2 TBTA_RX1P 1 2
AZ5B75-01B.R7G CSP0603P2Y AZ5B75-01B.R7G CSP0603P2Y
B ESD@ DT6 ESD@ DT14 B
TBTA_TX1N_C 1 2 TBTA_RX1N 1 2
ESD@ DT9 ESD@ DT17

TBTA_RX2N 1 2 TBTA_TX2P_C 1 2
ESD@ DT10 ESD@ DT18

TBTA_RX2P 1 2 TBTA_TX2N_C 1 2
DT41 ESD@ DT42 ESD@

TBTA_SBU1 1 1 TBTA_SBU1 TBTA_SBU2 TBTA_SBU2
10 9 1 1 10 9
TBTA_TOP_N_R 2 2 9 8
TBTA_TOP_N_R TBTA_BOT_N_R 2 9 8
TBTA_BOT_N_R
2
TBTA_TOP_P_R 4 4 7 7
TBTA_TOP_P_R TBTA_BOT_P_R 4 7 7
TBTA_BOT_P_R
4
TBTA_CC1 5 5 6 6
TBTA_CC1 TBTA_CC2 5 5 6 6
TBTA_CC2
3 3 3 3
8 8
A A
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
PROPRIETARY NOTE: Compal Electronics, Inc.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C
1.0
5 4 3 2 1
5 4 3 2 1
For kirkwood
For NON AR Config
Front Side
D D
Check ,FROM PWR PAGE

+TBTB_VBUS +TBTB_VBUS
JUSBC2
A1 B12
GND GND
CT159 1 2 0.22U_0201_6.3V6K TBTB_TX1P_C A2 B11 TBTB_RX1P
<23> TBTB_TX1P TBTB_TX1N_C SSTXP1 SSRXP1 TBTB_RX1N TBTB_RX1P <23>
CT160 1 2 0.22U_0201_6.3V6K A3 B10 RF Request
<23> TBTB_TX1N SSTXN1 SSRXN1 TBTB_RX1N <23> +TBTB_VBUS
2 1 A4 B9 1 2
0.47U_0201_25V CT163 VBUS VBUS CT164 0.47U_0201_25V +TBTB_VBUS
TBTB_CC1 A5 B8 TBTB_SBU2
<26> TBTB_CC1 CC1 SUB2 TBTB_SBU2 <26>
@EMI@ RT214 1 2 0_0402_5% TBTB_TOP_P_R A6 B7 TBTB_BOT_N_R @EMI@ RT216 1 2 0_0402_5%
<26> TBTB_TOP_P @EMI@ RT215 1 TBTB_TOP_N_R DP1 DN2 TBTB_BOT_P_R @EMI@ RT217 1
TBTB_BOT_N <26>
<26> TBTB_TOP_N 2 0_0402_5% A7 B6 2 0_0402_5% TBTB_BOT_P <26>
C DN1 DP2 C
Bottom
2
TBTB_SBU1 A8 B5 TBTB_CC2
<26> TBTB_SBU1 SUB1 CC2 TBTB_CC2 <26>
ESD@ DT21
TOP
12P_0402_50V8J
RF@ CT191
82P_0402_50V8J
RF@ CT192
2 1 A9 B4 1
2 1 1 AZ4024-02S_SOT23-3
0.47U_0201_25V CT165 VBUS VBUS CT166 0.47U_0201_25V
TBTB_RX2N A10 B3 TBTB_TX2N_C 0.22U_0201_6.3V6K 2 1 CT162
<23> TBTB_RX2N TBTB_RX2P A11 SSRXN2 SSTXN2 B2 TBTB_TX2P_C 0.22U_0201_6.3V6K 2 1 TBTB_TX2N <23>
CT161
<23> TBTB_RX2P SSRXP2 SSTXP2 TBTB_TX2P <23> 2 2
A12 B1
GND GND
1
1 4
GND GND
2 3
5 GND GND 6
GND GND
CONN@
20160628
ESD@ DT22 ESD@ DT30

TBTB_TX1P_C 1 2 TBTB_RX1P 1 2
ESD@ DT23 ESD@ DT31
B
TBTB_TX1N_C 1 2 TBTB_RX1N 1 2 B
ESD@ DT26 ESD@ DT34

TBTB_RX2N 1 2 TBTB_TX2P_C 1 2
ESD@ DT27 ESD@ DT35

TBTB_RX2P 1 2 TBTB_TX2N_C 1 2
DT43 ESD@ DT44 ESD@

TBTB_SBU1 1 1 TBTB_SBU1 TBTB_SBU2 TBTB_SBU2
10 9 1 1 10 9
TBTB_TOP_N_R 2 2 9 8 TBTB_TOP_N_R TBTB_BOT_N_R 2 9 8 TBTB_BOT_N_R
2
TBTB_TOP_P_R 4 4 7 7
TBTB_TOP_P_R TBTB_BOT_P_R 4 7 7
TBTB_BOT_P_R
4
TBTB_CC1 5 5 6 6
TBTB_CC1 TBTB_CC2 5 5 6 6
TBTB_CC2
3 3 3 3
8 8
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
A A
PROPRIETARY NOTE: Compal Electronics, Inc.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C-2
1.0
5 4 3 2 1
5 4 3 2 1
LINK 50398-04041-001 DONE

JEDP1
1
20160308 +3.3V_TSP
For Kirkwood
1 2
2 3 DMIC0 <35>
3 4
4 DMIC_CLK0 <35>
5
5 +3.3V_RUN TS_I2C_SDA
6 1 2
6 USB20_N5_R +3.3V_CAM
100P_0201_50V8J
RF@
100P_0201_50V8J
RF@
7 RV98 2.2K_0402_5%
7 8 USB20_P5_R TS_I2C_SCL 1 2
8
1
9 RV99 2.2K_0402_5%
9 10 CAM_MIC_CBL_DET# <12> TS_INT# 1 2
10 Pin15: LOOP_BACK
CA5
CA6
11 JTS1 RV311 100K_0402_5%
2
11 12 1
12 +BL_PWR_SRC 1 +3.3V_TSP
13 2
13 14 2 3 PCH_PLTRST#_AND <11,23,33,38,39>
14 3 TOUCH_SCREEN_PD# <12>
15 4
D
15 16 EMI@ LV1 1 2 BIA_PWM 4 5 TS_I2C_SDA TOUCH_PANEL_PD#: D
16 DISP_ON 5 TS_I2C_SCL TS_I2C_SDA <9> EXC24CQ900U_4P
17 BLM15BB221SN1D_2P EMI Request 6 Close lid >> TP_EN = 0 >> Disable touch events
17 18 6 7 TS_I2C_SCL <9> Open lid >> TP_EN = 1 >> Enable touch events 4 3
18 7 TS_INT# <6> USB20_N8_R USB20_N8 <10>
19 8
19 20 8 9 USB20_P8_R
20 21 9 10 TOUCH_SCREEN_DET# 1 2
21 EDP_HPD <6> +LCDVDD 10 TOUCH_SCREEN_DET# <12> USB20_P8 <10>
22
22 23 LV27 EMI@
23
1
EDP_HPD
10K_0402_5%
PESD5V0U2BT_SOT23-3
@ESD@ DV4
24 1 2 KKW
24 LCD_TST <36>
3
25 @ RV7 100K_0402_5%
25
RV305
26 +LCDVDD
26 27 Reserve for EA
27 28 PANEL_SIZE_DET <12> 11
2
28 29 EDP_AUXN_C CV1 2 1 0.1U_0402_25V6 GND 12
29 30 EDP_AUXP_C CV2 2 1 EDP_AUXN <6> GND
0.1U_0402_25V6
EDP_AUXP <6>
1
30 31 EDP_TXP0_C CV3 2 1 0.1U_0402_25V6
31 EDP_TXN0_C CV4 EDP_TXP0 <6> ACES_50208-01001-P03
32 2 1 0.1U_0402_25V6
32 33 EDP_TXP1_C CV5 2 1 EDP_TXN0 <6> CONN@
0.1U_0402_25V6
33 34 EDP_TXN1_C CV6 2 1 EDP_TXP1 <6>
0.1U_0402_25V6
34 35 EDP_TXP2_C CV7 2 1 0.1U_0402_25V6
EDP_TXN1 <6> LINK ACES_50208-01201-P01 Done
35 EDP_TXN2_C CV8 EDP_TXP2 <6> TS_I2C_SDA
41
42 G1 36
36
37 EDP_TXP3_C CV9
2
2
1
1
0.1U_0402_25V6
EDP_TXN2 <6> SP01001UP00 20160711 ESD depop locat i on 1 2
0.1U_0402_25V6 RF@CV54 33P_0402_50V8J
43 G2 37 38 EDP_TXN3_C CV10 2 1 EDP_TXP3 <6> TS_I2C_SCL 1 2
0.1U_0402_25V6
G3 38 EDP_TXN3 <6>
44 39 RF@CV55 33P_0402_50V8J
45 G4 39 40
G5 40 LCD_CBL_DET# <9>
RF Request
ACES_50398-04041-001
CONN@
RF Request
+3.3V_TSP
+BL_PWR_SRC +LCDVDD +3.3V_CAM +3.3V_TSP +3.3V_RUN
+3.3V_RUN
0.1U_0603_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10K_0402_5%
1 1 1 1 @
1
2
@
@ @ @ @
RV8
CV11
CV12
CZ1
CZ2
CA7
JIR1
2
2 2 2 2 +PWR_SRC
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
1 1 1
C 1 IR_CAM_DET# <12> C
2
1
2 3 TOUCH_SCREEN_DET#
3
100P_0402_50V8J
RF@ CZ3
4 1
2 2 4 5
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
5 6
6 +PWR_SRC
7
GND 8 2
DV1 DV2 GND
ACES_50208-0060N-P01
3 EDP_BIA_PWM 3
EDP_BIA_PWM <6> PANEL_BKLEN <6> CONN@
BIA_PWM DISP_ON
RF Request
1 1
2 BIA_PWM_EC 2 Link ACES_50208-0060N-P01 done
BIA_PWM_EC <36> PANEL_BKEN_EC <36>
20160315
1
4.7K_0402_5%
4.7K_0402_5%
1
BAT54CW SOT323 BAT54CW SOT323

RV1
RV2
2
+3.3V_RUN +3.3V_RUN
For Touchscreen
2
CHECK Power Rail
+3.3V_TSP
100K_0402_5%
1
RV326
1 2
RF Request UZ41 @ RZ516 0_0402_5%
2
1 7 +3.3V_TSP_UZ41
+LCDVDD +3.3V_CAM +BL_PWR_SRC 2 VIN VOUT 8 1 2
VIN VOUT CZ305 0.1U_0201_10V6K
1 2 TS_EN 3 6 1 2
<9> PCH_3.3V_TS_EN ON CT
@ RV306 0_0402_5% CZ306 470P_0402_50V7K
1 2 4
<36> 3.3V_TS_EN @ RV323
+5V_ALW VBIAS
0_0402_5% 5
GND 9
GND
12P_0402_50V8J
RF@ CV20
82P_0402_50V8J
RF@ CV21
12P_0402_50V8J
RF@ CV22
82P_0402_50V8J
RF@ CV23
12P_0402_50V8J
RF@ CV24
82P_0402_50V8J
RF@ CV25
1 1 1 1 1 1
B B
AOZ1336_DFN8_2X2
2 2 2 2 2 2
LCDVDD POWER +LCDVDD +EDP_VDD
WebCAM Backlight POWER +BL_PWR_SRC

+3.3V_ALW
@
CV16 PJP12 UV24
2 1 1 2 1
+PWR_SRC QV1 VOUT 5
10U_0603_10V6M VIN
+3.3V_CAM +3.3V_RUN 6 PAD-OPEN1x1m 2
D
GND
0.01UF_0402_25V7K
4 5 4
S
EN
@
QZ1 2
CV17
LP2301ALT1G_SOT23-3 1 3
1000P_0402_50V7K
/OC
0.1U_0603_50V7K
G
270K_0402_5%
2
1 3 AO6405_TSOP6 G524B1T11U_SOT23-5
D
CV13
2
2
DV3
RV4
CV15
2
G
2
<36> LCD_VCC_TEST_EN EN_LCDPWR

1 2 1
<11> 3.3V_CAM_EN#
1
@ RZ380 0_0402_5%
0.1U_0402_25V6K
3
<6> ENVDD_PCH
1
2
BL_PWR_SRC_ON
100K_0402_5%
@
CZ200
RV3
QV2 BAT54CW SOT323
2
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
1
A A
1 2 1 3
D
S
CV14
RV5 47K_0402_5%
EXC24CQ900U_4P
4 3 USB20_P5_R 2
G
<10> USB20_P5
2
1 2 USB20_N5_R
<10> USB20_N5 <36> EN_INVPWR
LZ1 EMI@ DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP CONN & Touch screen
1.0
5 4 3 2 1
A B C D E
RF Request
+3.3V_MMI_IN For USB Interface
12P_0402_50V8J
@RF@ CR25
82P_0402_50V8J
@RF@ CR26
1 1
2 2
1 1
+3.3V_MMI_IN
close to UR1.8 close to UR1.27 close to UR1.11
+3.3V_MMI_IN
4.7U_0603_6.3V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
0.1U_0201_10V6K
10U_0402_6.3V6M
0.1U_0201_10V6K
+3.3V_RUN +3.3V_MMI_IN UR1
PJP14
1 1 1 1 11
1
1
3V3_IN
CR29
CR1
CR3
1 2 12
CR2
CR4
CR30
SD_3V3 +3.3V_RUN_CARD
27
D3V3 13 +1.8V_RUN_CARD
2
2
2 2 2 2 PAD-OPEN1x2m 8 SD40_VDD2
A3V3 14 +SDREG2 1 2
6 SDREG CR15 1U_0402_6.3V6K
+1.2V_LDO +SD40_AV12 AV12
24
VDD_LANE 30 SDWP SD/MMCCLK_R
+DV_12S SD_WP
@EMI@ CR21
21 31 SD/MMCCD#
DV12S SD_CD#
5P_0402_50V8C
+1.2V_LDO 1 2 USB20_P6_R 9
<10> USB20_P6
1
@ RR20 1 2 0_0402_5% USB20_N6_R 10 DP 17 SD/MMCCLK @EMI@RR5 1 2 0_0402_5% SD/MMCCLK_R
<10> USB20_N6
close to UR1.6 close to UR1.24 close to UR1.21 @ RR21 0_0402_5% DM SD_CLK 18 SD/MMCCMD @ RR6 1 2 0_0402_5% SD/MMCCMD_R
CR31 1 2 0.1U_0402_25V6 USB3_PTX_C_DRX_P4 2 SD_CMD
close to UR1.17
2
<10> USB3_PTX_DRX_P4 USB3_PTX_C_DRX_N4 SS_RX+
Swap TX/RX (Based on Vendor Review) CR32 1 2 0.1U_0402_25V6 3
+SD40_AV12 +DV_12S 20160323 <10> USB3_PTX_DRX_N4 SS_RX-
CR13 1 2 0.1U_0402_25V6 USB3_PRX_C_DTX_P4 4 19 SD/MMCDAT3 @ RR7 1 2 0_0402_5% SD/MMCDAT3_R
<10> USB3_PRX_DTX_P4 CR14 1 2 0.1U_0402_25V6 USB3_PRX_C_DTX_N4 5 SS_TX+ SD_D3 20 SD/MMCDAT2 @ RR8 1 2 0_0402_5% SD/MMCDAT2_R
<10> USB3_PRX_DTX_N4 SS_TX- SD_D2 SD/MMCDAT1/RCLK-_R EMI depop locat i on
4.7U_0603_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
0.1U_0201_10V6K
15 SD/MMCDAT1/RCLK- @ RR9 1 2 0_0402_5%
29 SD_D1 16 SD/MMCDAT0/RCLK+ @ RR10 1 2 0_0402_5% SD/MMCDAT0/RCLK+_R
1 1
1
XTLI SD_D0
CR5
CR9 28
CR6
CR10
XTLO
CR8
1 2 SD_GPIO0 32 22 SD_UHS2_D1P
+3.3V_MMI_IN
2
2 2 2 GPIO0 SD40_D1+ SD_UHS2_D1N 2

RR3 10K_0402_5% 23
1 2 SD_GPIO1 1 SD40_D1- 26 SD_UHS2_D0P
RR22 10K_0402_5% GPIO1 SD40_D0+ 25 SD_UHS2_D0N
1 2 +RREF 7 SD40_D0-
RR4 6.2K_0402_1% RREF 33
EPAD
RTS5330-GR_QFN32_4X4
20160304 CIS Link
3 3
QR1
L2N7002WT1G_SC-70-3
HOST_SD_W P# SDW P_Q SDW P STATUS
SDWP 1 3 JSD1
S
4
+3.3V_RUN_CARD VDD1
High High Write Protect(SD LOCK) +1.8V_RUN_CARD 15
SD/MMCCMD_R 3 VDD2
G
2
High SD/MMCCLK_R 5 CMD
Low Low Write Enable CLK
<12> HOST_SD_WP#
SD/MMCCD# 9
16 CD
High High Write Protect(SD& FW LOCK) SWIO
Low SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
Low High Write Protect(FW LOCK) SD/MMCDAT2_R 1 DAT0/RCLK-
+3.3V_RUN_CARD +1.8V_RUN_CARD SD/MMCDAT3_R 2 DAT2
CD/DAT3
SD_UHS2_D0P 18
SD_UHS2_D0N 19 D0+
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
SD_UHS2_D1P 22 D0-
2 2
2
SD_UHS2_D1N 21 D1+
CR17
CR19
CR20
D1-
CR18
10
1
1 1 6 GND1 11
17 VSS1 GND2 12
20 VSS2 GND3 13
23 VSS3 GND4 14
VSS4 GND5
T-SOL_158-1240902600
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14 CONN@
LINK T-SOL_158-1240902600 DONE

4
20160329 4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader RTS5330
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
A B C D E
5 4 3 2 1
Only for Kirkwood
PCIE/USB MUX
D
NEED LINK TI HD3SS3212 as main D
+3.3V_WWAN
.1U_0402_16V7K
.1U_0402_16V7K
1 1
CZ154
CZ155
2 2
UZ29
1
USB3_PRX_DTX_P2 19 NC 6
<10> USB3_PRX_DTX_P2 USB3_PRX_DTX_N2 18 B0p VCC 10
<10> USB3_PRX_DTX_N2 2 0.1U_0402_10V7K USB3_PTX_C_DRX_P2 B0n NC
CZ150 1 17
<10> USB3_PTX_DRX_P2 B1p
CZ151 1 2 0.1U_0402_10V7K USB3_PTX_C_DRX_N2 16 3 PCIE_PRX_SW_DTX_P7
<10> USB3_PTX_DRX_N2 B1n A0p PCIE_PRX_SW_DTX_N7 PCIE_PRX_SW_DTX_P7 <33>
4
PCIE_PRX_DTX_P7 A0n PCIE_PTX_SW_DRX_P7 PCIE_PRX_SW_DTX_N7 <33>
15 7
<10> PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 14 C0p A1p 8 PCIE_PTX_SW_DRX_N7 PCIE_PTX_SW_DRX_P7 <33>
<10> PCIE_PRX_DTX_N7 CZ152 1 2 0.22U_0402_10V6K PCIE_PTX_C_SW_DRX_P7 13 C0n A1n PCIE_PTX_SW_DRX_N7 <33>
<10> PCIE_PTX_DRX_P7 C1p
CZ153 1 2 0.22U_0402_10V6K PCIE_PTX_C_SW_DRX_N7 12
<10> PCIE_PTX_DRX_N7 C1n 5
NGFF_CONFIG_1 9 GND 11
<33,36> NGFF_CONFIG_1 SEL GND 20
2 GND 21
OEn PGND
C C
Function SEL PD HD3SS3212RKSR_VQFN20_2P5X4P5
B to A L L
C to A H L
All ports Hi-Z,
IC power down X H
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type M3042_PCIE#_SATA
0 GND GND GND GND SSD-SATA HIGH
1 GND HIGH GND GND SSD-PCIE(2 lane) LOW
8 HIGH GND GND GND WWAN LOW
14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) LOW
15 HIGH HIGH HIGH HIGH NA LOW

B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB/PCIE MUX
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
LA-F292P 1.0

5 4 3 2 1
5 4 3 2 1
8
0
1
4
8
-
3
2
2
1
&
8
0
1
4
8
-
4
2
2
1
F
o
o
t
p
r
i
n
t
t
h
e
s
a
m
e
+3.3V_WWAN
NGFF slot A Key A Only for Kirkwood
NGFF slot B Key B +3.3V_WLAN
CONN@
JNGFF1
2 1 WWAN_PWR_EN 1 2
RZ43 47K_0402_5% USB20_P7_L 3 1 2 4
USB20_N7_L 5 3 4
100P_0402_50V8J
CONN@ +3.3V_WWAN 6
JNGFF2 7 5 6
RF@ CZ198
1 2 7
<36> NGFF_CONFIG_3
1
3 1 2 4
5 3 4 6 WWAN_PWR_EN
USB20_P4_L 7 5 6 8 WWAN_RADIO_DIS#_R 16
2
USB20_N4_L 9 7 8 10 SLOT2_SATA_LED# 1 2 17 16 18
SATALED# <10,39,43>
11 9 10 @ RN101 0_0402_5% 19 17 18 20
11 21 19 20 22
23 21 22 24
D 25 23 24 26 D
20 27 25 26 28
21 20 22 29 27 28 30
<36> NGFF_CONFIG_0 21 22 29 30
23 24 31 32
<36> WWAN_WAKE# P_SENSOR_ACK#_R 23 24 HW_GPS_DISABLE#_R 31 32
2 1 25 26 33 34
@RF@ RZ326 0_0402_5% 27 25 26 28
CZ304 CZ12 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P5 35 33 34 36
PCIE_PRX_L_DTX_N7 29 27 28 30 UIM_RESET close <10> PCIE_PTX_DRX_P5
CZ13 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N5 37 35 36 38
PCIE_PRX_L_DTX_P7 29 30 UIM_CLK <10> PCIE_PTX_DRX_N5 37 38 PCH_CL_RST1# <8>
31 32 RF@ CZ304 1 JNGFF2
2 68P_0402_50V8J 39 40
PCH_CL_DATA1 <8>
33 31 32 34 UIM_DATA 41 39 40 42
support PCIE & SATA PCIE_PTX_L_DRX_N7 35 33 34 36
+SIM_PWR
WLAN <10> PCIE_PRX_DTX_P5 43 41 42 44 WLAN_COEX3 PCH_CL_CLK1 <8>
PCIE_PTX_L_DRX_P7 37 35 36 38 <10> PCIE_PRX_DTX_N5 45 43 44 46 WLAN_COEX2
37 38 ISH_I2C2_SCL_R M3042_DEVSLP <10> 45 46 WLAN_COEX1
Double check P/N PIN for SATA/PCIE 39 40 2 1 47 48
39 40 ISH_I2C2_SDA_R ISH_I2C2_SCL <9> <11> CLK_PCIE_P1 47 48 WIGIG_32KHZ
41 42 @ RZ76 2 1 0_0402_5% 49 50 2 1
<10> PCIE_PRX_DTX_P8 41 42 ISH_I2C2_SDA <9> <11> CLK_PCIE_N1 49 50 PCH_PLTRST#_AND SUSCLK <11,39>
43 44 @ RZ77 0_0402_5% 51 52 @ RZ56 0_0402_5%
<10> PCIE_PRX_DTX_N8 43 44 51 52 BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,23,30,38,39>
45 46 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9 53 54
45 46 <11> CLKREQ_PCIE#1 53 54
CZ10 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N8 47 48 PCIE_WAKE# 55 56 WLAN_WIGIG60GHZ_DIS#_R
<10> PCIE_PTX_DRX_N8 <23,37,39> PCIE_WAKE#
CZ11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P8 49 47 48 50 PCH_PLTRST#_AND 57 55 56 58 ISH_UART0_RXD_R 2 1
<10> PCIE_PTX_DRX_P8 49 50 57 58 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <9>
51 52 59 60 1 0_0402_5%
51 52 PCIE_WAKE# CLKREQ_PCIE#0 <11> 59 60 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <9>
53 54 61 62 1 0_0402_5%
<11> CLK_PCIE_N0 53 54 61 62 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <9>
55 56 63 64 1 0_0402_5%
<11> CLK_PCIE_P0 55 56 63 64 PCH_PLTRST#_AND @ RZ81 ISH_UART0_RTS# <9>
57 58 @ RZ132 2 1 0_0402_5% 65 66 0_0402_5%
HOST_DEBUG_TX WLAN_COEX3
2 1 WWAN_ANTCTL0 59 57 58 60 WWAN_COEX3 @RF@ RZ128 1 2 0_0201_5% <36,37> 67 65 66 68
<34> WWAN_ANTCTL0_R @RF@ RZ327 2 10_0402_5% WWAN_ANTCTL1 61 59 60 62 WWAN_COEX2 @RF@ RZ129 1 2 0_0201_5% WLAN_COEX2 WIGI 69 67 68 70 PCIE_WAKE#
<34> WWAN_ANTCTL1_R @RF@ RZ328 2 10_0402_5% WWAN_ANTCTL2 63 61 62 64 WWAN_COEX1 @RF@ RZ130 1 2 0_0201_5% WLAN_COEX1 71 69 70 72
<34> WWAN_ANTCTL2_R @RF@ RZ329 2 10_0402_5% WWAN_ANTCTL3 65 63 64 66 SIM_DET 73 71 72 74
<34> WWAN_ANTCTL3_R @RF@ RZ330 0_0402_5% PAD~D @ T225 67 65 66 68 75 73 74 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9
69 67 68 70 75
<32,36> NGFF_CONFIG_1 69 70
71 72
73 71 72 74 77 76
73 74 GND GND
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
75
@RF@ CZ303
@RF@ CZ302
@RF@ CZ301
@RF@ CZ300
<36> NGFF_CONFIG_2 75
1
77 76 LOTES_APCI0241-P001A
GND GND
L
I
N
K
O
K
2
LOTES_APCI0242-P001A
L
I
N
K
O
K
+3.3V_WLAN
C C
RF Request
+3.3V_WWAN
+3.3V_WWAN
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
1 1 1
1
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
33P_0402_50V8J
47P_0402_50V8J
100P_0402_50V8J
2200P_0402_50V7K
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
RF@
WWAN_RADIO_DIS#_R
22U_0603_6.3V6M
RF@ CZ24
100U_B2_6.3VM_R35M
RF@CZ26
1 1 2
RF@ CZ25
<36> WWAN_RADIO_DIS#
2
1
2 2 2
1
1
CZ17
CZ18
CZ19
CZ20
CZ21
+ DZ5
WLAN_WIGIG60GHZ_DIS#_R
CZ23
RB751S-40 SOD-523 1 2
<36> WLAN_WIGIG60GHZ_DIS#
2
2 DZ1
RB751S-40 SOD-523
1 2 HW_GPS_DISABLE#_R
<36> GPS_DISABLE#
Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
DZ6
RB751S-40 SOD-523
1 2 1 2 BT_RADIO_DIS#_R
<36> BT_RADIO_DIS# RF Request
@RF@ RI27 0_0402_5% +1.8V_RUN
HCM1012GH900BP_4P DZ2 +3.3V_WLAN
1
+1.8V_RUN RB751S-40 SOD-523
1 2 PCIE_PRX_L_DTX_N7 RZ344
<32> PCIE_PRX_SW_DTX_N7 10K_0201_1%
2
PCIE_PRX_L_DTX_P7
15P_0402_50V8J
2.2P_0402_50V8C
12P_0402_50V8J
15P_0402_50V8J
4 3 RF Request
2
<32> PCIE_PRX_SW_DTX_P7
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
RF@ LI16 1 3 P_SENSOR_ACK#_R 1 2
<36> SAR_DPR#
1
1 2 @RF@ RI49 0_0402_5%
S
@RF@ RI28 0_0402_5%
1 2 Q1 L2N7002WT1G_SC-70-3
2
@RF@ RI29 0_0402_5%
HCM1012GH900BP_4P
1 2 PCIE_PTX_L_DRX_N7
<32> PCIE_PTX_SW_DRX_N7
LI9 RF@
1 2 USB20_N7_L
B <10> USB20_N7 B
4 3 PCIE_PTX_L_DRX_P7
<32> PCIE_PTX_SW_DRX_P7
RF@ LI17 4 3 USB20_P7_L
<10> USB20_P7
1 2 RF Request
@RF@ RI30 0_0402_5% EXC24CQ900U_4P
1 2
SIM Card Push-Push @RF@ RI47 0_0402_5%
+SIM_PWR
@RF@ RI50
1 2
0_0402_5%
Power Rating TBD
JSIM1
4.7U_0402_6.3V6M
1 5 Primary Power Aux Power

UIM_RESET 2 VCC GND 6 PWR Voltage
1
UIM_CLK 3 RST VPP 7 UIM_DATA LI8 RF@

CLK I/O USB20_P4_L Rail Tolerance
CZ37
4 8 1 2 Peak Normal Normal

NC NC <10> USB20_P4
2
9
DLSW 10 SIM_DET 4 3 USB20_N4_L
DTSW <10> USB20_N4 +3.3V
11 14 EXC24CQ900U_4P
12 GND GND 15
13 GND GND 16
GND GND 17
GND 1 2
JAE_SF51S006V4B @RF@ RI48 0_0402_5%
CONN@
JAE_SF51S006V4DR1000Q LINK DONE

20160321 (Temp symbol is correct, SP number is wrong on DTSW)
+SIM_PWR
UIM_CLK
@RF@ RZ335
1
15K_0402_5%
47P_0402_50V8J
A A
@RF@ CZ38
1
+SIM_PWR
UIM_DATA UIM_RESET
2
33P_0402_50V8J
33P_0402_50V8J
@RF@ RZ334
1
51_0402_5%
RF@CZ39
RF@CZ40
0.1U_0402_25V6
RF@ CZ41
1 1 1
2 2 2 Compal Electronics, Inc.
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
RF Request PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F292P
5 4 3 2 1
5 4 3 2 1
D D
Only for Kirkwood
+3.3V_WWAN_MAIN
Annt. Control
0.1U_0201_10V6K
1
CZ186
JTUN1 2
@RF@ RZ331 2 1 0_0402_5% +3.3V_WWAN_MAIN 1
+3.3V_WWAN +3.3V_WWAN_AUX 1
@RF@ RZ332 2 1 0_0402_5% 2
+3.3V_WWAN WWAN_ANTCTL0_R 2
3
<33> WWAN_ANTCTL0_R WWAN_ANTCTL1_R 3
4
5
6
<33> WWAN_ANTCTL3_R 6
7
8 7
C 8 C
9
10 GND +3.3V_WWAN_AUX
GND
ACES_50208-00801-003
0.1U_0201_10V6K
CONN@
Link ACES_50208-00801-003 done

1
20160315
CZ187
RF@CZ180 68P_0402_50V8J
+3.3V_WWAN_MAIN 1 2
RF@CZ181 68P_0402_50V8J 2
+3.3V_WWAN_AUX 1 2
RF@CZ182 68P_0402_50V8J
WWAN_ANTCTL0_R 1 2
RF@CZ183 68P_0402_50V8J
WWAN_ANTCTL1_R 1 2
RF@CZ184 68P_0402_50V8J
WWAN_ANTCTL2_R 1 2
RF@CZ185 68P_0402_50V8J
WWAN_ANTCTL3_R 1 2
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT RF Tunable Conn
1.0
5 4 3 2 1
2 1
+3.3V_RUN_AUDIO
SPKR_R
+3.3V_RUN_AUDIO_DVDD
100P_0402_50V8J
2 1
10K_0402_5%
LA14 BLM15PX600SN1D_2P
1
BEEP_R
@ CA72
@ RA51
+1.8V_RUN +3.3V_RUN_AUDIO_IO
0.1U_0201_10V6K
10U_0603_10V6M
100P_0402_50V8J
2 1
@ RA3 1
10K_0402_5%
2 0_0603_5% 1 LA12 BLM15PX600SN1D_2P
2
1
1
+1.8V_RUN_AUDIO
CA10
CA61
0.1U_0201_10V6K
10U_0603_10V6M
@ CA62
@ RA45
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) place close to pin16
1
Internal Speakers Header
2
1
10U_0603_10V6M
0.1U_0201_10V6K
CA55
CA56
2
2
2
1
CA58
CA57
40 mils trace keep 20 mil spacing need link SM01000NS00
2
JSPK1 2
INT_SPK_L+ EMI@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L+ 1 7
Realtek suggest rated current : 2A
2
INT_SPK_L- EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2 1 G1 2
INT_SPK_R+ INT_SPKR_R+ 2 Change Footprint to TAI-T_HCB2012KF-121T50_2P
EMI@ LA8 1 2 BLM15PX330SN1D_2P 3
INT_SPK_R- EMI@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 4 3
SPK_DET# 5 4 +5V_RUN_AUDIO +5V_RUN_AUDIO
<12> SPK_DET# 5 LA13
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
6 8 LA5 place close to pin41 place close to pin46
3
6 G2 +VDDA_AVDD1 +5V_RUN_PVDD_L
@ESD@ DA6
@ESD@ DA7
2 1 place close to pin40 1 2
ACES_50278-00601-001 BLM15PX600SN1D_2P HCB2012VF-601T20_2P
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
CONN@ 1 1 1 1 1 1
EMI@
EMI@
EMI@
EMI@
CA45
CA47
CA60
1
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
CA8
CA46
CA48
CA59
@ RA54 1 2 0_0402_5% 600 Ohm/2A RF Request
Change to 6pin to support 2 SPK vendor +5V_ALW
1
CA9
2 2 2 2 2 2
Link ACES_50278-00601-001 DONE @ RA55 1 2 0_0402_5%
+RTC_CELL
+5V_RUN_AUDIO
2
2
CA22
CA23
CA19
CA24
20160325
2
1
UA1
40
16
21
12
41
46
47
4
+3.3V_RUN
AVDD1
AVDD2
DVDD-IO
PVDD1
PVDD2
5VSTB/AUX MODE
CPVDD
DVDD
2 1
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
CA73 330P_0402_50V8J 1 1
1
Close to UA1 AUD_HP_OUT_R HP_OUT_R
2 1 25
RA58 16.2_0402_1% RA8 HP-OUT-R 36
10K_0402_5% AUD_HP_OUT_L 2 1 HP_OUT_L 26 LINE2-L 2 2
16.2_0402_1% RA7 HP-OUT-L 35
2
SPK_DET# 19 LINE2-R
B 2 1 HP-OUT2-L 34 LINE1_L 1 2 HP_OUT_L B
CA74 330P_0402_50V8J 20 LINE1-L CA43 10U_0603_10V6M AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
HP-OUT2-R 33 LINE1_R 1 2 HP_OUT_R
LINE1-R CA44 10U_0603_10V6M
Close to UA1 pin6 32 AUD_PC_BEEP 2 1 SPKR_R 1 2
PCBEEP BEEP_R SPKR <12>
15 CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
HDA_BIT_CLK_R DMIC_CLK0 LINE1-VREFO-R-E/MONO BEEP <36>
30 SLEEVE CA28 0.1U_0402_25V6 RA13 1K_0402_5%
SLEEVE
@EMI@ RA17
@EMI@ CA54
14
LINE1-VREFO-L-E
10P_0402_50V8J
29 RING2 SLEEVE/RING2 please keep 40 mils trace width

1
RING2
33_0402_5%
27 +MIC2-VREFO-L 2 1 RING2 RF Request

HDA_BIT_CLK_R 8 MIC2-VREFO-L RA5 2.2K_0402_5%
2
<12> HDA_BIT_CLK_R BCLK +1.8V_RUN_AUDIO +1.8V_RUN

28 +MIC2-VREFO-R 2 1 SLEEVE
9 MIC2-VREFO-R RA6 2.2K_0402_5%
<12> HDA_SYNC_R
2
SYNC
HDA_SDIN0_R
10P_0402_50V8J
@EMI@ CA33
1 2 10
<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN 23
place close to UA1 pin6
1
HDA_SDOUT_R 11 CBN
<12> HDA_SDOUT_R Place RA9 close to codec SDATA-OUT Place CA29 close to Codec
RF@ CA69
22 2 1
CBP
33P_0402_50V8J
CA29 1U_0603_10V6K
2
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
1 1 1
1 2
RA62 100K_0402_5% 2 7
SPDIFO/GPIO2 DC DET/EAPD
5 1 2 2 2 2
<30> DMIC0 GPIO0/DMIC-DATA RA44 100K_0402_5%
DMIC_CLK0 1 2 DMIC_CLK_CODEC 6 39 1 2
<30> DMIC_CLK0 EMI@ RA14 22_0402_5% GPIO1/DMIC-CLK LDO1-CAP CA51 10U_0603_10V6M
17 1 2
LDO2-CAP CA52 10U_0603_10V6M
+3.3V_RUN_AUDIO INT_SPK_L+ 42 13 1 2
SPK-L+ LDO3-CAP CA53 10U_0603_10V6M
INT_SPK_L- 43
Place closely to Pin 14. SPK-L- 1 2
+3.3V_RUN_AUDIO
100K_0402_1% 200K_0402_1%
1
INT_SPK_R- 44 RA18 10K_0402_5%

SPK-R-
RA59
INT_SPK_R+ 45 3 PD# 1 2
SPK-R+ PD CA31 1U_0603_10V6K RF Request
24 1 2
2
AUD_SENSE_A CPVEE CA49 1U_0603_10V6K +3.3V_RUN_AUDIO

AUD_SENSE_A
0.1U_0402_25V6
1 31 1 2
1
HP1/LINE1 JD MIC2-CAP
@ CA41
CA25 10U_0603_10V6M
AVSS2
AVSS1
PGND
1 2 AUD_SENSE_B 48 38 1 2
RA60
+3.3V_RUN_AUDIO HP2/LINE2 JD VREF

RA61 100K_0402_5% CA35 2.2U_0402_6.3V6M
2
ALC3253-CG_MQFN48_6X6
2
18
37
49
AUD_HP_NB_SENSE
Add for solve
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
pop noise and 1 1
detect issue
2 2
CLASS-D POWER DOWN CONTROL CIRCUIT

Add this Filter to avoid other HP-Out-Right Nokia-MIC
components/chips be influenced
HP-Out-Lef t iPhone-MIC
1 2
@ RA48 0_0402_5%
place at AGND and DGND plane
680P_0402_50V7K
@ESD@ CA13
1 2 @ DA8 1 2 1
<36> NB_MUTE#
@ RA35 0_0402_5%
RB751S-40 SOD-523 PD#
Global Headset
1
@ RA36
2
1
PJP19
2
<12> HDA_RST#_R
1 2 2 Universal Jack
0_0402_5% @ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
PAD-OPEN1x1m JHP1
1 2 7
@ RA37 0_0402_5% RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
DE2@two control lines1 AUD_HP_OUT_L @EMI@RA52 1 2 0_0402_5% AUD_HP_OUT_L1 1 #4 G/M
#1 L/R Normal
Open
5
#5
A A
AUD_HP_NB_SENSE 6
#6 AGND
AUD_HP_OUT_R @EMI@RA53 1 2 0_0402_5% AUD_HP_OUT_R1 2
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R/L
PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
+5V_RUN
1 2
+5V_RUN_AUDIO SINGA_2SJ3095-085111F
@ESD@CA1
@EMI@ CA2
@EMI@ CA3
@ESD@ CA4
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
ESD@ CONN@
3
+5V_RUN_AUDIO PAD-OPEN1x2m DA3
2.5A Link SINGA_2SJ3095-085111F DONE
680P_0402_50V7K
330P_0402_50V7K
330P_0402_50V7K
680P_0402_50V7K
ESD@
ESD@
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
Reserve for support D3 cold 20160308
1
PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
DA1
DA2
PAD-OPEN1x1m
+5V_RUN PAD-OPEN1x1m
500mA
@ UZ5
2
1
1 14 +5V_RUN_AUDIO_UZ5 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<12> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126
4 11
+5V_ALW
5
VBIAS GND
10 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K
6 9 @ PJP16
+3.3V_RUN VIN2 VOUT2 +3.3V_RUN_AUDIO_UZ5
7 8 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
GPAD PAD-OPEN1x1m
EM5209VF_SON14_2X3 1 2
@ CZ128 0.1U_0201_10V6K
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec ALC3253
2 1
5 4 3 2 1
+3.3V_ALW
2 1 +RTC_CELL_VBAT
For KW UPD2_SMBDAT
RE302
1 2
2.2K_0402_5%
+RTC_CELL UPD2_SMBCLK
@ RE32 0_0402_5% 1 2
0.1U_0201_10V6K
1 RE303 2.2K_0402_5%
UPD2_SMBINT#
CE11
1 2
+3.3V_ALW_UE1 RE91 100K_0402_5%
UPD1_SMBINT# 1 2
2
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP22 RE92 100K_0402_5%
1 2 VOL_UP# 1 2
+3.3V_ALW 1 1
1
CE13
CE14
CE23
@ RE519 10K_0402_5%
VOL_DOWN#
10U_0603_6.3V6M
PAD-OPEN1x1m 1 2
1
@ RE520 10K_0402_5%
MP uses SA00009GL30
2
2 2 PBAT_CHARGER_SMBDAT
CE16
1 2
20161213 RE37 2.2K_0402_5%
2
UE1 PBAT_CHARGER_SMBCLK 1 2
F2 TYPEC_ID RE43 2.2K_0402_5%
GPIO033/RC_ID0 SYSTEM_ID TYPEC_ID <37> NGFF_CONFIG_1
A2 J10 SYSTEM_ID <37>
1 2
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK J13 BOARD_ID RE562 2.2K_0402_5%
D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT BOARD_ID <37> SIO_SLP_SUS#_R D
B7 E7 1 2
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_SMBCLK UPD2_SMBDAT <25>
+3.3V_ALW_UE1
2 1 D7 NDS3@RE561 100K_0402_5%
GPIO004/SMB00_CLK/SPI0_MOSI UPD2_SMBCLK <25>
0.1U_0201_10V6K
0.1U_0201_10V6K
100_0402_1% RE314 K2 RPE12

VREF_ADC ISH_I2C1_SCL_EC
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 1 8
+3.3V_EC_PLL GPIO057/VCC_PWRGD GPS_DISABLE# RUNPWROK <14> ISH_I2C1_SDA_EC
CE19
CE20
@ CE17
F1 H5 2 7
VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <33> UPD1_SMBCLK
CE18
G11 3 6
GPIO104/UART0_TX HOST_DEBUG_TX <33,37> UPD1_SMBDAT
H1 G12 4 5
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FWP <12>
B13
GPIO127/A20M/UART0_CTS# UPD1_SMBINT# ME_SUS_PWR_ACK <11>
G8 F10 2.2K_0804_8P4R_5%
M9 VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# <26> RPE9
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_WAKE#_R
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 1 8
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <37> NGFF_CONFIG_2 2 7
+3.3V_ALW_UE1 PCH_DPWROK_EC GPIO026/TIN1 SIO_SLP_S4# <11,17,49,52> NGFF_CONFIG_0
1 2 0_0402_5% F8 M11 3 6
<11> PCH_DPWROK RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <11> NGFF_CONFIG_3
RF Request @DS3@RE536 E8 H9 4 5
<37> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <11>
0.1U_0201_10V6K
1 M12
+3.3V_ALW <9> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120 VGA_IDENTIFY
C2 L9 100K_0804_8P4R_5%
<33> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 VCCDSW_EN
CE15
F9 M10
<47,56> PBAT_PRES# SIO_SLP_SUS#_R GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 <32,33>
0.1U_0402_25V6
1 2 N4 N9 RPE11
2 <11> SIO_SLP_SUS# PCH_ALW_ON GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <33> USB_PWR_EN2#
DS3@ RE349 43K_0402_1% M8 1 8
<44> PCH_ALW_ON GPIO231 USB_POWERSHARE_EN#
@ CE66
K8 C11 2 7
<11> AC_PRESENT BREATH_LED# <43>
1
GPIO233 GPIO156/LED0 D10 USB_PWR_EN1# 3 6
GPIO157/LED1 BAT1_LED# <43> USB_POWERSHARE_VBUS_EN
<8> SML1_SMBDATA
E11 D11 4 5
GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <43>
Close to pin H1 D8 E1
2
<8> SML1_SMBCLK WWAN_WAKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <30>
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
1 1 M13 100K_0804_8P4R_5%
<33> WWAN_WAKE# K12 GPIO110/PS2_CLK2 E5
<11> SUSACK# WLAN_WIGIG60GHZ_DIS# L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT <37,38,45> AC_DIS
B3 1 2
<33> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 USH_EXPANDER_SMBCLK <37,38,45>
K11 M7 @ RE83 100K_0402_5%
2 2 @1
<11,14> SIO_PWRBTN# VCCST_PWRGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 SAR_DPR# VCCDSW_EN <11> GPS_DISABLE#
2 M4 1 2
<11,14,37> VCCST_PWRGD GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT SAR_DPR# <33>
RE308 1 2 0_0402_5%
<37> LID_CL_SIO#
N11 M3 RE12 100K_0402_5%
<44> SLP_WLAN#_GATE GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <47,56> WLAN_WIGIG60GHZ_DIS#
@ RE552 0_0402_5% E10 N2 1 2
<42> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <47,56>
C12 N10 NGFF_CONFIG_2 <33> RE8 100K_0402_5%
<42> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA LED_MASK# WWAN_WAKE#
A12 1 2
change to PS2 JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 ISH_I2C1_SDA_EC @ RE516 1 2 0_0402_5% RE38 10K_0402_5%
+3.3V_ALW <37> JTAG_TDI JTAG_TDO GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# ISH_I2C1_SCL_EC ISH_I2C1_SDA <9,45> LED_MASK#
F6 F7 @ RE517 1 2 0_0402_5% 1 2
<37> JTAG_TDO JTAG_CLK GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# UPD1_SMBDAT ISH_I2C1_SCL <9,45>
C8 B4 RE21 10K_0402_5%
<37> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <26>
C5 C3 THERMTRIP1# 1 2
<37> JTAG_TMS UPD1_SMBCLK <26>
@ RE526 2 1 10K_0402_5% USH_DET# JTAG_RST# G13 GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# RE301 10K_0402_5%
JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5%
GPIO200/ADC00 I_BATT <56>
RE532 2 1 4.7K_0402_5% BCM5882_ALERT# E3 J5 I_SYS_R RE312 1 2 300_0402_5% PCIE_WAKE#_R 1 2
<37> TACH_FAN1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 I_SYS <53,56>
D1 J6 RE35 10K_0402_5%
<43> VOL_UP# LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 VOL_DOWN# <43> LID_CL_SIO_TAB#
M2 G2 @ RE318 1 2 0_0402_5% 1 2
<30> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 USH_PWR_STATE# TOUCHPAD_INTR# <12,42>
L10 H2 RE5 10K_0402_5%
C <37> PWM_FAN1 GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POWERSHARE_VBUS_EN USH_PWR_STATE# <38> BC_DAT_ECE1117 C
L11 J2 1 2
<22> DISPLAY_HPD_EC# PCH_RSMRST# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POWERSHARE_EN# USB_POWERSHARE_VBUS_EN <40>
M5 J3 RE365 100K_0402_5%
Modify 0523 <42> PCH_RSMRST# J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_PWR_EN1# USB_POWERSHARE_EN# <40> WWAN_RADIO_DIS# 1 2
<9> NB_MODE# GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <41>
<30> BIA_PWM_EC N1 D3 RE10 100K_0402_5%
TBT_RESET_N_EC_R GPIO001/PWM4 GPIO210/ADC08 LOM_CABLE_DETECT# AUX_EN_WOWL <44> BT_RADIO_DIS#
1 2 L8 D2 1 2
<23,25,26> TBT_RESET_N_EC @ RE506 0_0402_5% HW_ACAVIN_NB N6 GPIO002/PWM5 GPIO211/ADC09 E2 +3.3V_RUN RE11 100K_0402_5%
T266 @ PAD~D GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 USB_PWR_EN2# BC_INT#_ECE1117 <42> LOM_CABLE_DETECT#
J9 G5 1 2
<30> PANEL_BKEN_EC H11 GPIO015/PWM7 GPIO213/ADC11 F5 UPD2_SMBINT# RE505 100K_0402_5%
<35> BEEP GPIO035/PWM8/CTOUT1 GPIO214/ADC12 DCIN1_EN UPD2_SMBINT# <25> 3.3V_TS_EN
PJP20 D9 K4 @ RE601 2 1 0_0402_5% 1 2
1 2 <11,44> SIO_SLP_WLAN# AC_DIS H12 GPIO133/PWM9 GPIO215/ADC13 L1 PCH_PCIE_WAKE# DCIN2_EN_R <57> @ RE557 100K_0402_5%
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <56> AC_DIS
G10 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 L3
PCH_PCIE_WAKE# <11,23,37> +RTC_CELL
1 <38> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11>
PAD-OPEN1x1m MSCLK H10
<37> MSCLK GPIO170/TFDP_CLK/UART1_TX CV2_ON_R VCI_IN1#
CE22 MSDATA G9 H8 RE539 1 2 100_0402_5% 1 2
<37> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ 3.3V_TS_EN CV2_ON <38>
0.1U_0201_10V6K 1 CE21 J7 RE507 100K_0402_5%
2 0.1U_0201_10V6K A4 GPIO223/SHD_IO0 L6 MASK_SATA_LED# 3.3V_TS_EN <30> VCI_IN2# 1 2
<35> NB_MUTE# EN_INVPWR B2 GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7 1.8V_PRIM_PWRGD MASK_SATA_LED# <43> RE508 100K_0402_5%
@ PJP21 RE362 2 1 100K_0402_5% <30> EN_INVPWR RESET_IN# C1 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 M6 VBUS1_ECOK 2 1.8V_PRIM_PWRGD
1 <52>
2 +3.3V_ALW IMVP_VR_ON_EC GPIO024/GPTP-IN2 GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS2_ECOK_R <57>
1 2 Close to pin N5 N7 @ RE603 0_0402_5%
+3.3V_ALW <37> IMVP_VR_ON_EC GPIO031/GPTP-OUT1
K9 D6 RE59 close to UE2 at least 250mils
<11,23,37> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <38> +PECI_VREF I_BATT_R
PAD-OPEN1x1m N8 C7 2 1 CE3 1 2 2200P_0402_50V7K
<11> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <56> +1.0V_VCCST
A5 @ RE59 0_0402_5%
P_SENSOR_ACT#_EC VCI_OUT ALWON <48> I_SYS_R
0.1U_0201_10V6K
RTD3@ RE509 1 2 0_0402_5% F13 D5
POWER_SW_IN# <37> CE4 1 2 2200P_0402_50V7K
<23> RTD3 SELECT E13 GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 VCI_IN1#
<57> AC_DISC#
1
GPIO124/nRESETI GPIO162/VCI_IN1# VCI_IN2#
CE25
C13 D4
<38> USH_DET# LID_CL_SIO_TAB# GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_WAKE#
RPE10 E12 E4
CV2_ON_R <45> LID_CL_SIO_TAB# GPIO126/PVT_IO3 GPIO000/VCI_IN3# POA_WAKE# <38>
8 1
2
7 2 IMVP_VR_ON_EC RTCRST_ON F11 PCH_RSMRST# 1 2
6 3 PCH_ALW_ON F12 GPIO122/BCM0_DAT/PVT_IO1 C6 RE342 10K_0402_5%
RUN_ON_EC <33> WWAN_RADIO_DIS# GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <44> SYS_PWROK
5 4 D12 1 2
<42> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
D13 F3 @ CE54 1 2 10P_0402_50V8J RE56 10K_0402_5%
<42> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT I_SYS_R
100K_0804_8P4R_5% 1 2
@
F4 RE313 10K_0402_5%
3.3V_ALW2 <33> NGFF_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF LCD_TST
@ RE57 2 1 1K_0402_5% B1 J11 1 2
+3.3V_ALW2 UPD1_HPD SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
K7 K13 RE60 1 2 43_0402_5% RE20 100K_0402_5%
PECI_EC <12>
1
@ RE602 1 2 0_0402_5% VBUS2_ECOK N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 EN_INVPWR 1 2

<57> VBUS1_ECOK_R GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N M3042_PCIE#_SATA <10>
100K_0402_5%
K6 A8 CE24 1 2 2200P_0402_50V7K RE55 100K_0402_5%

<8,37> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P TBT_RESET_N_EC_R
RE58
H7 A7 1 2
<8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE1_N
+3.3V_ALW K1 A10 CE26 1 2 2200P_0402_50V7K RE95 100K_0402_5%
<37> PCH_PLTRST#_5105 ESPI_CLK_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE1_P REM_DIODE1_N <37>
G7 A9
100K_0402_5%
REM_DIODE1_P <37>
2
<8,37> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE2_N

REM_DIODE2_N <37>
2
<8,37> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8 REM_DIODE2_P

<8,37> ESPI_IO0 REM_DIODE2_P <37>
RE63
L4 GPIO070/LAD0/ESPI_IO0 DP3_DN3A A11 REM_DIODE4_N CE27 1 2 2200P_0402_50V7K

B <8,37> ESPI_IO1 B
G6 GPIO071/LAD1/ESPI_IO1 DN4_DP4A B10 REM_DIODE4_P +RTC_CELL
<8,37> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_N
L5 C10
<8,37> ESPI_IO3 TP_DISABLE#_EC GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 REM_DIODE4_P REM_DIODE4_N <37>
L2 C9 VSET_5105 <37> REM_DIODE4_P <37>
1
UPD2_HPD M1 GPIO067/CLKRUN# VSET B11

RESET_OUT GPIO100/nEC_SCI VCP I_ADP <56> POA_WAKE#
@ RE548 1 2 0_0402_5% G4 H3 THERMTRIP2# 1 2
VSS_ANALOG
JTAG_RST# <11,14> SYS_PWROK DCIN2_EN GPIO106/PWROK GPIO103/THERMTRIP2# THERMTRIP2# <37>
@ RE600 1 2 0_0402_5% L12 B12 THERMTRIP1# RE324 100K_0402_5%
<57> DCIN1_EN_R GPIO107/nSMI THERMTRIP1# PROCHOT#_R1
VSS_ADC
H13 1 2
VSS_PLL
VR_CAP
MEC_XTAL1 A1 GPIO160/PWM11/PROCHOT# RE288 100_0402_5% PROCHOT# <12,53,56> +3.3V_ALW
1
MEC_XTAL2_R A3 XTAL1
VSS1
VSS2
VSS3
XTAL2
1U_0402_6.3V6K
1
VGA_IDENTIFY
@SHORT PADS~D
JTAG1 CONN@
100_0402_1%
1 2
1
@ RE65
MEC5105_WFBGA169_11X11 RE84 100K_0402_5%

A6
A13
E6
H4
1+VR_CAP J1
C4
G1
VGA_IDENTIFY
CE30
1 2
1U_0402_6.3V6K
@ RE85 100K_0402_5%
2
+VSS_PLL
2
+RTC_CELL_PCH +RTC_CELL
2
+1.8V_3.3V_ALW_VTR3 +3.3V_RUN QE15

LP2301ALT1G_SOT23-3 +RTC_CELL_PCH +RTC_CELL
VGA_ID0
2
+1.8V_3.3V_ALW_VTR3
CE31
2
2
RE529 UE10 1 3 0
Discrete
S
10K_0402_5% RE555 1 2
1U_0402_6.3V6K
10K_0402_5%
1 5 @RE551 0_0402_5% 1
10K_0402_5% UMA
1
NC VCC
G
1
2
1
TP_DISABLE#_EC
RE546
2
1
A +3.3V_RUN
CE63
4
3 Y TP_DISABLE# <42>
2
GND DE2
2
2
+3.3V_ALW
10K_0402_5% DMN65D8LDW-7_SOT363-6
74AUP1G07SE-7 SOT353 2 1
RE67
This change for AR only because EC code need to align on AR & NAR RB751S-40 SOD-523
1
D RE543 @ RE94
100K_0402_5%
1
2
1 2 UPD2_HPD RUNPWROK QE17 2RTCRST_ON_R 1 2 1 2 RTCRST_ON 1 2

<23,26> TBTB_HPD L2N7002WT1G_SC-70-3 G @ RE565 0_0402_5% 75_0402_5% PCH_RTCRST# <11>
RE68
1
MEC_XTAL2_R D
0.1U_0402_25V6
For EMI request DZ106 S 1M_0402_5%
3
RTCRST_ON
22P_0402_50V8J
100K_0402_5%
RB751S-40 SOD-523 2 @ QE12
3
2
ESPI_CLK_5105 UPD1_HPD
@ CE64
8/28 schematic review 1 2 G L2N7002WT1G_SC-70-3
1
1
<23,25> TBTA_HPD
QE2B
RE541
S
3
1
CE65
DZ107 @ RE93
33_0402_5%
1
@RE290 RB751S-40 SOD-523 RUN_ON# 5

@EMI@
A A
32 KHz Clock
2
2
<44> RUN_ON# 100K_0201_5%
0_0402_5%
RE350
1
2
2
+1.8V_3.3V_ALW_VTR3
YE1
2
QE2A
MEC_XTAL1 MEC_XTAL2
33P_0402_50V8J
1 2
1 2 UPD2_HPD 2
@EMI@
<17,37,44,51> RUN_ON
1
10P_0402_50V8J
10P_0402_50V8J
RE554 1M_0402_5%
UPD1_HPD
CE57
32.768KHZ_9PF_X1A000141000200 1 2
1
1
RE553 1M_0402_5%
2
CE28
CE29
0601 change PN to SJ10000Q400

2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EC MEC5105
5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_ALW_VTR3 +RTC_CELL
PCIE_WAKE# <23,33,39>
+3.3V_ALW
1
100K_0402_5%
UE6
RE31
RE340 @ CE10
1 5 10K_0402_5% 1 2 2 1 1 2
NC VCC <36> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,23,36>
@ RE275 0_0402_5% 0_0402_5% @ RE274
2 1U_0402_6.3V6K
2
<11> PCH_PLTRST#_EC A 4
3 Y PCH_PLTRST#_5105 <36> 1 2
<36> POWER_SW_IN# Stuff RE275 and no stuff RE274 keep E5 design
GND POWER_SW#_MB <11,43> Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
RE33 10K_0402_5%
1U_0402_6.3V6K
74AUP1G07SE-7 SOT353
CE12
2 1
2
0_0402_5% @ RE304
+3.3V_ALW
@ CE53
+3.3V_ALW 1 2
+3.3V_ALW
100K_0402_5%
UE4
1
RE25
0.1U_0402_25V6K
5
D 1 5 D
IMVP_VR_ON_EC 1 NC VCC
P
<36> IMVP_VR_ON_EC B IMVP_VR_ON
4 2
SIO_SLP_S3# 2 O A 4
RE26 <11,23,36,37> SIO_SLP_S3#
2
LID_CL_SIO# A Y VCCST_PWRGD <11,14,36>
G
2 1 UE3 3
<36> LID_CL_SIO# LID_CL# <45> GND
.047U_0402_16V7K
TC7SH08FU_SSOP5~D
3
10_0402_5% 74AUP1G07SE-7 SOT353
CE8
RF Request
2
IMVP_VR_ON <53>
+3.3V_ALW 1 2
0_0402_5% @ RE280
68P_0402_50V8J
1
RUN_ON_EC 2 1
RF@ CE61
<36> RUN_ON_EC RUN_ON <17,36,44,51>
0_0402_5% @ RE292
CONN@ +3.3V_RUN 2
JESPI
1 +3.3V_ALW
1 2 @ CE52
2 3 1 2
3 ESPI_IO0 <8,36>
4 ESPI_IO1 <8,36>
4 5 0.1U_0402_25V6K
5 ESPI_IO2 <8,36>
5
6
6 7 ESPI_IO3 <8,36> 1
P
7 8 20_0402_5% PCH_PLTRST#_EC ESPI_CS# <8,36> B
LPC@ RE375 1 4
11 8 9 @ RE560 1 20_0402_5% ESPI_RESET# 2 O
GND 9 ESPI_RESET# <8,36> A
G
12 10 UE5
GND 10 ESPI_CLK_5105 <8,36>
TC7SH08FU_SSOP5~D
3
JXT_FP241AH-010GAAM
+3.3V_ALW +3.3V_ALW
+3.3V_ALW
1
C RE300 C
4.3K_0402_5%
130K_0402_5%
2
RE79
RE343
2
BOARD_ID SYSTEM_ID
33K_0402_5% <36> BOARD_ID <36> SYSTEM_ID
1
1
CE40 CE47
4700P_0402_25V7K 4700P_0402_25V7K
2
TYPEC_ID
<36> TYPEC_ID
RE79 CE40 REV RE300 CE47 PANEL SIZE
1
TYPEC_ID
CE62
4700P_0402_25V7K 240K 4700p X00 240K 4700p 11"
2
130K 4700p X01 * 130K 4700p 12"
CHECK
* 62K 4700p X02 62K 4700p 13"
33K 4700p X03 33K 4700p 14"
RE343 CE40 REV 8.2K 4700p Reserve 8.2K 4700p 15"
240K 4700p Single Port ACE w/o AR 4.3K 4700p A00 4.3K 4700p 17"
130K 4700p Single Port ACE w/AR 2K 4700p 2K 4700p 15P
62K 4700p Dual Port ACE w/o AR 1K 4700p 1K 4700p
* 33K 4700p Dual Port ACE w/AR
8.2K 4700p Dual Port ACE (w/AR +w/o AR) BOARD_ID rise t i mei s meas ur ed fr o m5 %~68 %. PANEL_ID rise t i mei s meas ur ed fr o m5 %~68 %.
4.3K 4700p VSET_5105
2K 4700p VSET_5105 <36>
0.1U_0402_25V6
1K 4700p
1
1.58K_0402_1%
1
CE38
RE77
2
+3.3V_ALW
2
1
8
7
6
5
10K_8P4R_5%
10_0402_1%
RE71
RPE7
Rest=1.58K , Tp=96 degree
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
Rest=1.33K , Tp=93 degree
@ RE75
CONN@
Link ACES_50278-0040N-001 DONE
1
2
3
4
RE72
RE73
RE74
B JDEG1 B
+EC_DEBUG_VCC
1
1
2 JTAG_TDI 20160331
2
2 3 JTAG_TMS JTAG_TDI <36>
JFAN1
3 4 JTAG_CLK JTAG_TMS <36> 1
4 5 JTAG_TDO JTAG_CLK <36> 1 2 PWM_FAN1
RE86
5 6 JTAG_TDO <36> 2 3 TACH_FAN1 PWM_FAN1 <36>
MSCLK 10K_0402_5%
6 7 1 2 +3.3V_RUN 3 4 TACH_FAN1 <36>
MSDATA
Control Byte 7
8
8
DEBUG_TX
HOST_DEBUG_TX 4 +5V_RUN
10U_0603_6.3V6M
11 9 5
GND 9 GND
1
0 1 0 0 A2 A1 A0 R/W 12 10 6
GND 10 PWM_FAN1 GND
1
1 2 1 2 DE1 @
<9> SBIOS_TX
CE32
R/W = 0 = Write JXT_FP241AH-010GAAM @ RE306 RE48 10K_0402_5% ACES_50278-0040N-001 BZV55-B5V6_SOD80C2
0_0402_5% 1 2 TACH_FAN1
R/W = 1 = Read CONN@
2
RE51 10K_0402_5%
HOST_DEBUG_TX <33,36>
2
+3.3V_ALW
SMBus address 0x40 MSDATA <36>
MSCLK <36>
1 2
@ RE30
+3.3V_ALW 0_0402_5%
1
1
0.1U_0402_25V6K
1U_0402_6.3V6K
@ @ Thermal diode mapping

CE501
CE502
2
2
+3.3V_ALW 5085 Channel Locat i on
Place under CPU
Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
REM_DIODE1_P <36>
@ RE500
@ RE502
@ RE527
@
@UE2
RE504
100P_0402_50V8J
DP2/DN2 AR (QE5)
1
18 C
VSTBY33
@ CE35
2
2
19 DN2a/DP2a DDR (QE7) B
1
<37,39,46> USH_EXPANDER_SMBCLK 20 SCL
WRST# E QE3
<37,39,46> USH_EXPANDER_SMBDAT
3
SDL 16 LMBT3904WT1G SC70-3
GP7
1
NA
1U_0402_6.3V6K
@
1
2 A2 GP6
15
14
DP3/DN3 REM_DIODE1_N <36>
A1 GP5
CE500
3 13
DP2/DN2 for WiGig on QE5, place QE5 close
2
A0 GP4
WRST# 4 GP3
12
11 MW_2 @ RE518 1 20_0402_5%
DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
WRST# GP2 10 MW_1 @ RE550 1 20_0402_5%
EXPANDER_ALERT# GP1
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
7 9
T267 @ PAD~D INT GP0
@ @ @ DP4/DN4 for Skin on
RE501
RE503
RE528
5
6 NC CHECK RE69 QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
NC Vcore VR choke. to DDR and CE46 close to QE7
0.1U_0402_25V6
8 17 1 2
+3.3V_ALW THERMTRIP2# <36>
2
NC VSS 21
EPAD +1.0VS_VCCIO REM_DIODE4_P <36> REM_DIODE2_P <36>
8.2K_0402_5%
LMBT3904WT1G SC70-3
SIO_SLP_S3# <11,23,36,37>
1
LMBT3904WT1G SC70-3
CE36
100P_0402_50V8J
@ QE11
2
1
100P_0402_50V8J
100P_0402_50V8J
@ CE37
QE7
MCP23008T_QFN20P
E C
G
1
@ CE46
C C B
2 2
2
QE4
@CE39
A 1 3 1 2 2 2 B A
2
RE70 2.2K_0402_5% B B E QE5
C
D
Link MCP23008 OK
3
+1.0V_VCCST E E QE6 LMBT3904WT1G SC70-3
3
L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3
@ RE90 1 2 0_0402_5% REM_DIODE2_N <36>

<12> H_THERMTRIP# REM_DIODE4_N <36>
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MEC5105 support
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-F292P
5 4 3 2 1
5 4 3 2 1
RF Request RF Request
For NUVOTON TPM +3.3V_ALW +3.3V_M_TPM
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0201_50V8J
RF@ CZ59
68P_0201_50V8J
RF@ CZ60
1 1 1 1
@ RZ367 1 2 0_0402_5%
+3.3V_M_TPM
+UZ12_TPM
place CZ50, CZ75 as close as UZ12.8
D @ RZ89 1 2 0_0402_5% D
+3.3V_RUN 2 2 2 2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1 1
CZ75
CZ50
+3.3V_ALW 2 2
@ RZ369 1 2 0_0402_5%
+3.3V_ALW_PCH +3.3V_ALW
@ RZ368 1 2 0_0402_5%
+3.3V_M_TPM
2
KW pop RZ8/RZ9 because
PJP391 share I2C on USH/SAR/ALS
1 2 TPM_PIRQ#
PAD-OPEN1x1m
RZ69 10K_0402_5% +3.3V_ALW
1 2 USH_EXPANDER_SMBCLK
1
RZ8 2.2K_0402_5%
+3.3V_ALW_UZ12 1 2 USH_EXPANDER_SMBDAT
RZ9 2.2K_0402_5%
0.1U_0201_10V6K
10U_0603_10V6M
1 2 USH_PWR_STATE#
1 1 place CZ51,CZ52 as close as UZ12.1
+3.3V_RUN RZ10 100K_0402_5%
CZ51
CZ52
1
2 2
@ RZ362
10K_0402_5%
USH CONN
UZ12
1
2
C 1 2 TPM_GPIO0 29 VSB 1 2 RF@ CZ78 1 2 100P_0402_50V8J C

<11,17,51> SIO_SLP_S0# GPIO0/SDA/XOR_OUT +UZ12_TPM +3.3V_M_TPM
@ RZ112 0_0402_5% 30 8 @ RZ366 0_0402_5% JUSH1
1 2 TPM_LPM# 3 GPIO1/SCL VDD 14 +UZ12_VHIO 1 2 @ RZ85 1 2 0_0402_5% +PWR_SRC_R 1
GPIO2/GPX VHIO +3.3V_RUN +PWR_SRC 1
@ RZ363 0_0402_5% 6 22 @ RZ365 0_0402_5% 2
GPIO3/BADD VHIO 2
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
3
2 33_0402_5% PCH_SPI_D1_2_R <36> CV2_ON POA_WAKE#_R 3
RZ58 1 24 2 1 1 1 RZ364 1 2 100_0402_5% 4
<8> PCH_SPI_D1_R1 RZ59 1 2 33_0402_5% PCH_SPI_D0_2_R 21 LAD0/MISO NC 7 <36> POA_WAKE# 5 4
<8> PCH_SPI_D0_R1 TPM_PIRQ# LAD1/MOSI NC <36> EC_FPM_EN 5
CZ54
CZ53
CZ55
18 10 6
<9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 7 6
LAD3 NC 25 2 2 2 8 7
2 33_0402_5% PCH_SPI_CLK_2_R 19 NC <10> USB20_N10 8
EMI@ RZ60 1 26 9
<8> PCH_SPI_CLK_R1 @ RZ61 1 2 0_0402_5% PCH_SPI_CS#2_R 20 LCKL/SCLK NC 31 <10> USB20_P10 10 9
<8> PCH_SPI_CS#2 17 LFRAME#/SCS# NC 11 10
<11> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9 <36,37,45> USH_EXPANDER_SMBCLK 12 11
TPM_GPIO4 13 SERIRQ GND 16 <36,37,45> USH_EXPANDER_SMBDAT 13 12
T283@ PAD~D CLKRUN#/GPIO4/SINT# GND <36> BCM5882_ALERT# 13
28 23 CZ53,CZ55 as close as UZ12.14 14
LPCPD# GND 14
1
10K_0402_5%
@ RZ62
32 CZ54 as close as UZ12.22 15

4 GND 33 16 15
PP PGND +3.3V_ALW 16
5 12 17
TEST Reserved 18 17
+5V_ALW 18
NPCT750JAAYX_QFN32_5X5 19
+3.3V_RUN
2
20 19
+5V_RUN USH_RST#_R 20
@ RZ114 1 2 0_0402_5% 21
<11,23,30,33,39> PCH_PLTRST#_AND DZ8 22 21
2 1<36> USH_PWR_STATE# CONTACTLESS_DET#_R 23 22
<12> CONTACTLESS_DET# 24 23
RB751S-40 SOD-523 25 24
@ RZ87 1 2 0_0402_5% USH_DET#_R 26 25
<36> USH_DET# 26
Pop Depop Comment 27
DZ7
2 1 28 GND1
VDD - V_RUN Power PCH_SPI_CLK_2_R GND2
B
NPCT65x RZ89, RZ366, RZ62, RZ363 RZ365, RZ367, RZ112 VHIO - V_SPI Power B
RB751S-40 SOD-523 CVILU_CF5026FD0RK-05-NH
33_0402_5%
Option1 (recommended) CONN@
@EMI@
NPCT75x RZ89, RZ365, RZ112 RZ367, RZ366, RZ62, RZ363 VDD and VHIO - V_RUN power
RZ63
Option2 (for Z1 sample [early sample])
Link CVILU_CF5026FD0RK-05-NH DONE
NPCT75x RZ367, RZ366 RZ89, RZ365, RZ62 VDD and VHIO - V_SPI power 2016020
1
0.1U_0402_25V6
PCH_PLTRST#_AND Close to JUSH1
1
@EMI@
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
CZ56
.047U_0402_16V7K
ESD@ CZ61
2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
@
2
CZ64
CZ66
CZ67
CZ68
For ESD solution 2 2 2 2
RF Request
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
RF Request
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
USH_EXPANDER_SMBCLK 1 2 1 1 1 1
@RF@CZ62 68P_0402_50V8J
USH_EXPANDER_SMBDAT 1 2
A @RF@CZ63 68P_0402_50V8J 2 2 2 2 A
USH & TPM
1.0
5 4 3 2 1
5 4 3 2 1
For PCIEX4,Kirkwood
RF Request
+3.3V_HDD_M2 +3.3V_HDD_M2
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
68P_0402_50V8J
@RF@CN60
22U_0603_6.3V6M
22U_0603_6.3V6M
1 @ 1
1
CN61
CN62
1
CN63
CN64
2
2
2 2
2
2280 SSD
NGFF slot C Key M

Place near HDD CONN
+3.3V_HDD_M2 2.5A
JNGFF3 CONN@ PJP31
1 2 1 2
Need update! CHECK Kirkwood Port Mapping 3 1 2 4 +3.3V_RUN
PCIE_PRX_DTX_N9 5 3 4 6 PAD-OPEN1x2m
<10> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 5 6 8
<10> PCIE_PRX_DTX_P9 9 7 8 10 NVME_LED# 1 2
PCIE_PTX_C_DRX_N9 9 10 12 SATALED# <10,33,43>
CN65 2 1 0.22U_0402_10V6K 11 @ RN100 0_0402_5%
<10> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 11 12 14
CN66 2 1 0.22U_0402_10V6K 13
<10> PCIE_PTX_DRX_P9 15 13 14 16
PCIE_PRX_DTX_N10 17 15 16 18
<10> PCIE_PRX_DTX_P10 21 19 20 22
C CN67 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N10 23 21 22 24 C
CN68 2 1 0.22U_0402_10V6K 25
<10> PCIE_PTX_DRX_P10 27 25 26 28
PCIE_PRX_DTX_N11 29 27 28 30
<10> PCIE_PRX_DTX_P11 33 31 32 34
CN69 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 35 33 34 36
CN70 2 1 0.22U_0402_10V6K 37
<10> PCIE_PTX_DRX_P11 39 37 38 40 M2_DEVSLP <10>
PCIE_PRX_DTX_P12 41 39 40 42
<10> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 41 42 44
<10> PCIE_PRX_DTX_N12 45 43 44 46
CN71 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N12 47 45 46 48
CN72 2 1 0.22U_0402_10V6K 49
<10> PCIE_PTX_DRX_P12 51 49 50 52 PCH_PLTRST#_AND <11,23,30,33,38>
53 51 52 54 PCIE_WAKE# CLKREQ_PCIE#3 <11>
<11> CLK_PCIE_N3 55 53 54 56 PCIE_WAKE# <23,33,37>
<11> CLK_PCIE_P3 57 55 56 58
57 58
+3.3V_HDD_M2
67 68 SUSCLK_R 1 2
1 2 M2_DEVSLP 69 67 68 70 @ RN99
SUSCLK <11,33>
0_0402_5%
@ RN37 10K_0402_5% <10> m2280_PCIE_SATA# 71 69 70 72
if signal is PCIE GEN3/SATA GEN3 maybe change C value 71 72
or no need for DG0.9 SATA EXPRESS HDD 73 74
75 73 74
75
76
GND 77
GND
B LOTES_YPCI0016-P003A B
Link LOTES_YPCI0016-P003A Done (Key M)

20160315
A A
M2 2280 Socket
1.0
5 4 3 2 1
5 4 3 2 1
For PWR SW + Charger combine IC
+5V_USB_CHG_PWR
DI4 ESD@ JUSB1

USB3_PRX_DTX_N1 1 1 10 9 USB3_PRX_DTX_N1 1
<10> USB3_PRX_DTX_P1 USB20_N9_R VBUS
150U_B2_6.3VM_R35M
2
USB3_PRX_DTX_P1 USB3_PRX_DTX_P1 USB20_P9_R D-
100U_1206_6.3V6M
0.1U_0201_10V6K
D 2 2 9 8 3 D
@ 4 D+
<10> USB3_PRX_DTX_N1 USB3_PTX_C_DRX_N1 4 4 USB3_PTX_C_DRX_N1 1 1 1 USB3_PRX_DTX_N1 GND
CI17
7 7 5
USB3_PRX_DTX_P1 SSRX-
CI32
CI14
PESD5V0U2BT_SOT23-3
ESD@ DI5
+ 6 10
SSRX+ GND
2
USB3_PTX_C_DRX_P1 5 6 6 USB3_PTX_C_DRX_P1 7 11
5
2 2 USB3_PTX_C_DRX_N1 8 GND GND 12
3 3 2 USB3_PTX_C_DRX_P1 9 SSTX- GND 13
SSTX+ GND
8 SANTA_375230-1
CONN@
1
AZ1045-04F_DFN2510P10E-10-9
LINK 375230-1 DONE

USB3_PTX_C_DRX_P1
<10> USB3_PTX_DRX_P1
CI16
2 1
0.1U_0402_25V6
20160315
2 1 USB3_PTX_C_DRX_N1
<10> USB3_PTX_DRX_N1
CI13 0.1U_0402_25V6
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
SW_USB20_N9 1 2 USB20_N9_R
SW_USB20_P9 4 3 USB20_P9_R
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
MCM1012B900F06BP_4P
C C
+5V_ALW
+5V_USB_CHG_PWR 2 2
UI3
1 12
VIN VOUT
2
<10> USB20_N9 3 DM_OUT
<10> USB20_P9 DP_OUT 10 SW_USB20_P9
13 DP_IN 11 SW_USB20_N9
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<36> USB_POWERSHARE_VBUS_EN EN ILIM_L 16 2 1
RI14
ILIM_HI 22.1K_0402_1%
6
<36> USB_POWERSHARE_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
+5V_ALW SLGC55544CVTR_TQFN16_3X3
RI13 2 1 ILIM_SEL CIS Link Seligro SA000097E10 20160304

10K_0402_5% MAIN:SLGC55544CVTR
B +5V_ALW B
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
JUSB1+PS
1.0
5 4 3 2 1
5 4 3 2 1
For Breckenridge/Steamboat 12&Kirkwood

DI1 ESD@
USB3_PRX_DTX_N3 1 1 USB3_PRX_DTX_N3
10 9
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3 4 4 7 USB3_PTX_C_DRX_N3 +USB_EX2_PWR

7 RF Request
USB3_PTX_C_DRX_P3 5 5 6 6 USB3_PTX_C_DRX_P3 +USB_EX2_PWR JUSB2
1
3 3 USB20_N2_R 2 VBUS
USB20_P2_R 3 D-
D+
0.1U_0201_10V6K
8 4
USB3_PRX_DTX_N3 GND
100U_1206_6.3V6M
1 5
SSRX-
1
USB3_PRX_DTX_P3
CI3
D
AZ1045-04F_DFN2510P10E-10-9 6 10 D
SSRX+ GND
CI1
PESD5V0U2BT_SOT23-3
ESD@ DI2
7 11
GND GND
2
<10> USB3_PRX_DTX_P3 USB3_PTX_C_DRX_N3
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ Part Reference
1 1 8 12
2
2 USB3_PTX_C_DRX_P3 9 SSTX- GND 13
LI3 EMI@ SSTX+ GND
<10> USB3_PRX_DTX_N3 USB20_N2 1 2 USB20_N2_R SANTA_375230-1
<10> USB20_N2 2 2
CONN@
1
USB20_P2 4 3 USB20_P2_R
<10> USB20_P2 LINK 375230-1 DONE
MCM1012B900F06BP_4P 20160315
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
2 1 USB3_PTX_C_DRX_P3 +5V_ALW
<10> USB3_PTX_DRX_P3
CI4 0.1U_0402_25V6 UI1
1
2 1 USB3_PTX_C_DRX_N3 5 OUT
<10> USB3_PTX_DRX_N3 IN
CI5 0.1U_0402_25V6 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<36> USB_PWR_EN1# EN
1 3 USB_OC1# <10>
OCB
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT JUSB2
5 4 3 2 1
5 4 3 2 1
RF Request
KB_DET# 1 2
+3.3V_TP RF@ CZ84 68P_0402_50V8J
Touch Pad +3.3V_RUN +3.3V_TP BC_INT#_ECE1117 1
@RF@CZ85
2
68P_0402_50V8J
1
PJP35 RF@CZ83 BC_DAT_ECE1117 1 2
1 2 68P_0402_50V8J @RF@CZ86 68P_0402_50V8J
+3.3V_TP 2
PAD-OPEN1x1m BC_CLK_ECE1117 1 2
@RF@CZ87 68P_0402_50V8J
DAT_TP_SIO_R
4.7K_0402_5%
4.7K_0402_5%
1 2
1
D @RF@CZ88 68P_0402_50V8J D
RZ18
RZ19
CLK_TP_SIO_R 1 2
PS2 @RF@CZ89 68P_0402_50V8J
2
2 1 DAT_TP_SIO_R
<36> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0402_5%
2 1 CLK_TP_SIO_R
<36> CLK_TP_SIO_I2C_DAT
@ RZ23 0_0402_5%
10P_0402_50V8J
10P_0402_50V8J
I2C From EC
Keyboard
1
I2C1_SDA_TP_R JKBTP1 CONN@
CZ80
CZ81
2 1
@ RZ348 0_0402_5% KB_DET# 1
2
2 1 I2C1_SCK_TP_R <12> KB_DET# 2 1
@ RZ349 0_0402_5% 3 2
4 3 +3.3V_TP +3.3V_ALW +5V_RUN
5 4
+5V_RUN 5
I2C From EC 6
+3.3V_ALW BC_INT#_ECE1117 6
7
<36> BC_INT#_ECE1117 BC_DAT_ECE1117 7
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
8 1 1 1
<36> BC_DAT_ECE1117 8
@
9
BC_CLK_ECE1117 9
CZ90
CZ91
CZ92
10
+3.3V_TP +3.3V_TP <36> BC_CLK_ECE1117 11 10
<36> TP_DISABLE# 12 11 2 2 2
+3.3V_TP DAT_TP_SIO_R 12
13
CLK_TP_SIO_R 13
10K_0402_5%
10K_0402_5%
14
14
1
2.2K_0402_5%
2.2K_0402_5%
@ @ 15
15
RZ116
RZ117
16
<12,36> TOUCHPAD_INTR# 16
RZ20
RZ21
17
C I2C1_SDA_TP_R 18 17 Place close to JKBTP1 C
I2C1_SCK_TP_R 19 18
2
20 19
2
2
Reserve for future use 20
1 2 I2C1_SDA_TP_R
<9> I2C1_SDA_TP @ RZ26 0_0402_5%
1 2 I2C1_SCK_TP_R 21
<9> I2C1_SCK_TP @ RZ29 22 GND
0_0402_5%
GND Link CVILU_CF5020FD0R0-05-NH DONE
I2C From CPU 20160321
CHECK PIN DEFINE CVILU_CF5020FD0RK-05-NH
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
1
P
<36> PCH_RSMRST# B 4
O PCH_RSMRST#_AND <11,14>
2
<11,48> ALW_PWRGD_3V_5V A
G
UZ6
3
TC7SH08FU_SSOP5~D
A A
Keyboard
1.0
5 4 3 2 1
5 4 3 2 1
Bat t er y LE D
HDD LED MUX
means EC can switch battery white led and HDD LED by hot key “ Fn+ H”
<36> MASK_SATA_LED#
1 2 BATT_WHITE#
BATT_WHITE# <36,43> BAT2_LED#
RZ25 330_0402_5%
1 2 BATT_YELLOW#
<36> BAT1_LED#
5
RZ28 150_0402_5%
D D
4 3 BAT2_LED#_R
<10,33,39> SATALED#
@ QZ2B
3
R1/R2=10K
+3.3V_ALW DDTA114EUA-7-F_SOT323-3
QZ3
@
1
2
1 6 BAT2_LED#_R
<36,43> BAT2_LED#
1 2
@ QZ2A @ RZ511 150_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
POWER & INSTANT ON SWITCH
C
For NPI USE <36> BREATH_LED#
1
RZ32
2 BREATH_WHITE_LED_SNIFF#
150_0402_5%
C
@
2 SW3 1
<11,37,43> POWER_SW#_MB
4 3
SKRBAAE010_4P
PWR board CONN LED board CONN

+5V_ALW
+5V_ALW
JLED1
JPWR1 1
1 BATT_YELLOW# 2 1
2 1 BATT_WHITE# 3 2
<11,37,43> POWER_SW#_MB 3 2 4 3
<36> VOL_UP# 4 3 5 4
<36> VOL_DOWN# BREATH_WHITE_LED_SNIFF# 5 4 6 5
6 5 6 7
7 6 GND 8
8 GND GND
GND CVILU_CF61062D0R0-05-NH
ACES_50208-0060N-P01 CONN@
CONN@
B B
Link ACES_50208-0060N-P01 done

20160321
Link CVILU_CF61062D0R0-05-NH done
20160829
CLP1 CONN@ CLP2 CONN@ CLP4 CONN@ CLP3 CONN@ CLP6 CONN@ CLP5 CONN@ CLP8 CONN@ CLP7 CONN@
1 1 1 1 1 1 1 1
LED Circuit Control Table P1 P1 P1 P1 P1 P1 P1 P1
Fiducial Mark EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
@ FD1
1
SYS_LED_MASK# LID_CL#
For JAE JSIM1 boss hole CLP16 CONN@ CLP9 CONN@ CLP11 CONN@ CLP10 CONN@ CLP13 CONN@ CLP12 CONN@ CLP15 CONN@ CLP14 CONN@
FIDUCIAL MARK~D 1 1 1 1 1 1 1 1
P1 P1 P1 P1 P1 P1 P1 P1
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1 EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1 CLP24 CONN@ CLP17 CONN@ CLP19 CONN@ CLP18 CONN@ CLP21 CONN@ CLP20 CONN@ CLP23 CONN@ CLP22 CONN@
@ FD3 1 1 1 1 1 1 1 1
1 P1 P1 P1 P1 P1 P1 P1 P1
FIDUCIAL MARK~D EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
@ FD4
CPU NGFF EDP screw hole
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H11 @ H12 @ H13 @ H14 @ H16 @ H17 @ H18 @ H19 @ H20 @ ST1 @ ST2 CLP32 CONN@ CLP25 CONN@ CLP27 CONN@ CLP26 CONN@ CLP29 CONN@ CLP28 CONN@ CLP31 CONN@ CLP30 CONN@
H_3P8 H_3P8 H_3P8 H_3P8 H_1P1N H_1P1N H_7P0N H_7P0N H_2P3 H_2P5 H_2P3 H_2P5 H_2P3 H_2P3 H_2P5N H_2P3 H_2P3 H_2P3 CLIP_C5P5 CLIP_C5P5 1 1 1 1 1 1 1 1
FIDUCIAL MARK~D P1 P1 P1 P1 P1 P1 P1 P1
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P

1
CLP33 CONN@ CLP34 CONN@ CLP35 CONN@ CLP36 CONN@ CLP37 CONN@ CLP38 CONN@
1 1 1 1 1 1
@ H24 @ H26 @ H27 @ H28 @ H29 @ H34 P1 P1 P1 P1 P1 P1
A H_5P6 H_2P3 H_5P6 H_1P3N H_1P3X1P8N H_3P2 A
EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P EMIST_SUL-12A2M_1P
@ H30 @ H31 @ H32 @ H33
H_0P8N H_0P8N H_0P9N H_1P1N
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
5 4 3 2 1
5 4 3 2 1
+3.3V_WLAN/+3.3V_ALW_PCH source +1.8V_RUN source

2A
PJP36
1 2 +3.3V_WLAN
+3.3V_ALW
PAD-OPEN1x2m PJP42 0.013A
UZ2 1 2 +1.8V_RUN
1 14 +3.3V_WLAN_UZ2 1 2 +1.8V_PRIM UZ8
2 VIN1 VOUT1 13 CZ122 0.1U_0201_10V6K PAD-OPEN1x1m
VIN1 VOUT1 1 7
WLAN_PWR_EN 3 12 1 2 2 VIN VOUT 8 +1.8V_RUN_UZ8 1 2
ON1 CT1 CZ109 470P_0402_50V7K VIN VOUT CZ120 0.1U_0201_10V6K
D RUN_ON_1.8V D
+5V_ALW
4 11 1 2 3 6 1 2
VBIAS GND <17,36,37,44,51> RUN_ON @ RZ345 ON CT
0_0402_5% CZ121 470P_0402_50V7K
@ RZ65 1 2 0_0402_5% 5 10 1 2
<36> PCH_ALW_ON @ RZ64 1 2 0_0402_5% ON2 CT2 4
CZ113 470P_0402_50V7K +5V_ALW
<11,17,50,51,52> PCH_PRIM_EN +3.3V_ALW_PCH_UZ3 VBIAS
6 9 1 2 5
7 VIN2 VOUT2 8 CZ112 0.1U_0201_10V6K GND 9
VIN2 VOUT2 GND
1
15 @ CZ197
GPAD AOZ1336_DFN8_2X2
0.63A 470P_0402_50V7K
2
EM5209VF_SON14_2X3 PJP38
1 2 +3.3V_ALW_PCH
PAD-OPEN1x1m
+3.3V_ALW
1
RZ518
10K_0402_5%
2
1 2
<36> SLP_WLAN#_GATE
@ RZ71 0_0402_5%
2
@ DZ9
G
QZ15
1 3 SLP_WLAN#_M 3
<11,36> SIO_SLP_WLAN#
D
S TR BSS138W 1N SOT-323-3 1 WLAN_PWR_EN
1
2
<36> AUX_EN_WOWL
RZ38
C C
100K_0402_5%
BAT54CW_SOT323-3
2
1 2
@ RZ70 0_0402_5%
EC request to reserve OR gate for WLAN power enable
+3.3V_RUN source +3.3V_ALW

UZ3
1 14
2 VIN1 VOUT1 13
VIN1 VOUT1
3 12
ON1 CT1
4 11 +5V_RUN
+5V_ALW VBIAS GND
RUN_ON 5 10 1 2
ON2 CT2
1
CZ114 1000P_0402_50V7K @
6 9 RZ370
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2 100_0603_5%
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
2
GPAD
EM5209VF_SON14_2X3 PJP39
1 2
+5V_RUN_CHG
+3.3V_RUN
B B
PAD-OPEN1x3m
3.435A
1
D
2 @
+5V_RUN/+3.3V_WWAN source <36> RUN_ON#

G
S
QZ4
L2N7002WT1G_SC-70-3
PJP40 2A Reserve for S3 no power issue (+5V_RUN discharge circuit)

1 2 +5V_RUN
+5V_ALW
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2 +3.3V_WWAN_UZ4
2 VIN1 VOUT1 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2 1
<17,36,37,44,51> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K
4 11 RF@ CZ124
VBIAS GND 2200P_0402_50V7K
3.3V_WWAN_EN 5 10 1 2 2
<36> 3.3V_WWAN_EN ON2 CT2 CZ118 470P_0402_50V7K
6 9 +3.3V_WWAN_UZ4
+3.3V_ALW VIN2 VOUT2
A 7 8 1 2 A
1 2 3.3V_WWAN_EN VIN2 VOUT2 CZ119 0.1U_0201_10V6K
RZ40 100K_0402_5% 15 RF Request
GPAD PJP41
EM5209VF_SON14_2X3 1 2 +3.3V_WWAN
PAD-OPEN1x3m 2.5A DELL CONFIDENTIAL/PROPRIETARY

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power control
5 4 3 2 1
5 4 3 2 1
Only for Kirkwood

Accelerometer use on 360o hinge designs
+VDD_IO
double check with BIOS for SMB address
1
+3.3V_RUN +VDD_IO
D @ RZ121 D
0_0402_5%
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
2
ACC1_SA0
1
CZ168
CZ169
CZ170
@ RZ122
0_0402_5% LGA1
2
LNG2DM
2
10 5 GPP_A GROUP is +1.8V power rail
9 VDD_IO RES
VDD 12 ISH_GP1
ACC1_SA0 3 INT 1 11
ISH_I2C0_SDA 4 SDO/SA0 INT 2
ISH_I2C0_SCL 1 SDA/SDI/SDO 6
SCL/SPC GND 7 HIGH ACTIVE
2 GND 8 LNG2DMTR Interrupt active value.Default value:0
CS GND (0:active high; 1:active low)
LNG2DMTR_LGA12_2X2
+3.3V_WWAN
C SAR Sensor Located on motherboard

Located on MB C
2
6 1 +3.3V_WWAN
1 2
<36,37,38> USH_EXPANDER_SMBDAT +3.3V_RUN +VDD_IO
QZ13A @ RZ509 0_0402_5%
5
DMN65D8LDW-7_SOT363-6 1 2
+1.8V_RUN
2
2.2K_0402_5%
@ RZ510 0_0402_5%
2
2.2K_0402_5%
RZ350
3 4
+3.3V_WWAN
RZ351
<36,37,38> USH_EXPANDER_SMBCLK
QZ13B
+3.3V_RUN DMN65D8LDW-7_SOT363-6
1 Detect closed in tablet position Detect clamshell closed
1
I2C from EC
JSAR1
Reserve CPU path
2
1 +3.3V_ALW +3.3V_ALW
1 6 SAR_I2C0_SDA 2 1
<9> ISH_I2C0_SDA SAR_I2C0_SCL 2
3 5 UZ28 UZ1
@ QZ10A 4 3 G1 6 2 2
4 G2 VCC VCC
5
0.1U_0201_10V6K
0.1U_0201_10V6K
DMN65D8LDW-7_SOT363-6 1 1
ACES_50208-0040N-001 1 1
GND GND
@ CZ188
@ CZ167
4 3 CONN@
<9> ISH_I2C0_SCL 3 3
@ QZ10B 2 <36> LID_CL_SIO_TAB# VOUT 2 <37> LID_CL# VOUT
DMN65D8LDW-7_SOT363-6 TCS40DLR_SOT23F3 TCS40DLR_SOT23F3
ACES_50208-0040N-001 LINK DONE

RF Request Place CZ1 near UZ1.
+3.3V_WWAN
SAR_I2C0_SDA SAR_I2C0_SCL
20160315
B Hall sensor: SA00009CB00 B
Hall sensor: SA00009CB00
CZ164 1 CZ165 1 CZ166 1
@RF@ @RF@ @RF@
+3.3V_ALW +1.8V_RUN
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
2 2 2 Level Shift
ISH_GP0_D 1 2
RZ501 10K_0402_5%
ISH_GP0 1 2 ISH_GP0_D ISH_GP1_D 1 2
Located near the WWAN antenna 3.3V_ALS_EN# 2 1 ISH_GP0_D <9> RZ502 10K_0402_5%
10K_0402_5% RE521 DZ100 ISH_GP2_D 1 2
RB751S-40 SOD-523 RZ503 10K_0402_5%
ISH_GP1 1 2 ISH_GP1_D ISH_GP3_D 1 2
+3.3V_RUN ISH_GP1_D <9> @ RZ504 10K_0402_5%
JSEN2 DZ101 LID_CL#_NB_D 1 2
1 RB751S-40 SOD-523 RZ512 10K_0402_5%
2 1 ISH_GP2 1 2 ISH_GP2_D LID_CL#_TAB_D 1 2
ISH_I2C0_SCL @ RZ137 1 2 0_0402_5% ACC1_I2C0_SCL 3 2 ISH_GP2_D <9> RZ513 10K_0402_5%
ISH_I2C1_SCL @ RZ138 1 2 0_0402_5% ALS_I2C0_SCL 4 3 DZ102
<9,36> ISH_I2C1_SCL ISH_I2C0_SDA @ RZ140 1 2 0_0402_5% ACC1_I2C0_SDA 5 4 +3.3V_RUN
RB751S-40 SOD-523
ISH_I2C1_SDA @ RZ141 1 2 0_0402_5% ALS_I2C0_SDA 6 5 ISH_GP3 1 2 ISH_GP3_D
<9,36> ISH_I2C1_SDA ISH_GP0 ACC1_INT1 6 ISH_GP3_D <9> ISH_GP0
@ RZ143 1 2 0_0402_5% 7 1 2
3.3V_ALS_EN# 8 7 @ DZ103 @ RZ505 10K_0402_5%
ISH_GP3 1 2 ALS_INT# 9 8 RB751S-40 SOD-523 ISH_GP1 1 2
@ RZ145 0_0402_5% 10 9 LID_CL# 1 2 LID_CL#_NB_D @ RZ506 10K_0402_5%
+5V_ALW 10 LID_CL#_NB_D <9> ISH_GP2
11 1 2
<9> I2C2_SDA_ALS 12 11 DZ104 @ RZ507 10K_0402_5%
<9> I2C2_SCL_ALS 13 12 ISH_GP3 1 2
RB751S-40 SOD-523
14 GND LID_CL_SIO_TAB#1 2 LID_CL#_TAB_D @ RZ508 10K_0402_5%
ALS I2C reserve EC solution +3.3V_RUN GND LID_CL#_TAB_D <9> LID_CL# 1 2
ACES_50208-01201-P01 DZ105 @ RZ514 10K_0402_5%
A RB751S-40 SOD-523 LID_CL_SIO_TAB#1 2 A
CONN@
@ RZ515 10K_0402_5%
Device Side CPU side
2
USH_EXPANDER_SMBCLK 6 1 ALS_I2C0_SCL
LINK ACES_50208-01001-P03 Done DELL CONFIDENTIAL/PROPRIETARY
@ QZ14A 20160321
5
USH_EXPANDER_SMBDAT 3 4 ALS_I2C0_SDA Title
@ QZ14B BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SENSOR
DMN65D8LDW-7_SOT363-6 Size Document Number R ev
1.0
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P0 PCH SIO_PWRBTN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#
7
VCCCLK1~6 SIO_SLP_SUS#
VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS# 5
SIO_SLP_S5#
+1.0V_MPHYGT VCCAMPHYPLL_1P0 SLP_S5#
VCCAPLLEBB
SIO_SLP_S4#
9
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
3 VCCDSW_3P3
SLP_A#
SIO_SLP_A#
CPU
+3.3V_SPI 5 +3.3V_ALW_PCH SIO_SLP_LAN#
11
+VCC_CORE VCCHDA SLP_LAN#
D VCCST_PWRGD VCCSPI D
12 VCCST_PWRGD VCC VCCPRIM_3P3

VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
VCCIO +1.8V_PRIM SYS_PWROK
H_CPUPWRGD 6 16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.2V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.6V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 6 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.0V_VCCST 11 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL 17 PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
4 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD AP2821K EDP_VDDEN
+PWR_SRC
+1.0V_PRIM_CORE SIO_SLP_SUS# +3.3V_ALW
6 TLV62130
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
6 +1.8V_PRIM
TLV62130
+5V_RUN
C 3.3V_TS_EN C
+5V_TSP LP2301ALT1G GPP_B21
+PWR_SRC
6
+3.3V_RUN
+1.0V_PRIM SYX198
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
Power Button
EC 5105 1BAT 2AC

11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5105 SYX198
+5V_ALW
+5V_RUN +5V_HDD 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SYX198
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD +3.3V_ALW
B PCH_RSMRST# 5 B
+PWR_SRC 7 SIO_SLP_SUS#
+3.3V_ALW
+3.3V_ALW @SIO_SLP_WLAN# TLV62130 +1.0VS_VCCIO PCH_DPWROK

4 EM5209VF
@PCH_ALW_ON +3.3V_ALW_PCH 5
RESET_OUT#
11 +3.3V_WLAN EM5209VF AUX_EN_WOWL 16
Pop option
+3.3V_SPI
5 SIO_SLP_SUS#
10 SIO_SLP_S4#
SIO_SLP_S5#
9
SIO_SLP_LAN#
MCP 23008
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95857 SIO_SLP_S4#
+VCC_GT +1.2V_MEM VDDQ
RT8207MZ VTT
DDR
+0.6V_DDR_VTT
PCH_PWROK
12
0.6V_DDR_VTT_ON
A
SM BUS 14 A

Power Sequence
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Re v
1.0
LA-F292P
Date : Tuesday, November 14, 2017 Sheet 46 of 60
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
EMC@ PC2
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
@ JRTC1
1
+COINCELL 2 1
2
D D
3
2
4 GND
+RTC_CELL GND
1
PD1 PD2
@ESD@ @ESD@ ACES_50271-0020N-001
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C
PBATT1
1 2 +PBATT
PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT (36,56)
6 6 3
PBAT_CHARGER_SMBCLK (36,56) PBAT_PRES# (36,56)
1
6 7 5 4
EMC@ PC1
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND 13
GND 14
GND
DEREN_40-42507-01001RHF GND
GND
C C
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D BATT/RTC
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-F292P
5 4 3 2 1
A B C D E
@ PR119
0_0402_5%
PGOOD_3V 1 2
PGOOD_5V ALW_PWRGD_3V_5V (11,42)
1 2
1 @ PR120 1
0_0402_5%
PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V 1 2
@ PR100 +PWR_SRC
PJP100 0_0603_5% PC102 3VALWP
1
3V_VIN BST_3V
TDC 5.6 A
499K_0402_1%
1 2 1 2 1 2
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K Peak Current 6.7 A
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
OCP Current 11.5 A
1
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
82P_0402_50V8J
0.1U_0402_25V6
PU100
2
1
1
RF@ PC100
RF@ PC103
RF@ PC131
PC105
PC104
BS
IN
IN
IN
IN
1
1
@EMC@ PC133
@EMC@ PC134
@EMC@ PC135
@EMC@ PC136
LX_3V 6 20 PL100
2
LX LX 2.2UH_PCMB062D-2R2MS_7A_20%
2
2 7 19 LX_3V 1 2
GND LX +3.3V_ALWP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMC@ PR106
8 SY8288BRAC_QFN20_3X3 18 @ PR104
GND GND
4.7_1206_5%
0_0402_5%
9 17 1 2
RF demand PG LDO +3.3V_ALW2
1
PC106
PC107
PC108
PC109
PC110
PC129
PC161
PC162
10 16 @ PR105
NC NC 0_0402_5%
OUT
2
EN2
EN1
21 1 2
NC
+3.3V_RTC_LDO @ @
FF
GND
1 3V_SN 2
PR107
11
12
13
14
15
680P_0603_50V7K
100K_0402_5%
@EMC@ PC112
2 1 2 3.3V LDO 150mA~300mA 2
+3.3V_ALW
1
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V
4.7U_0603_6.3V6K
2
PGOOD_3V
PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118
+PWR_SRC PJP103
@ PR111 +5V_ALWP 1 2 +5V_ALW
PJP101 0_0603_5% PC114 1 2
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0603_25V7K

1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
10U_0603_16VAK
10U_0603_16VAK
82P_0402_50V8J
0.1U_0402_25V6
1
RF@ PC115
RF@ PC116
RF@ PC132
PU102
1
1
@EMC@ PC137
@EMC@ PC138
PC117
PC118
@EMC@ PC139
@EMC@ PC140
BS
IN
IN
IN
IN
LX_5V 6 20 PL101
2
LX LX 1UH +-20% PCMB062D-1R0MS 9A

7 19 LX_5V 1 2
3 GND LX +5V_ALWP 3
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
8 SYV828CRAC QFN 20P PWM 18
GND GND
1
PR112
680P_0603_50V7K 4.7_1206_5%
PC119
1
@EMC@
PC120
PC121
PC122
PC123
PC124
PC130
PC150
PC151
PC163
PC164
9 17 1 2
RF demand PG VCC
10 16
2
NC NC 4.7U_0603_6.3V6K
1 5V_SN
@ @
OUT
LDO
2
EN2
EN1
21
FF
GND
11
12
13
14
15
PC125
PR113
@EMC@
100K_0402_5%
2
1 2
+3.3V_ALW +5V_ALW2
ENLDO_3V5V
3V5V_EN
4.7U_0603_6.3V6K
1
PGOOD_5V
PC126
5V LDO 150mA~300mA
@ PR114
0_0402_5%
5VALWP
2
1 2
(36) ALWON
TDC 7.8 A
Peak Current 9 A
3V5V_EN
OCP Current 11.5 A
1M_0402_1%
4.7U_0603_6.3V6K
1
1
PR116
PC128
PC127 PR117
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2
4 4
EN1 and EN2 dont't floating
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F292P
A B C D E
5 4 3 2 1
D D
+PWR_SRC
PJP202
1 2 +1.2V_DDR_B+
PU200
82P 50V J NPO 0402
0.1U 25V K X5R 0402
PAD-OPEN 1x2m~D RF@ RF@

10U_0603_25V6M
10U_0603_25V6M
1
+3.3V_ALW 10 19 PR202 PC204

IN OT
PC202
PC203
4.7_1206_5% 680P_0603_50V7K
PC200
PC201
13 18 @ PR203 PC205 1 2 1 2
2
BYP PG
1U_0402_6.3V6K
14 12
0_0603_5%
1 2
0.1U_0603_16V7K
1 2
+1.2V_DDRP
VCC BS
1
PC206
C PL201 C
1
LX_DDR
2.2U_0402_6.3V6M
4 11 1 2
VTTGND LX
PC207
1UH_PCMB062D-1R0MS_9A_20%
2
330P_0402_50V7K
RF@ RF@ 2 9 16
PGND FB
1
102K_0402_1%
RF demand
1
+1.2V_DDRP
PC208
PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2200P_0402_50V7K
100P_0402_50V8J
22U_0603_6.3V6M
R1
EMC@ PC216
EMC@ PC217
7 1 2
2
VLDOIN
1
PC210
PC211
PC212
PC213
PC214
PC223
2
2
@ ILMT_DDR 17 6
PR205 ILMT VTT +0.6VSP
2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A
1
100K_0402_1%
2 3
1
when this pin is pull S3 VTTREF
1U_0402_10V6K
22U_0603_6.3V6M
PR206
R2
1
ILMT_DDR
PC218
low, floating or pull
PC219
high SY8210AQVC_QFN19_4X3
S5_1.2V
+1.2V_DDR OCP set 8A
2
2
@PR207
0_0402_5% Layout for Pin4,9,15
VTTGND , PGND seperate GND via
1
PGNE Cin_cap shape GND via

@ PR208
SGND alone GND
0_0402_5%
1 2
B (11,17,36,52) SIO_SLP_S4# B
0.1U_0402_10V7K
1M_0402_5%
1
1
@ PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2
@ PJP200 @ PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
@ PR210 1 2 1 2
0_0402_5%
1 2
(7) 0.6V_DDR_VTT_ON
1M_0402_5%
0.1U_0402_10V7K
1
+1.2V_DDR 0.6Volt +/- 5%

PR212
@ PC222
TDC 6.4A TDC 0.007A

2
Mode S3 S5 VOUT VTT Peak Current 9.7A Peak Current 0.01A

Normal H H on on
2
Stadby L H on off OCP Current 11.6A OCP Current 2A (fix)

Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
PJP302
+1VALWP 1
1 2
2 +1.0V_PRIM
JUMP_43X118
@EMC@ PR303 @EMC@ PC302

4.7_1206_5% 680P_0603_50V7K
2 SNB_+1VALW P 1
+PWR_SRC PJP301
+1VALW P_B+
PU301
1 2
1 2 2 9 @ PR304 PC304
IN PG 0_0402_5% 0.1U_0201_10V6K
10U_0603_25V6M
10U_0603_25V6M
PAD-OPEN 1x2m~D 3 1 BST_+1VALW P 1 2 BST_+1VALW P_C 1 2 PL301
100P_0402_50V8J
100P_0402_50V8J
IN BS
1
1
1UH_PCMB051H-1R0MS_8A_20%
@RF@ PC301
@RF@ PC303
PC305
PC306
C 4
IN LX
6 SW _+1VALW P 1 2 +1VALWP C
2
2
5 19
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
330P_0402_50V7K
1
1
7 20
GND LX
PC307
PC308
PC309
PC310
PC311
21.5K_0402_1%
1
8 14 FB_+1VALW P
2
GND FB
PR306
@ PR312 18 17
2.2U_0402_6.3V6M
GND VCC
1
0_0402_5%
1K_0402_5%
1
1 2 EN_+1VALW P 11 10
PC313
PR308
(11,17,44,51,52) PCH_PRIM_EN
2
EN NC
1
13 12
2
PR302 ILMT NC
2
1M_0402_1% 15 16
+3.3V_ALW BYP NC
21
1U_0402_6.3V6K
2
PAD
1
1
SY8286RAC_QFN20_3X3 PR311
PC312
31.6K_0402_1%
2
+3.3V_ALW
2
1
@ PR307
0_0402_5%
+1.0V_PRIM
B
TDC 3.5A B
2
ILMT_+1VALW P
Peak Current 6.5 A
1
OCP Current 9 A Fix by IC

@ PR310 TYP MAX
0_0402_5% Choke DCR 11.0mohm , 12.0mohm
2
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A A
Title
+1VALWP

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
1
@ PR425
0_0402_5% PR404 @ 0 X X 0(LPM)
(11,17,38,51) SIO_SLP_S0# 1 2 0_0402_5%
PJP401
TPS62134C 1 0 0 0.80
2
JUMP_43X79 1 0 1 0.95
@ PR402 1 2
0_0402_5% +1VS_VCCIOP 1 2 +1.0VS_VCCIO 1 1 0 1.00
1 2
(17,36,37,44) RUN_ON
1 1 1 1.05
EN_1VS_VCCIO
0.1U_0402_25V6
1
1
@ PC402
PR403
D 1M_0402_1% D
2
@ PL407
3A_Z120_40M_0603_2P
2
1 2
+5V_ALW
13
14
15
16
17
PU401
+1.0VS_VCCIO
EN
PGND
PGND
TP
LPM
PL405
3A_Z120_40M_0603_2P
VIN_1VS_VCCIO
TDC 1.9 A
+3.3V_ALW 1 2 12
PVIN VOS
1
+1VS_VCCIOP Peak Current 2.7 A
PL402 OCP Current 3.3 A
10U_0603_10V6M
10U_0603_10V6M
1UH_1277AS-H-1R0N-P2_3.3A_30%
TYP MAX
1
LX_1VS_VCCIO
+3.3V_ALW 11 2 1 2
+1VS_VCCIOP
PC403
PC404
PVIN SW
Choke DCR 48.0mohm
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
TPS62134CRGT_QFN16_3X3
1
10 3
PC406
PC407
PC422
AVIN SW
2
2200P_0402_50V7K
SNUB_1VS_VCCIO
0.1U_0402_25V6
1
1
VID0_VCCIO 9 4
PC408
@EMC@ PC409
VID0 PG @EMC@ PR405
1
AGND
@ 4.7_0603_5%
VID1
FBS
PR413 PR414 @EMC@
SS
2
10K_0402_1% 10K_0402_1%
2
5
VID0_VCCIO
1
@EMC@ PC401 +1VS_VCCIOP
SS_1VS_VCCIO
VID1_VCCIO
1
VID1_VCCIO 470P_0402_50V7K
2
PR421
1
0_0402_5%
@
PR415 PR416
470P_0402_50V7K
2
10K_0402_1% 10K_0402_1% @ PR422
1
0_0402_5%
0_0402_5%
C C
2
1 2
@ PR427
PC410
VCCIO_SENSE (17)
2
@ PR412
0_0402_5%
2
1 2
VSSIO_SENSE (17)
"R" for SILERGY

+3.3V_ALW
1
@ PR426 PR410 @
0_0402_5% 0_0402_5%
1 2
(11,17,38,51) SIO_SLP_S0#
2
PJP402
@ PR406 JUMP_43X79
EN_1.0V_PRIM_COREP
0_0402_5% 1 2
(11,17,44,50,52) PCH_PRIM_EN 1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
0.1U_0402_25V6
1
1
@ PC411
PR407
1M_0402_1%
2
@ PL408
3A_Z120_40M_0603_2P
2
1 2
+5V_ALW
13
14
15
16
17
PU402
B B
EN
PGND
PGND
TP
LPM
PL406
3A_Z120_40M_0603_2P
VIN_1V_PRIM
+3.3V_ALW 1 2 12
PVIN VOS
1
+1.0V_PRIM_COREP
PL404
10U_0603_10V6M
10U_0603_10V6M
1UH_1277AS-H-1R0N-P2_3.3A_30%
1
LX_1V_PRIM
11 2 1 2
+1.0V_PRIM_COREP
PC412
PC413
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
+3.3V_ALW TPS62134DRGT_QFN16_3X3
1
10 3
PC415
PC424
PC427
AVIN SW
Rup
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
2
2200P_0402_50V7K
82P_0402_50V8J
0.1U_0402_25V6
1
9 4
PC421
PC417
0 X X 0.7(LPM)
PC418
VID0 PG @EMC@ PR409

1SNUB_1V_PRIM
TPS62134D 1 0 0 0.85
2
AGND
4.7_0603_5%
VID0_PRIM_CORE
VID1
FBS
SS
1 0 1 0.90
2
1
RF@ RF@ 1 1 0 0.95

8
PR417 PR418 RF@

10K_0402_1% 10K_0402_1% @EMC@ PC419 1 1 1 1.00
RF demand
2
VID0_PRIM_CORE 470P_0402_50V7K
VID1_PRIM_CORE
@ PR408
VID1_PRIM_CORE 0_0402_5%
SS_1V_PRIM
1 2
(18) CORE_VID0
1
@ PR411 @ PR423
+1.0V_PRIM_CORE
@ PR419 @ PR420 0_0402_5% 0_0402_5% TDC 1.8 A
10K_0402_1% 10K_0402_1% 1 2 1 2
(18) CORE_VID1 Peak Current 2.6 A
2
OCP Current 3.1 A

470P_0402_50V7K
1M_0402_1%
TYP MAX
1
1
PR428
A A
@ PR424 Choke DCR 48.0mohm
PC420
100K_0402_1%
2
@
2
"R" for SILERGY
Title
+1VS_VCCIOP/+1.0V_PRIM_COREP
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F292P
5 4 3 2 1
5 4 3 2 1
@ PL502
3A_Z120_40M_0603_2P
1 2 VIN_1.8VALW
PJP501
1 2
+3.3V_ALW
22U_0603_6.3V6M
1
PAD-OPEN1x1m
PC502
2
D D
PJP502
1 2
+1.8VALWP +1.8V_PRIM
PAD-OPEN1x1m
Imax= 2A, Ipeak= 3A

FB=0.6V
PR517
PU501
100K_0402_5% PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW 4 3 LX_1.8VALW 1 2
IN LX +1.8VALWP
1
5 2
(36) 1.8V_PRIM_PWRGD PG GND @EMC@ PR502
1SNUB_1.8VALW
68P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
6 1
FB EN
1
4.7_0603_5%
PC503
PC501
PC504
PR501
2
@ PR504 RT8097ALGE_SOT23-6
2
0_0402_5% 20K_0402_1%
1 2 EN_1.8VALW
(11,17,44,50,51) PCH_PRIM_EN
2
@EMC@ PC506
Rup
1
680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1% 0.1U_0402_16V7K
2
FB_1.8VALW
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 2 A
C
Note: Peak Current 3 A C
2
When design Vin=5V, please stuff snubber OCP Current 3.5A
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
B B
+1.8V_MEM
TDC 0.5 A
Peak Current 0.7 A
OCP Current 0.8 A
PU503
PJP505
AP7361C-FGE-7-01_U-DFN3030-8_3X3 PJP506
1 2 +1.8V_VIN 9
+3.3V_ALW GND 1 1.8V_out 1 2
+1.8V_MEM
1
8 OUT
PAD-OPEN1x1m IN
1
PC514 2
NC PAD-OPEN1x1m
4.7U_0603_6.3V6K 7
2
NC
1
3 PR515
22U_0603_6.3V6M
@ PR513 6 ADJ/NC 12.7K_0402_1% PC515
1
0_0402_5% NC 4 0.01UF_0402_25V7K
PC516
2
1 2 EN_1.8V 5 GND
(11,17,36,49) SIO_SLP_S4# EN
2
1
@ PC513
PR514 PR516
2
1M_0402_1% .1U_0402_16V7K 10.2K_0402_1%

2
A A
Title
+1.8VALWP/1.8V_MEN
1.0
LA-F292P
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST
@ PR602
0.1U_0402_25V6
0_0402_5%
1
45.3_0402_1%
100_0402_1%
75_0402_1%
PC602
1 2
+5V_ALW
PR605
PR601
PR604
Local sense put on HW site
2
PJP603
0.22U_0603_25V7K
@ 1 2 CPU_B+
1U_0603_10V6K
1 2
D 1 2 @ PR603 VCCSA_B+ CPU_B+ D
(15) VIDSCLK
1
49.9_0402_1% PR618 0_0402_5%
PC603
PC604
PAD-OPEN1x1m
(15) VIDALERT_N 1 2
0_0402_5% @ PR625
2
(15) VIDSOUT 1 2
10_0402_1% PR626
PR678 VCCSA_B+
VIDALERT_N_B
(12,36,56) PROCHOT#
VIDSOUT_B
VIDSCLK_B
100_0402_1%
1 2 1 2
1 2
PC605 47P_0402_50V8J
10U_0603_25V6M
10U_0603_25V6M
470K_0402_5%_B25/50 4700K PR608
PR610 88.7K_0402_1%
PH601
10K_0402_1% PR612 1 2
1
PC612
PC608
1 2 1 2 @ PR613 1.91K_0402_1%
86.6K_0402_1% 1 2 PR611
1 2 1 2 +3.3V_RUN 1.87K_0402_1%
2
PR631 PC613 (11) PCH_PWROK 1 2
27.4K_0402_1% 330P_0402_50V7K @ PR614 0_0402_5%
1 2 1 2
(37) IMVP_VR_ON
PC614 @ PR617 @ PR616 0_0402_5%
2200P_0402_50V7K 4.3K_0402_1%
1 2 1 2
40
39
38
37
36
35
34
33
32
31
PU602 SA_UGATE
@ PC616 PR619 2.2_0603_5%
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
33P_0402_50V8J @ PR620 1 2
1 2 @ PC617 @ PR621 0_0402_5%
1200P_0402_50V7K 316_0402_1% 1 2 1 30 PWM_VSA PU614
(36,56) I_SYS PSYS PWM_C
1
1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2378_DFN8_2X2 PQ614
(15) VCCSENSE IMON_B FCCM_C
@ PR622 3 28 PE642DT_DFN3X3
D1
D1
D1
G1
@ PC618 1.5K_0402_1% 4 NTC_B ISUMN_C 27 PC611 1 8 PL614
COMP_B ISUMP_C UGATE PHASE
0.082U_0402_16V7K
1 2 1 2 5 26 0.22U_0603_16V7K 0.47UH MMD-05AHNR47MEX2L 10.5A

FB_B RTN_C FB_VSA 9 SA_SW
@ PC620
6 25 1 2 2 7 10 4 1
RTN_B FB_C BOOT FCCM D1 D2/S1
+VCC_SA
1
330P_0402_50V7K 7 24 COMP_VSA
ISUMP_B COMP_C IMON_VSA PWM_SA
PR627 @EMC@
PC621 PR623 8 23 3 6 3 2
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C
G2
S2
S2
S2
2
ISEN1_B PWM_A PWM_GT (54)
1
SA_LGATE
4.7_1206_5%
0_0402_5%
1 2 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_GT (54) GND LGATE
1
PR606
TP
ISUMN_A
ISUMP_A
PR624
PWM1_B
PWM2_B
COMP_A
8
FCCM_B
IMON_A
0.01UF_0402_25V7K 41
NTC_A
RTN_A
AGND 3.65K_0603_1%
FB_A
(15) VSSSENSE
1
@
2
1
@ PR679
ISUMP_VSA 2
0_0402_5%
PWM_VSA
+5V_ALW
1SA_SNUB
11
12
13
14
15
16
17
18
19
20
ISUMN_VSA
ISL95857AHRTZ-T TQFN 40P PWM
680P_0603_50V7K
1U_0402_10V6K
(54) ISUMP_IA
IMON_GT
2
FB_GT
NTC_GT
COMP_GT
(54) FCCM_IA
4.99K_0402_1%
PC685
@EMC@ PC622
FCCM_VSA
(54) PWM1_IA
2
2
(54) PWM2_IA
PR628
@ PR658 PC625
20M_0402_5% 330P_0402_50V7K
2
0.033U_0402_16V7K
0.01U_0402_25V7K
1 2
PR629
1
@ 86.6K_0402_1%
1
2.49K_0402_1%
PC624
@ PC626
1 2
33P 50V J NPO 0402

10K_0402_5%_B25/50 4250K
PR630
PH603
1
1
2200P_0402_50V7K
4700P_0402_25V7K
11K_0402_1%
PR632 PC627 470K_0402_5%_B25/50 4700K

2
2
1
2200P_0402_50V7K
PR633
PC628
@ 1K_0402_1% 1 2 1 2 @ PR636
ISUMP_VSA
PH602
1 2 1 2 665_0402_1%
2
357_0402_1%
PR647 PR635 1 2
1
@ PR638 27.4K_0402_1% 10K_0402_1%
2.61K_0402_1%
2
1
PC630
PR640
360_0402_1% 1 2
2
PC631
1 2 PC629 PR639
PR642
(54) ISUMN_IA 2200P_0402_50V7K 3.09K_0402_1% 1 2 1 2
10KB_0402_5%
@U42 PC635 1 2 1 2
2
0.022U_0402_16V7K PC632 PR641
0.033U 25V K X7R 0402
2
2
ISEN1_IA
1K_0402_1%
11K_0402_1%
1 2 PC636 1000P_0402_50V7K 1K_0402_1%
33P_0402_50V8J
4700P 50V K X7R 0402
PR643
1
1
PR644
PC633
1 2
PC637
@U42 PC638
1
B 0.022U_0402_16V7K PC639 PR645 PR646 PC640 B
1
1 2 ISEN2_IA 1500P_0402_50V7K 316_0402_1% 1 2 1 2
330P_0402_50V7K
@U22PR634 1 2 1 2
PH604
0_0402_5% 316_0402_1% 2200P_0402_50V7K
1 2
2
.1U_0402_16V7K
1 2 PR649
+5V_ALW
1
1
113K_0402_1%
1 2 PR648 1 2
1
ISUMN_VSA
PC641
1.91K_0402_1% @ PC642
(54) ISEN1_IA
680P_0402_50V7K 2K_0402_1%
@U22 PR615
PC643
PR651
0.033U_0402_16V7K 1.62K_0402_1% PC644
2
2K_0402_1%
0_0402_5% 1 2 .1U_0402_16V7K
(54) ISEN2_IA
2
.1U_0402_16V7K
PR652
1 2
2
1
@
PR650
PC645
2
1 2
680P_0402_50V7K
@ PC646 @
0.01U_0402_25V7K
2
VSA_SEN- (17)
PC647
PC601
1 2
2
1
PC649
@ 0.01UF_0402_25V7K
0.082U_0402_16V7K
1 2
IA OCP : 77A by PR638 setting 453 (for U42) (16) VCC_GT_SENSE
PR656
IA OCP : 38A by PR638 setting 365 (for U22) 11K_0402_1%
2
PC650
1 2
GT OCP : 37A by PR640 setting 357 @ PC652
SA OCP : 10A by PR636 setting 665 PR657
1
@ PC651 @ 330P_0402_50V7K
PH605
1 2 4.42K_0402_1% 1 2
0.082U_0402_16V7K
1 2 1 2
@ PC653
330P_0402_50V7K
PR608 setting 88.7K for
1
10K_0402_5%_B25/50 4250K
IA IccMax : 64A @ PR653 VSA_SEN+ (17)
2 1
GT IccMax : 31A ISUMN_GT (54)
2
PC654 20M_0402_5%
A A
SA IccMax : 6A 1 2
ISUMP_GT (54)
0.01UF_0402_25V7K
(16) VSS_GT_SENSE
PR611 setting 1.87K for frequency 450KHz DELL CONFIDENTIAL/PROPRIETARY
Local sense put on HW site
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
AR U42
+PWR_SRC
+VCC_CORE @U42 +VCC_GT_+VCC_CORE PC626 @U42AR PR613 @U42AR PR621 @U42AR PC617 @U42AR PC624 @U42AR PC642 @U42AR PR651 @U42AR
PJP601 PR682 SOLDER_PREFORMS_0603
1 2 1 2
1 2
CPU_B+ PAD-OPEN 4x4m +VCC_GT @U22
PR683 SOLDER_PREFORMS_0603
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
@EMC@ PL602 1 2 0.1U_0402_25V6 93.1K_0402_1% 1K_0402_1% 220P_0402_50V7K 0.01UF_0402_25V7K 0.022U_0402_16V7K 113K_0402_1%
1 2
1
1 2
@EMC@ PC691
@EMC@ PC692
RF@
RF@
RF@
RF@
RF@
9A Z80 10M 1812_2P
@EMC@ PC689
@EMC@ PC690
@RF@
PR638 @U42AR PR622 @U42AR PC616 @U42AR PR636 @U42AR PC646 @U42AR PR629 @U42AR PR617 @U42AR
100U_D2_20VM_R55M
100U_D2_20VM_R55M
2
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
1 1
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
D D
82P_0402_50V8J
82P_0402_50V8J
+ + +VCC_CORE @U42 +VCC_GT_+VCC_CORE
PC606
@ PC697
1
1
PR684 SOLDER_PREFORMS_0603
PC682
PC656
PC657
PC658
PC659
PC693
PC660
PC694
PC695
PC696
1 2
2 2 1 2
453_0402_1% 3.09K_0402_1% 68P_0402_50V8J 732_0402_1% 0.047U_0402_25V7K 86.6K_0402_1% 4.3K_0402_1%
2
2
For KBL U42 : Pop PR682 and PR684
For KBL U22 : Pop PR683 nAR U42
RF demand
PC626 @U42NAR PR613 @U42NAR PR621 @U42NAR PC617 @U42NAR PC624 @U42NAR PC642 @U42NAR PR651 @U42NAR
PL610
PU610 0.15UH_MMD-06BDER15MEM1L_27A_20%
10 11 IA_SW1 4 1
9 PGND
VIN
SW
SW
12 +VCC_CORE
3 2
PC655 8 13 0.1U_0402_25V6 93.1K_0402_1% 1K_0402_1% 220P_0402_50V7K 0.022U_0402_16V7K 0.022U_0402_16V7K 105K_0402_1%
0.1U_0402_25V6
VIN GL
IA1P
0.22U_0603_16V7K
RF@ PR663
IA1N
4.7_1206_5%
+5V_ALW
1
1
1 2 7 14
PC686
6 PHASE PGND 15 PR667 @U42 PR668 PR666 PR638 @U42NAR PR622 @U42NAR PC616 @U42NAR PR636 @U42NAR PC646 @U42NAR PR629 @U42NAR PR617 @U42NAR
N/C PVCC 3.65K_0603_1% 100K_0603_1% 10_0402_1%
2
1 2 5 16 1 2 1 2
1U_0402_10V6K
2
BOOT N/C
1
PR660 4 17
10K_0402_1%
2
1
3.9_0603_1% AGND N/C
@ PR686
PC661
(53) ISEN1_IA
3 @ PR670
IA_SNUB1
2 VCC 19 100K_0402_1% 453_0402_1% 3.09K_0402_1% 68P_0402_50V8J 732_0402_1% 0.047U_0402_25V7K 88.7K_0402_1% 4.3K_0402_1%
2
PR688 1 FCCM GL 18 IA2N 2 1
2
1_0603_5% PWM AGND
1 2 VCC_IA1 FDMF3035_PQFN31_5X5
nAR U22
+5V_ALW
1U_0402_10V6K
680P_0603_50V7K
(53,54)
(53,54)
ISUMP_IA
ISUMN_IA
1
RF@ PC662
PC1335
C C
PC626 @U22 PR613 @U22 PR621 @U22 PC617 @U22 PC624 @U22 PC642 @U22 PR651 @U22
2
2
@ PR659
0_0402_5% 0.047U_0402_25V7K 88.7K_0402_1% 316_0402_1% 1200P_0402_50V7K 0.022U_0402_16V7K 0.022U_0402_16V7K 105K_0402_1%
(53,54) FCCM_IA 1 2
@ PR687 PR638 @U22 PR622 @U22 PC616 @U22 PR636 @U22 PC646 @U22 PR629 @U22 PR617 @U22
0_0402_5%
1 2
(53) PWM1_IA
360_0402_1% 1.5K_0402_1% 33P_0402_50V8J 732_0402_1% 0.047U_0402_25V7K 88.7K_0402_1% 3.4K_0402_1%

10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
@U42 PC683
@U42 PC684
@U42 PC672
@U42 PC673
GPU_B+
1
PJP602
1 2
GPU_B+ CPU_B+
2
PAD-OPEN 1x2m~D
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
1
1
@U42 PL613
PC675
PC674
PC664
PC665
@U42 PU613 0.15UH_MMD-06BDER15MEM1L_27A_20%
10 11 IA_SW2 4 1
2
9 PGND
VIN
SW
SW
12 +VCC_CORE
3 2 @EMC@ PR669 @EMC@ PC670
@U42 PC671 8 13 4.7_1206_5% 680P_0603_50V7K
4.7_1206_5%
VIN GL
1
GT_SNUB
IA2P
B 0.22U_0603_16V7K IA2N 1 2 1 2 B
+5V_ALW
0.1U_0402_25V6
1
1 2 7 14
@U42 PC688
@EMC@ PR676
PHASE PGND
1
6 15 @U42 PR674 @U42 PR675 @U42 PR673

N/C PVCC 3.65K_0603_1% 100K_0603_1% PL612
10_0402_1%
1 2 5 16 1 2 1 2 PU612 0.15UH_MMD-06BDER15MEM1L_27A_20%
1U_0402_10V6K
2
BOOT N/C
1
4 17 10 11 GT_SW 4 1
10K_0402_1%
2
+VCC_GT
1
@U42 PR672 AGND N/C 9 PGND SW 12

@ PR689
@U42 PC1336
(53) ISEN2_IA VIN SW

3.9_0603_1% 3 3 2
IA_SNUB2
2 VCC 19 @ PR677 PC663 8 13
0.1U_0402_25V6
2
1 FCCM GL 18 IA1N 1 2 0.22U_0603_16V7K VIN GL

+5V_ALW
2
PWM AGND
1
100K_0402_1% 1 2 7 14
PC687
PHASE PGND PR661
@U42 PR691 FDMF3035_PQFN31_5X5 6 15
1_0603_5% N/C PVCC 3.65K_0603_1%
2
1 2 VCC_IA2 1 2 5 16
+5V_ALW
1U_0402_10V6K
BOOT N/C
1
(53,54)
(53,54)
ISUMP_IA
ISUMN_IA
PR665 4 17
10K_0402_1%
2
AGND N/C
1
3.9_0603_1%
PR1298
PC1337
1U_0402_10V6K
680P_0603_50V7K
1
(53)
(53)
ISUMP_GT
ISUMN_GT
3
@U42 PC677
@EMC@ PC678
2 VCC 19
2
1 FCCM GL 18 @
2
2
PR1300 PWM AGND
1_0603_5% FDMF3035_PQFN31_5X5
1 2 VCC_GT
+5V_ALW
@U42 PR671
0_0402_5%
1U_0402_10V6K
1
1 2
PC669
(53,54) FCCM_IA
@U42 PR692
2
0_0402_5%
1 2
(53) PWM2_IA
@ PR1299
0_0402_5%
1 2
A (53) FCCM_GT A
@ PR664
0_0402_5%
1 2
(53) PWM_GT
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857A
5 4 3 2 1
4
+VCC_CORE
22U_0603 * 6 pcs + 1U_0201 * 5 pcs
VCC_GT_+VCC_CORE Place on CPU
+VCC_GT_+VCC_CORE
PC1127
A
A
220U_D7_2VM_R4.5M
+220u_D7*3 pcs
22U_0603 * 33 pcs +1U_0201*33 pcs
VCC_CORE Place on CPU
2 1 2 1 2 1
1
+
PC1062 PC1099 PC1083 PC1076
220U_D7_2VM_R4.5M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
1
+
PC1095 PC1030 PC1081 PC1078
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2 1
PC1094 PC1031 PC1080 PC1077
PC1322 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
1
+
@U42 PC1321 PC1096 PC1032 PC1082 PC1079
PC1323 220U_D7_2VM_R4.5M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1090 PC1033 PC1067 PC1001
PC1324 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1093 PC1034 PC1072 PC1002
PC1325 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1091 PC1035 PC1069 PC1003
PC1326 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1097 PC1036 PC1074 PC1004
PC1327 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
B
B
2 1
PC1092 PC1037 PC1070 PC1005
PC1330 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1098 PC1038 PC1061 PC1006
PC1331 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1050 PC1039 PC1071 PC1007
PC1332 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1051 PC1084 PC1066 PC1008
PC1333 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1052 PC1086 PC1073 PC1009
PC1334 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
PC1053 PC1085 PC1068 PC1010

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC1054 PC1088 PC1075 PC1011

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1126 PC1087 PC1064 PC1012

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
22U_0603 * 12 pcs + 1U_0201*7 pcs
VCC_SA Place on CPU
PC1089 PC1065 PC1013

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
C
C
+VCC_GT
+220u_D7*2 pcs
22U_0603 * 19 pcs + 1U_0201 * 14 pcs
VCC_GT Place on CPU (U22)
PC1128
220U_D7_2VM_R4.5M
2 1 2 1 2 1
2
1
+
PC1063 PC1040 PC1133 PC1014

+VCC_SA
220U_D7_2VM_R4.5M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1
2
1
+
PC1041 PC1137 PC1015

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PC1181 PC1042 PC1129 PC1016

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2 1
2 1 @ PC1180 PC1043 PC1132 PC1017
PC1153 22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
D
D
1U_0201_6.3V6M PC1057 2 1 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 2 1 @ PC1177 PC1044 PC1136 PC1018
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1147 PC1058 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1179 PC1045 PC1134 PC1019
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1148 PC1059 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1176 PC1046 PC1020
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1149 PC1060 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1178 PC1047 PC1021
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M

Date:
Size
Title
PC1150 PC1139 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1175 PC1048 PC1022
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
Tuesday, November 14, 2017
Document Number
PC1151 PC1140 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PC1049 PC1023
1U_0201_6.3V6M 22U_0603_6.3V6M
PC1152 PC1141 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
PROCESSOR DECOUPLING
2 1 PC1055 PC1024
1U_0201_6.3V6M 22U_0603_6.3V6M
PC1142 2 1 2 1
22U_0603_6.3V6M
2 1 PC1056 PC1025
1U_0201_6.3V6M 22U_0603_6.3V6M
PC1143 2 1 2 1
22U_0603_6.3V6M
2 1 PC1328 PC1026
E
1U_0201_6.3V6M 22U_0603_6.3V6M
Sheet
PC1144 2 1
22U_0603_6.3V6M
2 1 PC1329
1U_0201_6.3V6M
PC1145
56
22U_0603_6.3V6M
2 1
of
PC1146
22U_0603_6.3V6M
59
R ev
1.0
1
A B C D
EMC@ PL901
+PWR_SRC_AC 1UH_PCMB051H-1R0MS_8A_20%
1 2
+SDC_IN +CHARGER_SRC
PR901
0.01_1206_1% @ PJP901
1 4 1 2
+PWR_SRC
2 3 PAD-OPEN 4x4m
SMF4L22A SOD123FL-2
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
1
2200P_0402_50V7K
15U_B2_25VM_R100M
1
+
PD906
@EMC@ PC902
@EMC@ PC903
PC909
1
1
PC911
PC904
PC905
PC906
@ 2
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
10U_0603_16VAK
1 1
15U_B2_25VM_R100M
1
1
+
PC913
PC914
PC915
PC916
PC917
PC918
PC919
PC920
PC990
2
2
@ 2
10U_0603_25V6M
10U_0603_25V6M
1
1
PC951
PC952
1
1
PR909 PR910
EMI demand
2
2_0603_1% 2_0603_1%
2200P_0402_50V7K
2
1U_0402_25V6K
1U_0402_25V6K
0.1U_0402_25V6
1000P_0402_50V7K
1000P_0402_50V7K
1
1
@EMC@ PC928
@EMC@ PC929
@EMC@ PC986
@EMC@ PC987
@EMC@ PC988
@EMC@ PC989
PC925
4.7U 6.3V M X5R 0402
2
CSIP_ISL9538 1 2 CSIN_ISL9538
1U 25V K X5R 0402
1U 25V K X5R 0402

1
1
PC926
PC927
2
2
+PWR_SRC
2
PC930
+SDC_IN PR943
PD901 0_0603_5% 0.22U_0603_25V7K RF demand
2 1
2 1 1 2 ADP_ISL9538
+PWR_SRC
SDMK0340L-7-F_SOD323-2~D PR914
1
4.7_0603_5%
PD903
PR944
2 1
TBTA_DC_SS 442K_0402_1%
82P_0402_50V8J
82P_0402_50V8J
82P_0402_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
1
1
2 2
PC956
PC957
PC958
PC959
PC960
PC961
PC962
PC963
2
RB520SM-30T2R_EMD2-2
BOOT1_ISL9538
ACIN_ISL9538
CSIP_ISL9538
CSIN_ISL9538
UG1_ISL9538
LX1_ISL9538
LG1_ISL9538
2
PD904
1
2 1
RF@
RF@
RF@
RF@
RF@
RF@
RF@
RF@
TBTB_DC_SS
1
PC955 PR945 PR915

0.1U 25V K X5R 0402 100K_0402_5% 4.7_0603_5%
2
RB520SM-30T2R_EMD2-2 1 2 VDD_ISL9538
2
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%
9
ISL9538HRTZ-T TQFN 32P PWM
PC931
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
ADP
CSIP
ASGATE
1
1U_0603_25V6
+VCHGR
9
1 2 @ PR960 DCIN_ISL9538
0_0402_5% 17 8 VDDP_ISL9538 2 1 UG1_ISL9538 1 8 LG1_ISL9538 LG2_ISL9538 8 1 UG2_ISL9538 PQ906
D1
D1
1 2 DCIN VDDP G1 G2 G2 G1 PR917 EMZB08P03V_DFN8-5
VDD_ISL9538 LG2_ISL9538 LX1_ISL9538 LX2_ISL9538
2 1 18
VDD LGATE2
7 PC932 2
S1/D2 D2/S1
7 PL902 7
D2/S1 S1/D2
2 0.005_1206_1% 1 +PBATT
2
1U_0402_6.3V6K 1UH_PCMB102T-1R0MS_10.8A_20% 2
PC933 PR918 @ PR919 ACIN_ISL9538 19 6 LX2_ISL9538 3 6 1 2 6 3 1 4 3 5
1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 D1 D2/S1 D2/S1 D1
100K_0402_1%
1 2 OTGEN/CMIN 20 5 UG2_ISL9538 PR921 4 5 5 4 2 3
S2
S2
@ PR920 OTGEN/CMIN UGATE2 4.7_0603_5% D1 D2/S1 LX1_ISL9538 LX2_ISL9538 D2/S1 D1
1
4
ACAV_IN1 1 2 0_0402_5% 21 4 BOOT2_ISL9538 2 1 2 1
10U_0603_16VAK
10U_0603_16VAK
(36,47) PBAT_CHARGER_SMBDAT
10
10
SDA BOOT2
1
@ PR922
4.7_1206_5%
4.7_1206_5%
1
PQ909 1 2 0_0402_5% 22 3 PC934 PQ905
EMC@ PR923
EMC@ PR924
(36,47) PBAT_CHARGER_SMBCLK PQ904
SCL VSYS
1
1
D
PR925 @ PR926 0_0402_5% 0.22U_0603_25V7K AOE6936_DFN5X6E8-10 AOE6936_DFN5X6E8-10
PC935
PC936
OTGPG/CMOUT
2 154K_0402_1% 1 2 PROCHOT#_ISL9538 23 2 CSOP_ISL9538

(12,36,53) PROCHOT#
AMON/BMON
(36) AC_DIS PROCHOT# CSOP

G
4700P_0402_25V7K
1SNUB_CHG1 2
1SNUB_CHG2 2
2
1
CSON_ISL9538
BATGONE
S (57) PROCHOT#_ISL9538 @ PR928 24 1

3
ACOK CSON
2
L2N7002WT1G 1N SC-70-3 0_0402_5% @ PR929
PC937
BGATE
CMOP
PROG
ACOK_ISL9538
PSYS
VBAT
1 2 0_0402_5%
1 2
680P_0603_50V7K
680P_0603_50V7K
1
PR927 +PWR_SRC @
BGATE_ISL9538
2
1M_0402_1% @ PR930 PC938

25
26
27
28
29
30
31
32
100K_0402_1% 10P_0402_50V8J
EMC@ PC940
EMC@ PC941
PR931 1 2 1 2 1 2
100K_0402_1%
105K_0402_1%
2
2 PR932 1
(36,47) PBAT_PRES#
1 2 @ PC939 0.1U_0402_25V6 3
PR933
BGATE_ISL9538
VBAT1_ISL9538
100K_0402_1%
1 2
+3.3V_ALW @ PR951
0_0402_5%
(57) CMOUT
1 2
@ PC942
COMP_ISL9538 1U 25V K X5R 0402
1 2
1
@ PR934
0_0402_5%
0.1U_0402_25V6
560P_0402_50V7K
PR937
1
1
PC947
1_0603_1%
0_0402_5%
16.5K_0402_1%
1
1 2
@ PC943
@ PR947
@ PR935
@ PR936
PR948
0_0402_5%
0_0402_5%
2
2
2
2
@ PC945 PR938
.012U 16V K X7R 0402
2
2
1
PC944
1U 25V K X5R 0402 1_0603_1%

1
2
1 2
2
+3.3V_VDD_PIC
I_BATT
I_ADP
PC946 @ PR950
0.22U_0402_25V6K 0_0402_5%
1 2 1 2
I_SYS
@ PR939
0_0402_5% PC949
(25,57) AC1_DISC#
1 2 3 0.1U_0402_10V7K
I_BATT
1 2
I_ADP
(36,53)
@ PR941 1
0_0402_5%
5
+PBATT (26,57) AC2_DISC#
1 2 2 @ PR946
1
(36)
(36)
@ PR942 1 0_0402_5%
100K_0402_1%
P
2 1 IN1 4 1 2
PR961
0_0402_5% ACAV_IN (36)
PD905 ACAV_IN1 1 2 2 O
G
PR940 BAT54CW-7-F SOT-323 DII IN2
2
1
100K_0402_1%
4 100_0402_5% PU903 4
PR953
Close to EC ADP_I pin @ PC950 @ MC74VHC1G08DFT2G SC70 5P AND
0.1U_0402_25V6
For IT8010 voltage leakage issue
1
2
PR948 @U22 PR948 @U42
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
16.5K_0402_1% 11.8K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_charger_ISL9538
A B C D
5 4 3 2 1
PJP1201
1 2
PAD-OPEN 1x2m~D S2 PD1202
S5 S1 2 1
B2100AF-13 SMAF-2
EMC@ PL1203
@ PQ1200 PQ1202 PQ1203 +SDC_IN
FBMA-L11-201209_0805
EMZB08P03V_DFN8-5 EMZB08P03V_DFN8-5
TBTA_DC_SS EMZB08P03V_DFN8-5
+TBTA_VBUS 1
EMC@ PL1201
2 +TBTA_VBUS_1 1 1 1
FBMA-L11-201209_0805 2 2 2
1 2 5 3 +AC1_IN 3 5 5 3
2
PR1277 +3.3V_VDD_PIC
100P_0402_50V8J
1000P_0402_50V7K
100P_0402_50V8J
4
1
AO3409 P-CHANNEL SOT-23

300K_0402_5% PR1202
0.1U_0402_25V6
PR1201
1M_0402_1%
300K_0402_5%
1500P_0402_50V7K
S1_OVP
0.022U_0402_25V7K
1
2
PC1283
PC1201
PC1202
@EMC@ PC1203
1M_0402_5%
2
2
1
S
D PR1205 D
PQ1225
PR1206
499K_0402_1%
499K_0402_1%
1
1
3
S
2
G
PQ1204
PC1204
PC1206
100K_0402_5%
2
2
G
@ @ PR1287 PC1205 2
PR1203
PR1204
1
EMC@
EMC@
1
@EMC@
10K_0402_5% +3.3V_VDD_PIC D 0.47U_0603_25V6K
1
@ PR1279 D
1
1
@ 100K_0402_5%
2
PR1278
6
100K_0402_5% PR1207
L2N7002WT1G 1N SC-70-3
@ PR1210
PC1202 can't over 1000P 100K_0402_5%
1
D
@ PR1208 0_0402_5%
PQ1224A
2
EN_PD_HV_1#
2
2 +3.3V_VDD_PIC 0_0402_5% 2 1 2
PQ1205
AC_DISC# (36,57)
1
PR1209 G
L2N7002WT1G 1N SC-70-3
@
49.9K_0402_1% S
3
2
2
D
PR1284
1
PR1212 2
PQ1206
0_0402_5%
1
2
3
49.9K_0402_1% G
+3.3V_VDD_PIC S5 OVP (26,57) EN_PD_HV_2 +3.3V_VDD_PIC @ PR1211
PQ1224B
S
+3.3V_VDD_PIC
3
100K_0402_5%
1
6
+TBTA_VBUS_1 5
(25,57) EN_PD_HV_1
2
PD1201 PC1207 @ PR1214 PQ1207A
1
2
0.01U_0402_25V7K 0_0402_5%
PR1213
100K_0402_5%
4
SDMK0340L-7-F_SOD323-2 1 2 1 2 2 PQ1207B
1
3
1 2 DMN65D8LDW-7_SOT363-6
499K_0402_1%
221K_0402_1%
1
6
PR1217 @ PR1219 @ PR1221
100K_0402_5%
0.1U_0402_25V6
1
5
2
PR1218 47K_0402_1% @ 0_0402_5% 0_0402_5%
PR1215
PR1216
1
1.8M_0402_1% PQ1201A 1 2 1 5 1 2
PC1208
PR1220
P
(25,57) EN_PD_HV_1 IN1 VBUS1_ECOK_R (36,57)
1 2 2 DMN65D8LDW-7_SOT363-6 4
2
2
O
3
1 2 2
2
4
G
8
2
PU1201A @ PR1223 IN2
1
2
3 LM393DGKR_VSSOP8 0_0402_5% @ PR1222 PR1224
P
3
+ 1 1 2 5 PR1285 0_0402_5% PU1202
O 100K_0402_5%
2.2U 25V M X5R 0402
0.1U 25V M X5R 0402

2 PQ1201B 1M_0402_5% MC74VHC1G08DFT2G SC70 5P AND
G
-
1
10U 10V M X5R 0402
200K_0402_1%
200K_0402_1%
100P_0402_50V8J
1
1
1
PC1211
PC1212
4
1
1
1
PR1225
PC1209
PR1227
PC1210
PQ1209
2
2
@ PR1226 L2N7002WT1G 1N SC-70-3
2
0_0402_5%
2
D
1 2 3 1
(36) DCIN1_EN_R
@
L2N7002WT1G 1N SC-70-3)
@ PR1230 PT1
G
(From EC)
2
1
D
0_0402_5% PAD~D @ PR1295
100K_0402_5%
LPSA_PROTECT#
2
2 1 2 0_0402_5%
PQ1208
S3_OVP
1
1 2
PR1228
G
100K_0402_5%
1
@ PR1232 @ PR1233
PR1229
S
3
PR1231 0_0402_5% 0_0402_5%

10K_0402_5% 1 2
EN_PD_HV_1 (25,57)
1
2
2
2
C C
+3.3V_VDD_PIC
+3.3V_ALW
PJP1202
1
PAD-OPEN 1x2m~D
2
S4 PD1205
S6 S3
2 1
B2100AF-13 SMAF-2 +SDC_IN

EMC@ PL1204
FBMA-L11-201209_0805 @ PQ1210 PQ1211 TBTB_DC_SS PQ1212
EMZB08P03V_DFN8-5 EMZB08P03V_DFN8-5 EMZB08P03V_DFN8-5
+TBTB_VBUS 1
EMC@ PL1202
2 +TBTB_VBUS_1 1 1 1
FBMA-L11-201209_0805 2 2 2
1 2 5 3 +AC2_IN 3 5 5 3
1500P_0402_50V7K
2
+3.3V_VDD_PIC
100P_0402_50V8J
0.1U_0402_25V6
1000P_0402_50V7K
100P_0402_50V8J
4
1

PR1280 PR1235
1
1
PC1213
PC1214
@EMC@ PC1215
PR1234
PC1216
1M_0402_1%
1M_0402_5%
S3_OVP 300K_0402_5% 300K_0402_5%

1
2
PC1284
@ PR1236
499K_0402_1%
0.022U_0402_25V7K
3
1
S
PR1239
PQ1227
499K_0402_1%
2
1
1
3
S
+3.3V_VDD_PIC 2
G
PC1217
PQ1213
PR1237
PC1218
PR1238
100K_0402_5%
2
1
EMC@
@EMC@
G
@ @ PR1288 0.47U_0603_25V6K 2
2
2
EMC@
1
10K_0402_5% D
2
1
PR1281 PR1282 D
1
@
100K_0402_5% 100K_0402_5%
2
PR1240
L2N7002WT1G 1N SC-70-3
@ PR1243
PQ1226A
PC1214 can't over 1000P EN_PD_HV_2# 100K_0402_5%
1
2 D
@ PR1241 0_0402_5%
2
0_0402_5% 2 1 2
PQ1214
AC_DISC# (36,57)
1
PR1244 G
1
+3.3V_VDD_PIC
L2N7002WT1G 1N SC-70-3
49.9K_0402_1% S
3
1
2
D
PQ1226B
3
2
2
PQ1215
1
1
PR1246 G
@ PR1283
+3.3V_VDD_PIC 49.9K_0402_1% S
3
5 0_0402_5%
(26,57) EN_PD_HV_2
2
6
S6 OVP
1
+3.3V_VDD_PIC (25,57) EN_PD_HV_1 +3.3V_VDD_PIC @ PR1242 PC1219 @ PR1248 PQ1216A
2
100K_0402_5% 0.01U_0402_25V7K 0_0402_5% DMN65D8LDW-7_SOT363-6
+TBTB_VBUS_1 1 2 1 2 2
B PD1206 @ PR1245 PQ1216B B
100K_0402_5%
1
2
3
0_0402_5% DMN65D8LDW-7_SOT363-6
PR1249
100K_0402_5%
0.1U_0402_25V6
1
2
SDMK0340L-7-F_SOD323-2 1 2 1 @ PR1255
P
(26,57) EN_PD_HV_2
1
1
1 2 IN1 4 0_0402_5%
PC1220
PR1250
499K_0402_1%
221K_0402_1%
O
1
PR1254 1 2 2 5 1 2
VBUS2_ECOK_R (36,57)
G
IN2
2
PR1256 47K_0402_1% @
PR1252
PR1253
2
1.8M_0402_1% PQ1217A PR1286 @ PR1247
4
1 2 2 DMN65D8LDW-7_SOT363-6 1M_0402_5% 0_0402_5% PU1203 PR1257
2
MC74VHC1G08DFT2G SC70 5P AND 100K_0402_5%

2
PU1201B @ PR1259
1
5 LM393DGKR_VSSOP8 0_0402_5%
P
1
+ 7 1 2 5 PQ1218 +3.3V_ALW +3.3V_ALW
O
10U 10V M X5R 0402
2.2U 25V M X5R 0402
0.1U 25V K X5R 0402
6 PQ1217B @ PR1251 L2N7002WT1G 1N SC-70-3

G
1
- DMN65D8LDW-7_SOT363-6 0_0402_5%
200K_0402_1%
200K_0402_1%
100P_0402_50V8J
4
1
2
S
1 2 3 1
PC1221
PC1223
PC1224
(36) DCIN2_EN_R
4
1
PR1263 @ PR1264 @
PR1261
PR1262
PC1222
100K_0402_5% 100K_0402_5% +3.3V_ALW

2
@ PR1275
G
100K_0402_5%
2
0_0402_5%
2
1
1 2
PR1258
(36,57) VBUS2_ECOK_R
100K_0402_5%
CMOUT (56)
1
2
@ PR1276
PR1260
@
L2N7002WT1G 1N SC-70-3)
@ PR1266 (From EC) PT2 @ PR1296 @ PR1265 0_0402_5% AC_DISC# (36,57) PR1291
1
1
D 1 2
0_0402_5% PAD~D 0_0402_5% 0_0402_5% (36,57) VBUS1_ECOK_R 100K_0402_5%
2 1 2 LPSB_PROTECT# 1 2 S1_OVP
PQ1219
G @ PR1292
2
1
1
S @ PR1269 +3.3V_VDD_PIC +3.3V_ALW +3.3V_ALW 0_0402_5%

3
PR1270 0_0402_5% 1 2
2
10K_0402_5% 1 2
EN_PD_HV_2 (26,57)
6
1500P_0402_50V7K
2
+3.3V_ALW PR1267 PQ1222A
2
3
100K_0402_5% DMN65D8LDW-7_SOT363-6
2
PR1271 PQ1221B PQ1222B 2
PC1285
1
3
100K_0402_5% DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6
5
1
1
2
@ PR1293 @ 5
4
0_0402_5%
1
6
1 2 PQ1221A
(25,57) EN_PD_HV_1
4
PQ1220A
3
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6 PROCHOT#_ISL9538 (56)

@ PR1273 PQ1220B 2 +3.3V_ALW +3.3V_ALW
0_0402_5% DMN65D8LDW-7_SOT363-6
1
1 2 5 D
(25,56) AC1_DISC#
2
2
PQ1228
L2N7002WT1G 1N SC-70-3
G
4
PR1272 PR1268 S
3
100K_0402_5% 100K_0402_5%
1
A 1 2 A
@ PR1289
6
0_0402_5%
@ PR1294 PQ1223A
3
0_0402_5% DMN65D8LDW-7_SOT363-6
1 2 PQ1223B 2
(26,57) EN_PD_HV_2
@ PR1274 5
1
0_0402_5%
1 2
(26,56) AC2_DISC#
4 1 2 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

@ PR1290 Title
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_2TypeC PD_Selector
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) LA-F292P

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1 37 MEC5105
UE2.P19 USH_EXPANDER_SMBCLK 0.2(X01)
2017/05/16 EE for smbclk/data missed on EVT CKT UE2.P20 USH_EXPANDER_SMBDAT
2 HDMI
22 MEC5105 2017/05/16 EE GPIO naming DISPLAY_HPD_EC change to DISPLAY_HPD_EC# 0.2(X01)
3 Power control
37 MEC5105 2017/05/16 EE CKT naming error UE1.H5 HW_GPS_DISABLE# naming to GPS_DISABLE# 0.2(X01)
Power control
Add QZ15 ,RZ517,RZ518
4 37 2017/05/16 EE modify WLAN PWR enable control CKT EC GPIO133 change to "SLP_WLAN#_GATE" 0.2(X01)
MEC5105
AR
Add RE506
5 36 2017/05/23 EE for AR Contact "TBT_RESET_N_EC" From UE2 to UT1 0.2(X01)
PD
change RT87,RT88 to stuff
6 25 2017/05/23 EE BOM error change RT89,RT90 to non-stuff 0.2(X01)
7 43 screw hole 2017/05/16 EE part reference naming error "ST1 " change to "ST1", delete unnecessary space 0.2(X01)
8 57 Type C 2017/05/24 EE AR layout Change RT159 pop 0.2(X01)

C C
add RT409,RT410
UT1.J4 from TBTA_I2C_INT Change to TBTB_I2C_INT_R &
52 Type C
2017/05/24 EE AR layout Add0 ohm to TBTB_I2C_INT 0.2(X01)
9
UT1.E2 from TBTB_I2C_INT Change to TBTA_I2C_INT_R &
Add0 ohm to TBTA_I2C_INT
swap PA to TBTB, PB to TBTA
Change ROM From TBTA to TBTB 0.2(X01)
Del FLASH Conn.
Change RT63 to @
10 56 Type C 2017/05/24 EE AR layout RT218 change to TBTA_ROM_CLK_PD Pull-Down
RT219 change to TBTA_ROM_DI_PD Pull-Down
RT220 change to TBTA_ROM_DO_PD Pull-Down 0.2(X01)
RT221 change to TBTA_ROM_CS#_PD Pull-Up to +3.3V_TBTA_FLASH
PD
see 0525 swap list
11 36 2017/05/25 EE EC to PD SMB swap follow EC request SMB ADDR need same with NAR SKU, SWAP UPD1/UPD2 SMB 0.2(X01)
see 0525 swap list
follow EC request need to swap
12 36 EC MEC5105 2017/05/25 EE EC control power phase EC SWAP 1.DCIN1_EN and DCIN2_EN
B 0.2(X01) B
2.VBUS1_ECOK and VBUS2_ECOK
13 36 EC MEC5105 2017/06/01 EE DFB request YE1 change PN from SJ10000PW00 to SJ10000Q400 0.2(X01)
14 36 EC MEC5105 2017/06/01 EE BOM error Change RE95 to stuff 0.2(X01)
HDMI
change CT203 to @
15 22 2017/06/01 EE HDMI EA test change RV32 to 200_0402_1% SD034200080 0.2(X01)
16 28 BOARD_ID 2017/06/01 EE BOARD_ID RE79 Change to 130k ohm 0.3(X02)
17 35 codec 2017/06/01 EE DFB request LA13 footprint change to TAI-T_HCB2012KF-121T50_2P DFX requirement 0.3(X02)
Card Reader
RTK Vic suggest add GPIO1 PU
18 32 2017/06/02 EE GPIO UR1.32 from SD_GPIO change to SD_GPIO0 0.3(X02)
UR1.1 PU 10K to +3.3V_MMI_IN
1.UE1.D9 from SLP_WLAN#_GATE Change to SIO_SLP_WLAN#
19 36 EC MEC5105 2017/06/02 EE modify WLAN PWR enable control CKT 2.NGFF_CONFIG_1 PU RE552 Cheange Location to RE562 0.3(X02)
3.SLP_WLAN#_GATE contact to EC GPIO114(Add RE552)
1. RE563 change Location to RE600
EE align schematic 2. RE564 change Location to RE601
20 36 EC MEC5106 2017/06/02 3. RE565 change Location to RE602 0.3(X02)
4. RE566 change Location to RE603
A A
Title
EE P.I.R (1/3)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
LA-F292P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Item Page# Date Issue Description Solution Description Rev.
1 57 2017/06/6 TI symbol shortage issue PQ904 / PQ905 change to AOE6936 (SB00001JP00) X01
because TI shortage issue
D D
2 55 2017/06/6 TI symbol shortage issue PU610 / PU612 / PU613 change to FDMF3035 (SA0000AHX00) X01
because TI shortage issue
3 57 2017/06/14 NA Change PR915,PR909,PR910,PR937,PR938 size from 0402 to 0603 X01

because Charger IC version update fine-tune
4 52 2017/06/14 NA JUMP PJP403 / PJP404 change to PL407 / PL408 EMI bead X01
5 55 2017/06/14 NA Add un-stuff footprint PC693 ~ PC696 for RF request X01
6 57 2017/06/14 NA Add un-stuff footprint PC990 B2 size footprint for acoustic concern X01
7 57 2017/06/14 NA Add PL901 EMI choke for EMI request X01
8 49 2017/06/14 For thermal derating concern Change +5V_ALW output MLCC type from X5R to X6S X01
for more thermal derating
C Change MOS solution to 2nd source C

9 58 2017/06/14 Vendor sample EOL from AON7409 to EMZB08P03V because vendor EOL X01
Location : PQ1202,PQ1203,PQ1211,PQ1212,PQ906
Change MOS solution to 2nd source

10 54 2017/06/14 Vendor sample EOL from AON7934 to PE642DT because vendor EOL X01
Location : PQ614
For nAR U22

1. PR636 from 665 change to 732
11 55 2017/08/4 For new CPU driver MOS fine-tune R/C value 2. PR651 from 113K change to 105K X02
3. PR613,PR629 from 86.6K change to 88.7K
4. PC626,PC646 from 0.01uF change to 0.047uF
For nAR U42

2. PR651 from 113K change to 105K X02
12 55 2017/08/4 For new CPU driver MOS fine-tune R/C value 3. PR629 from 86.6K change to 88.7K
B 4. PC626 from 0.033uF change to 0.1uF B
5. PC646 from 0.01uF change to 0.047uF

For AR U42
2. PC626 from 0.033uF change to 0.1uF X02
13 55 2017/08/4 For new CPU driver MOS fine-tune R/C value 3. PC624 from 0.033uF change to 0.01uF
1. PR202 and PC204 change to stuff

2. PR663 and PC662 change to stuff X02
14 55 2017/08/10 Stuff component for RF request
3. PC693, PC694, PC695 change to stuff
15 57 2017/08/10 Reserve footprint for chagrer input Add PD906 for footprint reserve X02
16 57 Reserve footprint change to stuff PD906 reserve footprint change to stuff A00
A A
Title
PWR P.I.R

5 4 3 2 1
5 4 3 2 1

Request
D D
21 36 MEC5105 2017/06/07 EE UPD1_HPD/UPD2_HPD RE553/RE554 resistor to 1M ohm(change to SD028100480) 0.3(X02)
22 11 CPU(6/14) 2017/06/15 EE Microchip request RC444 Change to @ 0.3(X02)

23 39 USH 2017/06/15 EE NPCT75x Pop RZ89, RZ365, RZ112,Depop RZ367, RZ366, RZ62, RZ363 0.3(X02)
24 11 CPU(6/14) 2017/06/15 EE SUSACK# SUSACK#_R Reserved RC550 PU 1K to +3.3V_1.8V_PGPPA 0.3(X02)
25 11 CPU(6/14) 2017/06/15 EE XTAL RC417,RC418 change to 33 ohm 0.3(X02)
26 38 TPM 2017/06/15 EE NPCT750 RZ69.1 From +UZ12_VHIO Change to +3.3V_ALW_PCH 0.3(X02)
27 12 CPU(7/14) 2017/06/15 EE ME Lock RC223.1 from ME_FWP change to ME_FWP_SW 0.3(X02)
28 9 CPU 2017/07/27 EE align schematic Reserved RC557 PU,RC558 PD 0.5(X04)
29 23 AR 2017/07/27 EE align schematic 、
Add RT419、
RT420 & Add RT421 to EC& Reserved RT422 to PCH 0.5(X04)
30 9 CPU 2017/07/27 EE align schematic Remove RC405 0.5(X04)
HDMI
LV31~LV36 Change to 8.2 ohm & LV37~LV38 Change to 15nH,
C 31 22 2017/08/07 EE EMI request 、
CT201、、CT20 4 chang e t o @
CT202 0.5(X04) C
32 37 EC 2017/08/08 EE BOARD ID BOARD ID RE79 From 130K change to 62K 0.5(X04)
9 CPU (4/14) 2017/08/09 EE RTD3 Reserved RC559

33 0.5(X04)
34 9 2017/08/09 EE RTD4
CPU (4/14) 、
Add RC560、
Reserved RC561 0.5(X04)
、
PJP7 Change to RT450 Reserved、Add RT451 to +3.3V_ALW
35 2 5 、2 6 PD 2017/08/09 EE PD PJP9 Change to RT452 、 Reserved RT453 to +3.3V_ALW 0.5(X04)
36 23 AR 2017/08/10 EE RTD3 Add RT456 For RDT3 0.5(X04)

37 9 CPU (4/14) 2017/10/30 EE GPIO map change Depop RC330, RC331 1.0(A00)
38 12 CPU (7/14) 2017/10/30 EE ME SW depop Depop RC222, SW1, RC221 change to 0 ohm short pad 1.0(A00)
B B
39 44 PAD,LED 2017/10/30 EE PWR SW depop Depop SW3 1.0(A00)

MEC5105
40 38 support 2017/10/30 EE UE2 depop Depop UE2,CE501,CE502,RE501,RE503,RE528,RE504,CE500 1.0(A00)
MEC5105
41 38 support 2017/10/30 EE BOARD ID BOARD ID RE79 From 62K change to 4.3K 1.0(A00)
42 8 CPU (3/14) 2017/10/30 EE Add solder mask Add footprint -NPM on UC6 1.0(A00)
Add footprint -NPM on LV3, LV6, LV9, LV12, RI27, RI28,
HDMI CONN RI29, RI30, RI47, RI48, RI49, RI50
43 2 3 、3 4 & NGFF Card 2017/10/30 EE DFX request 1.0(A00)
44 39 USH & TPM 2017/10/30 EE TPM A-rev. UZ12 SA0000AQ200->SA0000AQ220 1.0(A00)
45 All All 2017/10/30 EE 0 ohm change to short pad 0 ohm change to short pad 1.0(A00)
[Type C]
46 27 PD Power-2 2017/10/30 EE Change Part Number UT7 SA00009TZ00 change to SA00009TZ10 1.0(A00)
[Type C]
47 2 5 、2 6 2017/10/30
PD Controller TI EE PD change main source UT5 UT11 SA0000AX700 change to SA0000BIJ00 1.0(A00)
A A
Title
EE P.I.R (2/3)
LA-F292P
5 4 3 2 1
5 4 3 2 1

Request
D D
48 9,23 TBT-AR-DP 2017/10/30 EE RTD3_CIO_PWR_EN PU change Depop RT372, pop RC559 1.0(A00)
(1/2) DP, PCIE
TBT-AR-DP
49 23 (1/2) DP, PCIE 2017/10/30 EE EMI HDMI request CT201,CT202 depop 1.0(A00)
50 22 HDMI CONN
EE EMI HDMI request RV32 SD034200080->SD028360080
2017/10/30 LV31,LV32,LV33,LV34,LV35,LV36 SHI0000JI00->SHI0000I300 1.0(A00)
[Type C]
51 2 5 、2 6 2017/11/02
PD Controller TI EE Material change CT74,CT83,CT150 SE000010V00->SE00000QL10 1.0(A00)
C C
B B
A A
Title
EE P.I.R (3/3)
LA-F292P
5 4 3 2 1

Compal La-F292p Dda30 r1.0

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Compal La-F292p Dda30 r1.0

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A B C D E

PCB NO : LA-F292P Kirkwood MLK Port Map as of 2017-04-13

X9 KBL UMA U42

@ : Nopop Component RTD3@ : Support RTD3 Component

CONN@ : Connector Component

USB2.0[8] Wacom G12T Touchscreen/Pen

S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

S5 S4/AC ON OFF OFF ON OFF

S5 S4/AC doesn't exist OFF OFF OFF OFF OFF

SIO_SLP_SUS# CPU PWR

ISL95808 CSD97396 CSD97396 AO6405

+3.3V_ALW +3.3V_CV2 +3.3V_RUN

MEC 5105 04 C3 UPD1_SMBCLK

UC1I CPU@ KBL-R U4+2

B31 CSI2_DN6 AP2 MEM_CONFIG0

<20> DDR_A_D[0..63] <21> DDR_B_D[0..63]

KBL-R U4+2 <20> DDR_A_CAB[0..9] KBL-R U4+2 <21> DDR_B_CAB[0..9]

+1.2V_MEM LPDDR3 COMPENSATION SIGNALS

@ RC31 1K_0402_5% WEAK INTERNAL 20K PD

PCH_SPI_D3_R1 @ RC407 1 2 33_0402_5% PCH_SPI_D3_1_R +3.3V_ALW_PCH

PCH_SPI_CLK_R1 @ RC408 1 2 33_0402_5% PCH_SPI_CLK_1_R

B PCH_SPI_D1_R1 @ RC410 1 2 33_0402_5% PCH_SPI_D1_1_R B

+3.3V_RUN UC1F CPU@ KBL-R U4+2

@ RC560 AN8 P2 MEM_INTERLEAVED

S TR BSS138W 1N SOT-323-3 10K_0402_5%

BOOT BIOS Dest i nat i on(Bi t 10

Internal 20k PD 10K_0402_5% 10K_0402_5%

DIMM TYPE AR_DET#

TYPEC_CON_SEL1 LOW LOW HIGH HIGH HIGH Interleave HIGH NON AR

For AR, Kirkwood

UC1H CPU@ KBL-R U4+2

12/17:INT1 is PP mode, depop RC370,double check.

UC1J CPU@ KBL-R U4+2

2 1 PCH_PCIE_WAKE# @ RC325 0_0402_5% CC23

1 4 2 ESD Request:place near CPU side

10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

Compal Electronics, Inc.

@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% 1 1 1 ESD request,Place near CPU side.

HIGH ENABLE HIGH DISABLE

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

For Skylake , RC120 depop

@ RC2161 2 0_0603_5% +1.0V_PRIM_XDP CXDP@

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

Place close CPU side

CAD Note: Place the PU resistors close to CPU

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

UC1M CPU@ KBL-R U4+2

A48 KBL-U / KBL-R U4+2 N70

N64 VCCGT VCCGTX_AM58 AU58

1 1 1 BB32 AM30 TC7SH08FU_SSOP5~D

BB41 AM42 +VCC_SA

SIO_SLP_S3# HIGH HIGH LOW

+1.0V_VCCST source +1.0V_VCCSTG source

close UC1.AL1 and <120mil

@ RC2351 2 0_0402_5% T19

ESPI@ RC212 1 2 0_0402_5% 1 2 1 KBL-RU42_BGA1356 15 OF 20

@ RC1731 2 0_0402_5% @ RC1701 2 0_0402_5%

close UC1.N20 and <100mil 1 1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on