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EE 445 Computer Architecture I, Short Exam 1

October 24, 2022
Number of questions: 2. Time allowed: 50 minutes.
This exam only covers Algorithmic State Machines and Register Transfer Language
(plus the relevant EE 348 Review).
Please show your work. Only what you write on the solution sheets will be graded.
Best of luck.
Question 1 (25 points):
A selective insert microoperation is defined for registers A, B, and C as follows:
The bit pattern in B is used to determine which bits of C are inserted in A.

Example:
A(t): 1 1 0 0
B: 1010
C: 0011
A(t+1): 0 1 1 0

(a) (8 points) What is the RTL representation for this micro-operation?

(b) (17 points) Design and draw the typical cell Ai of a register A implemented by a T FF (remember:
Q(t+1)=T⊕Q(t)). The control signals and the RTL microoperations are as follows:

P1: Selective insert (as described above) with registers B and C.

P2: AB∨C (here ∨: LOGICAL OR).
P3: AA’.

Use the separate design method. At most one of the control signals can be asserted at a time. If none of the
control signals P1, P2, P3 are asserted, A keeps its value. In your drawing, clearly show the typical register
cell Ai with its T FF, the required Boolean expressions (combining control signals along with Ai, Bi, Ci),
and the clock. Do not draw the gates for these Boolean expressions; simply write down the expressions
where needed in the drawing.
Question 2 (75 points):
The Booth’s multiplication algorithm is used to multiply two n-bit numbers X and Y to get the result Z. All
numbers are represented in signed 2’s complement representation. Suppose the magnitude of either number
is at most 2n-1-1.
The following register configuration is given:

A, B: n-bit registers
R1, R2, C: (2n+1)-bit registers.
D: 2n-bit register.
P: log2(n) bit counter with decrement input and 0-check output Pzero that is asserted if P is all 0’s.
Assume that register A is loaded with X and register B is loaded with Y before the algorithm starts. The
algorithm starts with the start signal S, and register D holds Z upon completion.

A typical implementation of the algorithm can be summarized as follows:

1- Upon the start signal S initially:
➢ Load the n leftmost bits of R1 with A, and load the remaining n+1 bits of R1 with zeros.
➢ Load the n leftmost bits of R2 with the 2’s complement of A (which is A’+1), and load the
remaining n+1 bits of R2 with zeros.
➢ Load the n leftmost bits of C with zeros, load the next n bits of C with B, and load the
rightmost bit with 0.
➢ Load P with 1’s (equivalent to n-1).
2- Check the two rightmost bits of C:
➢ If they are 01, load C+R1 (here +: ADDITION) to C. Ignore the overflow.
➢ If they are 10, load C+R2 (here +: ADDITION) to C. Ignore the overflow.
➢ Otherwise, leave C unchanged
3- Perform an arithmetic shift right by one position (cell) for the content of C. The added bit from the
left is the same as the sign bit.
4- Repeat Steps 2 and 3 n times. (Hint: You have the counter P.)
5- Load the 2n leftmost bits of C to register D, which now holds the multiplication result Z.

Example: Consider the case of X=-6, Y=7, and n=4. The algorithm works as follows:
A=1010 and B=0111
• After S is raised:
➢ R1=1010 0000 0, R2=0110 0000 0, and C=0000 0111 0.
• The loop will be executed as follows:
➢ C_1C_0=10: C=C+R2=0110 0111 0, then C=ashr(C)=0011 0011 1.
➢ C_1C_0=11: C=C=0011 0011 1, then C=ashr(C)=0001 1001 1.
➢ C_1C_0=11: C=C=0001 1001 1, then C=ashr(C)=0000 1100 1.
➢ C_1C_0=01: C=C+R1=1010 1100 1, then C=ashr(C)=1101 0110 0.
• The multiplication result is in D=1101 0110, which corresponds to Z=-42.

(a) (25 points) Derive an algorithmic state machine (ASM) chart representing a circuit that executes
the Booth’s multiplication algorithm. Specify all the states. Clearly indicate the register operations
with proper RTL syntax.
(b) (25 points) Draw a block diagram of the data path unit with all the involved registers, combinational
components, and signals.
(c) (25 points) Design and draw the controller unit with the MUX and D FF method.