Course Syllabus

Synopsys Design Flow Tutorial

Author: V.Sh. Melikyan, Sci.D., Professor

Reviewers: M.K. Martirosyan
E.H. Babayan, Ph.D.

Introduction:
The course program of “Synopsys Design Flow Tutorial” is assigned for undergraduate education on IC
Design specialization and is taught in the 6th semester (3 year’s 2st semester).

Objective:
The main objectives of the course are to study the Synopsys design flow, logic synthesis (Design
Compiler) and physical synthesis (IC Compiler). The course also focuses on generation of test patterns
(TetraMAX), and verification approaches:
- Static timing analysis (PrimeTime)
- Formal verification (Formality)
- Logic (VCS) and SPICE-level (HSpice) simulation
- Physical verification (IC Validator) and layout parasitics extraction (StarRC).

Class Hours:
The course duration is 60 hours, lectures volume is 40 hours and laboratory works are 20 hours.

Homework and Exam:

Grades will be assigned on:
 Labs (30 score)
 Lectures (70 score)
 Final exam.

Prerequisites:
The course program is compiled taking into account that the following courses had been studied
beforehand:
 Informatics
 Electrical Engineering
 Digital Integrated Circuits.
Understanding of the course is the basis for the further specialized subjects destined by the educational
plan of IC Design specialization.

Reference Materials:
To study the course the necessary list of references is given below.
1. V.Taraate. Digital Logic Design Using Verilog: Coding and RTL Synthesis. Springer; 2016
2. A. Reis, R. Drechsler. Advanced Logic Synthesis. Springer. 2017
3. Ch. Roth, L. Kinney. Fundamentals of Logic Design. CL Engineering; 2013
4. H. Bhatnagar. Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler (TM) and
PrimeTime®, 2001

Grading:
This course will be graded according to Professor’s discretion.

Synopsys University Courseware

Copyright © 2017 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan
Course Syllabus

Lectures (40 hours):

Topic 1 (4 hours) - Synopsys Design Flow
 Synopsys design flow. VCS overview. VCS features. DVE Top Level window. Tracing the cause of
failed assertion. RTL and gate signal comparison. Gate level path schematic. Introduction to Design
Compiler. DC and design flow. Design Compiler input and output files. Gate level view after
compile. Design for test. DFT key features. Schematic view after DFT. Formality introduction. Key
concepts. Equivalence checking verification process. Input files of formality. Formality flow
overview. Introduction. ATPG modes. Design flow using DFT Compiler and TetraMAX.TetraMAX
design flow. Steps of running TetraMAX. Test design rule checking. Introduction. PrimeTime inputs
and outputs. Using PrimeTime in physical synthesis flow. Input and output files of IC Compiler. IC
Compiler design flow. Physical design steps . Introduction. Input files of IC Validator. Design
database. Runset file. Schematic netlist. Netlist translation. DRC flow. LVS flow. StarRC overview.
Inputs and outputs of StarRC. Input and output formats of StarRC. StarRC extraction flow. HSPICE
features. Input and output files of HSpice. Synopsys design flow.

Topic 2 (4 hours) – Logic Simulation (VCS)

 VCS overview. Invoking VCS interactive mode. VCS features. DVE top-level window. Tracing the
cause of failed assertion. RTL and gate signal comparison. Gate-level path schematic. User
defined radixes.

Topic 3 (4 hours) – Logic Synthesis (Design Compiler)

 Introduction to Design Compiler. DC and design flow. Basic synthesis flow. DC’s input and output
files. Design Compiler setup. Design view from DC after reading. Design optimization constraints.
Gate-level view after compile. Analyzing design (reports). Visual analyzing design. Design for test.
DFT key features. DFT compiler and the galaxy test automation solution. Scan styles available in
DFT Compiler. Basic scan synthesis flow. Reading the design. Schematic view of design.
Performing RTL test design rule checking. Schematic view after DFT.

Topic 4 (4 hours) – Physical Synthesis (IC Compiler)

 Input and output files of IC compiler. IC compiler design flow. MW library creation. Setup logic
libraries. TluPlus setup. Design importing. Floorplanning. Rectangular rings. Power straps. FP
placement. Core placement and optimization dialog box. FP placement. Script FRAGMENT for
placement. Clock tree synthesize. Clock tree synthesis. Command of CTS. Preroute standard cells.
After prerouting. Routing from the GUI. Routing dialog box. Command for routing. DRC (design rule
checking) box. LVS (layout-versus-schematic) box. Write verilog format box. Write .spef Format
Box. Write .gds format box.

Topic 5 (4 hours) – Static Timing Analysis (PrimeTime)

 Introduction. PrimeTime inputs and outputs. Physical synthesis flow using PrimeTime. PrimeTime
top-level GUI window. Execution script file. Executed script content. Schematic view. Timing
analysis view.

Topic 6 (4 hours) – Formal Verification (Formality)

 Formality introduction. Key concepts. Equivalence checking verification process. Input files of
Formality. Formality flow overview. The main window of Formality GUI. Guidance (loading of
automated setup file). Reference (specifying the reference design). Implementation (specifying the
implementation design). Set up (set up the design). Match (matching compare points). Verify (verify
the designs). Debug.

Topic 7 (4 hours) – Automatic Test Pattern Generation - ATPG (TetraMAX)

 Introduction. ATPG modes. Design flow using DFT compiler and TetraMAX. TetraMAX design
flow. TetraMAX GUI main window. Steps of running TetraMAX. Test design rule checking.
Reading the netlist and verilog library models. Building the ATPG model. Run build model. Test
design rule checking. Analyze the faults. Write patterns.

Synopsys University Courseware

Copyright © 2017 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan
Course Syllabus

Topic 8 (4 hours) – Physical Verification (IC Validator)

 Introduction. Input files of IC validator. Design database. Runset file. Runset file including.
Schematic netlist. Netlist translation. DRC flow. LVS flow.

Topic 9 (4 hours) – Layout Parasitics Extraction (StarRC)

 Introduction. StarRC overview. Inputs and outputs of StarRC. Input and output formats of StarRC.
StarRC extraction flow.

Topic 10 (4 hours) – SPICE-level Simulation of Completed Design (HSpice)

 HSpice features. Input and output files of HSpice. Synopsys design flow. Netlist (.sp,.netl). analyze
type. Measure. Options. Model file. Measure (mt*).

Laboratory Works (20 hours):

Topic 1 (2 hours) – Logic Simulation. VCS
Topic 2 (2 hours) – Logic Synthesis. Design Compiler and Design for Test Compiler
Topic 3 (4 hours) – Physical Design. IC Compiler
Topic 4 (2 hours) – Static Timing Analysis. PrimeTime
Topic 5 (2 hours) – Formal Verification. Formality
Topic 6 (2 hours) – Automated Test Pattern Generation. TetraMAX
Topic 7 (2 hours) – Physical Verification. IC Validator
Topic 8 (2 hours) – Layout Parasitics Extraction. StarRC
Topic 9 (2 hours) – SPICE-level Simulation of Completed Design. HSpice.

Synopsys University Courseware

Copyright © 2017 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan