You are on page 1of 81

A B C D E

1 1

2 2

CFL-H MB Schematic Document


LA-G132P
Rev: 2.0
3 3

2018.11.30

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 1 of 81
A B C D E
5 4 3 2 1

Coffee Lake H Block Diagram


FHD Panel eDP x4 eDP MUX eDP x4
G-SYNC DD
Intel
eDP x4 CHA Memory Bus A-ch DDR4-SO-DIMM X1
P42 P41 Coffee Lake- H6+2 P22
1.2V DDR4 2666MHz
D
HDMI TDP: 45W D

HDMI Conn. Nvdia GPU


P43 N18E-G2 MAX-Q 8G PEG x16 42mm x 28mm
N18E-G2 MAX-Q 8G BGA 1440-Pin CHB Memory Bus B-ch DDR4-SO-DIMM X1
N18E-G1 MAX-P 6G P23
DP N18E-G0 MAX-P 6G 14nm 1.2V DDR4 2666MHz
Mini-DP Conn. P24~39 SPI ROM
P44 0.65mm Ball Pitch
1MB
DDI 1x4 DDI 1x4 P6~13

DMI x4

USB 2.0 x1 Camera 1.0M HD


TBT Thunderbolt PCIe x4
Type-C Conn. Titan Ridge SP P42
(TBT, DP, USB3.1)
USB 3.1 x1
C
P57~58 USB 2.0 x1 USB 3.1 Gen2 Conn. C
P60 USB 2.0 x1 (Upper Side)(Port1)P56
Cannon Lake PCH-H
SPI ROM
I2C 1MB HM370 USB 3.1 x1 USB 3.1 Gen1 Conn.
VBUS POWER Power Delivery
TPS65988 P59 (Upper Side)(Port2)
PCIe x1 USB 2.0 x1
24mm x 25mm P56
NGFF (TYPE E)
USB2.0.x1 BGA 874-Pin
2230 Conn. Sub Board
WLAN/BT4.0 CNVi 0.5mm Ball Pitch
CNVi P55
P49
Novo BTN

NGFF (TYPE M) PCIe x4 USB 3.1 x1


USB3.0 Redriver USB 3.1 Gen1 Conn.
M.2 PCIE SSD(Gen3) USB 2.0 x1
with AOU
P49
B B

LAN HDA Audio Codec Combo Jack


PCIe x1 Realtek ALC3268
RJ45 Conn. P45 P45
Realtek RTL8111H
P50 Int. Array Mic
SATA SATA P42
Redriver HDD Conn.
SPI ROM SPI P54 17"
W25Q64FVSSIQ
16MB P16 I2S Smart AMP Int. Speaker
TAS5766 P46
I2C for 15" only
Touch Pad P14~21 B+
P52
USB 2.0 x1 LPC Bus Line Sub-woofer Subwoofer
USB 2.0 x1 ALC1304 P47 for 17" only
I2C Hall Sensor for 17" only
EC
LED Controller I2C ITE MCU I2C ENE KB9542B P46
A
IT8295 P61 IT8176 P61 A

I2C Thermal
P48
Sensor P51

RGB KBL Int. KBD Security Classification Compal Secret Data Compal Electronics, Inc.
P62 P52 Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
CFL-H 6+2 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 2 of 81
5 4 3 2 1
A B C D E

Board ID Table for AD channel PCH SMBUS Address Table


Vcc
Ra
3.3V +/- 1%
100K +/- 1%
HSIO Port Table(CPU) PCH_SMBUS Net Name Power Rail Device Address (7 bit)
Address (8bit)
Write Read
Board ID /PCB Revision Rb V AD_BID min V AD_BID TYP V AD_BID Max EC AD3 HSIO Port Device PCIE CLK&CLKREQ HPD
0 --> 0.1 0 0x00 - 0x13 PCH_SMBCLK JDIMM1 0X50 0XA0 0XA1
0V 0.300 V PEG DGPU (DIS) CLK4 & & CLKREQ#4 PCH_SMBDATA +3V_PCH_PRIM
1 --> 0.2 12K +/- 1% 0.347 V 0.354 V 0.36 V 0x14 - 0x1E JDIMM3 0X52 0XA4 0XA3
2 --> 0.3 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 DDI1 NA NA
3 --> 0.4 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 PCH_SML0CLK
DDI2 NA NA PCH_SML0DATA +3VS NA
4 --> 0.5 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A
1
5 --> 0.6 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 DDI3 NA NA 1

6 --> 0.7 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54 PCH_SML1CLK EC TBC TBC TBC
eDP Embedded Display EDP_HPD PCH_SML1DATA +3VS
7 --> 0.8 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
8 --> 0.9 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76
9 --> 1.0 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87
Power State EC SMBUS Address Table
10 --> 1.1 130K +/- 1% 1.849 V 1.865 V 1.881V 0x88 - 0x96 Address (8bit)
SIGNAL EC_SMBUS Port Power Rail Device Address (7 bit)
11 --> 1.2 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock Write Read
12 --> 1.3 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF
240K +/- 1% 2.316V 2.329V 2.343V 0xB0 - 0xB7
S0 (Full ON) HIGH HIGH HIGH ON ON ON ON SMBUS Port1 BAT 0x16 TBC TBC
13 --> 1.4 EC_SMB_CK1 +3VLP_EC
14 --> 1.5 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xBF S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF CHGR 0x09 0x12 0x13
EC_SMB_DA1
15 --> 1.6 330K +/- 1% 2.521 V 2.533V 2.544 V 0xC0 - 0xC9 TBT Reserved TBC TBC
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
16 --> 1.7 430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4
17 --> 1.8 560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD S5 (Sof t OFF) LOW LOW LOW ON OFF OFF OFF
Current Mon 1 0x41 0x82 0x83
18 --> 1.9 750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0
NC 3.000 V 3.000 V 0xF1 - 0xFF Current Mon 2 0x40 0x80 0x81
19 --> 2.0
SMBUS Port2 PCH TBC
BOM Structure Table (1/2) HSIO Port Table(PCH) HM370 USB2.0 Port Table EC_SMB_CK2
EC_SMB_DA2
+3VS GPU 0x9E/0x9F TBC TBC
USB2 Function Smart Amp 0x4C 0x98 0x99
Funct i on Stuff Note HSIO Port Capable USB3.0 PCIE SATA Device PCIE CLK&CLKREQ NOTE
UMA@ 1 USB3.1 PORT 1 THERMAL 0x4D 0x9A 0x9B
Unit SKU 0 USB3.1_1(OTG)
DIS@ 1 USB3.1 PORT 1 Lef t Back USB3.1 re-driver
2 USB3.1 PORT 2 0x29 0x52 0x53
2 15@ 1 USB3.1_2 USB3.1 PORT 2 2
Project SKU 2 Right Back
0X3F
17@ 3 SMBUS Port4 G-sensor 0x1F 0x3E
2 USB3.1_3 USB3.1 PORT 3 USB3.1 PORT 3
CPU1@ i5-8300H-R1 3 Right Fornt EC_SMB_CK4 +3VS
CPU2@ i7-8750H-R1 4 Anti-ghost IT8176 EC_SMB_DA4 Ant i- ghost TBC
3 USB3.1_4 4
CFL-H SKU CPU3@ i5-8300H 5 TBT TYPE-C
4 USB3.1_5 5
CPU4@ i7-8750H
6 LED Controller IT8295
I2C Address Table
CPU5@ i5-8300H-R3 5 USB3.1_6 Address (8bit)
6 I2C Port Power Rail Device Address (7 bit)
CPU6@ i7-8750H-R3 7 Write Read
6 USB3.1_7 Camera
N18G0@ 7
N18G1@ 8 I2C_0_SCL
DGPU SKU 7 USB3.1_8 8 I2C_0_SDA +3VS
N18G2@ 9 TBC TBC TBC
N18G3@ 8 Tobii EC KB9542
10 I2C_1_SCL
9 I2C_1_SDA +3VS Touch Pad
PCH1@ SR40B-R1 0x15 TBC TBC
11
PCH SKU HM370 PCH2@ QNYF 10
PCH3@ SR40B-R3 12
GPU1@ 2060-G1-R1
11
13
Voltage Rails
12 Power Plane Descript i on S0 S0ix S3 S4/S5 DS3
N18 x SKU GPU2@ 2070-G2-R1
14 WLAN+BT NGFF VIN Adapter power supply N/A N/A N/A N/A N/A
GPU3@ 2080-G3-R1 13 BATT+ Bat t er y po wer s uppl y N/A N/A N/A N/A N/A
GPU4@ 2060-G1-R3
14 PCIE_9 / GbE +19VB AC or bat t er y po wer r ail f or po wer ci rc ui t N/A N/A N/A N/A N/A
GPU5@ 2070-G2-R3 9
+VCC_CORE Core voltage for CPU ON OFF OFF OFF OFF
3
GPU6@ 2080-G3-R3 15 PCIE_10
3
10 +VCC_SA System Agent voltage Supply ON OFF OFF OFF OFF
M8G@ X7678038L51
16 PCIE_11 / SATA_0A HDD +VCC_GT/+VCC_GTX Sliced graphics power rail ON OFF OFF OFF OFF
S8G@ X7678038L52 11 0
VRAM 8G +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF OFF OFF
H8G@ X7678038L53 17 PCIE_12 / GbE / SATA_1A 12 1 +VCC_EOPIO/+VCC_EDRAM Processor EOPIO/EDRAM supply ON OFF OFF OFF OFF
M8G@ X7678038L56
18 PCIE_13 / GbE / SATA_0B LAN CLK2 & & CLKREQ#2 +1.05VALW System +1.0V power rail ON ON ON ON* OFF
VRAM 6G S8G@ X7678038L57 13 0
+0.95VS_VCCIO +1.0VS IO power rail ON ON OFF OFF OFF
H8G@ X7678038L58 19 PCIE_14 / SATA_1B WLAN+BT NGFF CLK3 & & CLKREQ#3
14 1 +1.05V_VCCMPHY +1.0V power for PCH MODPHY rails ON/OFF ON/OFF ON/OFF ON/OFF OFF
20 PCIE_15 / SATA_2 +0.95VS_DGPU +0.95VS power rail for GPU ON OFF OFF OFF OFF
EC 15 2
+1.2V_VDDQ DDR4 +1.2V power rail ON ON ON OFF ON
21 PCIE_16 / SATA_3 16 3 +1.5VS_MEM_GFX +1.5VS power rail for GPU/VRAM ON OFF OFF OFF OFF
ESPI@
22 PCIE_17 / SATA_4 +1.8VALW System +1.8V power rail ON ON ON ON* OFF
eSPI I/F LPC@ 17 4
Support +1.8VS System +1.8VS power rail ON ON OFF OFF OFF
CMC@ 23 PCIE_18 / SATA_5
Debug 18 5 CLK1 & & CLKREQ#1 SATA +1.8VGS +1.8VS power rail for GPU ON OFF OFF OFF OFF
DCI@ NGFF SSD funct i on on
24 PCIE_19 +2.5V DDR4 +2.5Vpp power rail ON ON ON OFF ON
GSYNC@ 19 SATA#4
Panel SKU +3VALW System +3VALW always on power rail ON ON ON ON* ON
NOGSYNC@ 25 PCIE_20 20 +3VALW +3VALW power for PCH suspend rails ON ON ON ON* ON
Intel TBT TR TBT@
26 PCIE_21 +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON* ON
Intel CNVi CNVI@ 21
+3VLP +19VB to +3VLP power rail for suspend powerON ON ON ON ON
8111H_SW@ 27 PCIE_22
LAN Mode 22 Thunderbolt +3VS System +3VS power rail ON ON OFF OFF OFF
8111H_LDO@ CLK0 & & CLKREQ#0
28 PCIE_23 Intel Titan Ridge SP +3VGS +3VS power rail for GPU ON OFF OFF OFF OFF
FIN1@ Y730 FIN 23
4 FIN FPC +5VALW System +5VALW power rail ON ON ON ON* ON 4
FIN2@ Y740 FIN 29 PCIE_24 24 +5VS System +5VS power rail ON ON OFF OFF OFF
ON@ NCP45491
OVRM +3VL_RTC RTC power ON ON ON ON ON
UPI@ US5650PQKI
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

ME Connector ME@
EMI@ Security Classification Compal Secret Data Compal Electronics, Inc.
EMI Components @EMI@ 2018/7/31 2018/7/31 Title
EMI15@ Issued Date Deciphered Date

ESD Components ESD@ @ESD@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
RF Components RF@ @RF@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 3 of 81
A B C D E
A B C D E

IMVP8 VR
NCP81215MNTXG
(PU8)
NCP302045MNTXG x4
+19VB_CPU (PUZ2/PUZ4/PUZ5/PUZ6) 128000mA
+VCC_CORE +CHGRTC_R
JRTC1
+RTCVCC
+19VB_CPU NCP302045MNTXG x1 32000mA +3VLP
(PUZ3) +VCCGT RT6575DGQW
(PU401) +CHGRTC
DH1

+19VB_CPU NCP81253MNTBG 11100mA


(PU27) +VCCSA R189 +3VALW_EC
EN:VR_ON
1 1

7430mA 3300mA
+1.2V RC166 +1.2V_VCCPLL_OC
+19VB_1.2VP RT8207PGQW (PJ501/PJ502)
(PU501)
306mA
RH88 +1.05V_BCLKPLL2
1500mA +1.2V_U3RD
+0.6VS R621
(PJ503)
S5 EN:SYSON
S3 EN:DDR_VTT_PG_CTRL RH87 +1.05V_OC

RH86 +1.05V_OCPLL1
VIN_+0.95VS_VCCIOP SY8286RAC 6400mA +0.95VS_VCCIO
(PU701) (PJ702) 60mA
+1.05V_VCCST RH85
EN:SUSP#&PM_SLP_S3# +1.05V_SRC

+19VB_1.05VALW SY8288RAC 5200mA EM5209VF 150mA RH83 +1.05V_XTAL


+1.05VALW (UC5) +1.05V_VCCSTU +1.05V_VCCSFR
(PU702)
(PJ704)
EN:SYSON
EN:+1.8V_PG
RH61 +1.05V_VCCAMPHYPLL
EM5201V 20mA
(UC3) +1.05VS_VCCSTG
EN:SUSP#
RH84 +1.05V_VCCAZPLL
CHARGER
ISL88739HRZ-T RC74
+19VB +1.05V_XDP
(PU301)
RH59 +1.05V_VCCCLPLLEBB

RH55
+12.6V_BATT +1.05V_PCH_PRIM
2
RH58 +1.05V_VCCUSB 2

RH54
BATTERY +1.05V_VCCMPHY RH57 +1.05V_CNV_HVLDO

RH56 +1.05V_FUSE

RV347 +LEDVDD
RH119 +1.05V_FHV1

RH120 +1.05V_FHV0

G9661MF11U +2.5VP
(PU502) RH161 +1.8V_PRIM
(PJ605) RA13 +1.8VS_AUDIO
EN:PM_SLP_S4#

SY8032ABC EM5209VF
+19VB_3/5V +1.8VALW (UC5) +1.8VS RC72
RT6575DGQW (PU601) +1.8VS_3VS_PGPPA
(PU401) +3VALW (PJ601)
EN:3V/5VALW_PG
(PJ403)
EN:EC_ON EM5209VF +1V8_AON
G9661MF11U (UG1) +1V8_MAIN 'RTPM4 +1.8VS_TPM
(PU1302) +1.0VS_DGPUP
(PJ1303)

RH162
+3VALW_DSW
RC73
3 +1.8VS_3VS_PGPPA 3

RL18
+3V_LAN
RS2
+3VS_SSD
QW10
+3V_WLAN

R622
+3VS_U3RD

EN:SD_PWR_EN

+3VS UV18 +3VS_DP


EM5209VF (JP3V)
(U21)
G5016KD1U
(UV20) +LCDVDD_CONN
AP2330W-7
+5VS (UV14) +HDMI_5V_OUT EN:PCH_ENVDD
(JP5V)
EN:SUSP#
RTH3
+3VS_THM
G524B2T11U RHD3
(U47) +5VALW_USB1 +5VS_HDD
EN:USB_PWR_EN#
+5VALW
(PJ401 G524B2T11U +5VALW_USB2
PJ405) (U46)
EN:USB_CHG_EN

TPS2544RTER
(U12) +5V_CHGUSB
EN:USB_PWR_EN#

VR
RT8813DGQW
www.teknisi-indonesia.com
4
(PU801) 4

AON6962 x2
+19VB_VGA_CORE (PQ801/PQ802) +VGA_CORE

EN:VGA_CORE_EN

PU802+PQ1303 +VGA_CORE

+19VB_+1.5VS_VRAMP RT8237EZQW 11000mA


Security Classification Compal Secret Data Compal Electronics, Inc.
(PU1301) +1.5VGS Issued Date 2018/7/31 2018/7/31 Title
Deciphered Date
(PJ1301)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
EN:1.5VSDGPU_PWR_EN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 4 of 81
A B C D E
A B C D E

[DDX03 PWR Sequence_CFL-H 6+2_DDR4]

G3->S0 S0->S3 S3 ->S0 S0->S5


+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
PCH_RTCRST# PCH_RTCRST#

+19VB +19VB

+3VLP/+5VLP +3VLP/+5VLP

1 EC_ON EC_ON 1
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#
SLP_SUS# is ignored in Non-DSx systems
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN(SLP_SUS#)

+1.8VALW +1.8VALW
tPCH06_Min : 200 us
+1.05VALW +1.05VALW
tPCH34_Max : 20 ms
+1.05V_PCH_PRIM +1.05V_PCH_PRIM

+1.05V_VCCMPHY +1.05V_VCCMPHY

SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
AC_PRESENT
AC_PRESENT

ON/OFF ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST# PBTN_OUT#
2 2

PM_SLP_S0# PM_SLP_S0#

PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us(DSx); 95 ms(Non-DSx)
ESPI_RST# ESPI_RST#

PM_SLP_S4# PM_SLP_S4#

SYSON SYSON

+2.5V +2.5V

+1.05V_VCCST/VCCPLL +1.05V_VCCST/VCCPLL

+1.2V_VDDQ +1.2V_VDDQ

PM_SLP_S3# PM_SLP_S3#

SUSP# SUSP#
tCPU04 Min : 100 ns
+1.05VS_VCCSTG/+1.2V_VCCPLL_OC +1.05VS_VCCSTG/+1.2V_VCCPLL_OC
tCPU10 Min : 1 ms
+0.95VS_VCCIO +0.95VS_VCCIO

3 3
T <=10msec
+5VS/+3VS/+1.8VS +5VS/+3VS/+1.5VS/+1.05VS
T <= 30msec
EC_VCCST_PG EC_VCCST_PG

T <= 30msec
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
+0.6VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA

+VCC_CORE +VCC_CORE

+VCC_GT +VCC_GT

VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK

H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK

4 4
SUS_STAT# SUS_STAT#

PCH_PLTRST#
PCH_PLTRST#

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 5 of 81
A B C D E
A B C D E

1 1

CFL-H
UC1D

K36 D29
DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 [41]
K37 E29
DDI1_TXN_0 EDP_TXN_0 EDP_TXN0 [41]
J35 F28
DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 [41]
J34 E28
DDI1_TXN_1 EDP_TXN_1 EDP_TXN1 [41]
H37 A29
EDP_TXP2 [41]
H36 DDI1_TXP_2
DDI1_TXN_2
EDP_TXP_2
EDP_TXN_2
B29
EDP_TXN2 [41]
eDP
J37 C28
DDI1_TXP_3 EDP_TXP_3 EDP_TXP3 [41]
J38 B28
DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 [41]
D27 C26 EDP_AUXP [41]
E27 DDI1_AUXP EDP_AUXP B26
DDI1_AUXN EDP_AUXN EDP_AUXN [41]
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 EDP_DISP_UTIL +0.95VS_VCCIO
DDI2_TXP_1 EDP_DISP_UTIL TC1 TP@
G38
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 DP_RCOMP RC1 1 2 24.9_0402_1%
E37 DDI2_TXN_2 DISP_RCOMP
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
DDI2_TXN_3 Max Trace Length: 600 mil
2 2
F26
E26 DDI2_AUXP
DDI2_AUXN
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 CPU_DISPA_BCLK_R
PROC_AUDIO_CLK CPU_DISPA_BCLK_R [18]
A27 G25 CPU_DISPA_SDO_R
DDI3_AUXP PROC_AUDIO_SDI CPU_DISPA_SDO_R [18]
B27 G29 CPU_DISPA_SDI RC2 2 1 20_0402_5% CPU_DISPA_SDI_R
DDI3_AUXN PROC_AUDIO_SDO
4 of 13 CPU_DISPA_SDI_R [18]

CFL-H_BGA1440
@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
CFL-H(1/8)DDI/eDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 6 of 81
A B C D E
A B C D E

CHANNEL-A
Interleaved Memory
UC1A
CFL-H

DDR CHANNEL A
1 [22] DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK0 [22]
DDR_A_D1 BT6 AG2 DDR_A_CLK#0 DDR_A_CLK#0 [22]
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK1 [22]
DDR_A_D3 BR3 AK1 DDR_A_CLK#1 DDR_A_CLK#1 [22]
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE0 [22]
DDR_A_D10 BL2 AT2 DDR_A_CKE1
DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR_A_CKE1 [22]
DDR_A_D11 BM1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#0 [22]
DDR_A_D15 BK2 AE2 DDR_A_CS#1
DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR_A_CS#1 [22]
DDR_A_D16 BG4 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT0 [22]
DDR_A_D20 BG2 AE4 DDR_A_ODT1
DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR_A_ODT1 [22]
DDR_A_D21 BG1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA0 [22]
DDR_A_D25 BD1 AH1 DDR_A_BA1
DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 [22]
DDR_A_D26 BC4 AU1 DDR_A_BG0
DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 [22]
2 DDR_A_D27 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA16_RAS# [22]
DDR_A_D29 BD4 AG4 DDR_A_MA14_WE#
DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA14_WE# [22]
DDR_A_D30 BC1 AD1 DDR_A_MA15_CAS#
DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# [22]
DDR_A_D31 BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA0 [22]
DDR_A_D33 AB2 AP4 DDR_A_MA1
DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 DDR_A_MA1 [22]
DDR_A_D34 AA4 AN4 DDR_A_MA2
DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 DDR_A_MA2 [22]
DDR_A_D35 AA5 AP5 DDR_A_MA3
DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR_A_MA3 [22]
DDR_A_D36 AB5 AP2 DDR_A_MA4
DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA4 [22]
DDR_A_D37 AB4 AP1 DDR_A_MA5
DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR_A_MA5 [22]
DDR_A_D38 AA2 AP3 DDR_A_MA6
DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA6 [22]
DDR_A_D39 AA1 AN1 DDR_A_MA7
DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 DDR_A_MA7 [22]
DDR_A_D40 V5 AN3 DDR_A_MA8
DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA8 [22]
DDR_A_D41 V2 AT4 DDR_A_MA9
DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 DDR_A_MA9 [22]
DDR_A_D42 U1 AH2 DDR_A_MA10
DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA10 [22]
DDR_A_D43 U2 AN2 DDR_A_MA11
DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 DDR_A_MA11 [22]
DDR_A_D44 V1 AU4 DDR_A_MA12
DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR_A_MA12 [22]
DDR_A_D45 V4 AE3 DDR_A_MA13
DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 DDR_A_MA13 [22]
DDR_A_D46 U5 AU2 DDR_A_BG1
DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 [22]
DDR_A_D47 U4 AU3 DDR_A_ACT#
DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# [22]
DDR_A_D48 R2
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_PAR [22]
DDR_A_D50 R4 AU5 DDR_A_ALERT#
DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# [22]
DDR_A_D51 P4
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 [22]
DDR_A_D54 R1 BL3 DDR_A_DQS#1
DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#1 [22]
DDR_A_D55 P1 BG3 DDR_A_DQS#2
3 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#2 [22] 3
DDR_A_D56 M4 BD3 DDR_A_DQS#3
DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR_A_DQS#3 [22]
DDR_A_D57 M1 AA3 DDR_A_DQS#4
DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR_A_DQS#4 [22]
DDR_A_D58 L4 U3 DDR_A_DQS#5
DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 DDR_A_DQS#5 [22]
DDR_A_D59 L2 P3 DDR_A_DQS#6
DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR_A_DQS#6 [22]
DDR_A_D60 M5 L3 DDR_A_DQS#7
DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_A_DQS#7 [22]
DDR_A_D61 M2
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS0 [22]
DDR_A_D63 L1 BK3 DDR_A_DQS1
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR_A_DQS1 [22]
BF3 DDR_A_DQS2 [22]
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS2
LP3/DDR4 BC3 DDR_A_DQS3
DDR0_DQSP_3/DDR0_DQSP_5 DDR_A_DQS3 [22]
BA2 AB3 DDR_A_DQS4 [22]
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS4
BA1 V3 DDR_A_DQS5
NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR_A_DQS5 [22]
AY4 R3 DDR_A_DQS6 [22]
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS6
AY5 M3 DDR_A_DQS7 [22]
NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 DDR_A_DQS7
BA5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(2/8)DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 7 of 81
A B C D E
A B C D E

CHANNEL-B
Interleaved Memory
UC1B
CFL-H

[23] DDR_B_D[0..63] DDR CHANNEL B


1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK0 [23]
DDR_B_D1 BR11 AN9 DDR_B_CLK#0 DDR_B_CLK#0 [23]
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1
DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK1 [23]
DDR_B_D3 BR8 AM8 DDR_B_CLK#1 DDR_B_CLK#1 [23]
DDR_B_D4 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE0 [23]
DDR_B_D10 BL8 AT10 DDR_B_CKE1
DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE1 [23]
DDR_B_D11 BJ8 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#0 [23]
DDR_B_D15 BJ7 AE7 DDR_B_CS#1
DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 DDR_B_CS#1 [23]
DDR_B_D16 BG11 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT0 [23]
DDR_B_D20 BF11 AE8 DDR_B_ODT1
DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 DDR_B_ODT1 [23]
DDR_B_D21 BF10 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16_RAS# [23]
DDR_B_D25 BC11 AH11 DDR_B_MA14_WE#
DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA14_WE# [23]
DDR_B_D26 BB8 AF8 DDR_B_MA15_CAS#
DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# [23]
2 DDR_B_D27 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA0 [23]
DDR_B_D29 BB10 AH9 DDR_B_BA1
DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 DDR_B_BA1 [23]
DDR_B_D30 BC7 AR9 DDR_B_BG0
DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 [23]
DDR_B_D31 BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA0 [23]
DDR_B_D33 AA10 AK6 DDR_B_MA1
DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA1 [23]
DDR_B_D34 AC11 AK5 DDR_B_MA2
DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 DDR_B_MA2 [23]
DDR_B_D35 AC10 AL5 DDR_B_MA3
DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 DDR_B_MA3 [23]
DDR_B_D36 AA7 AL6 DDR_B_MA4
DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA4 [23]
DDR_B_D37 AA8 AM6 DDR_B_MA5
DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA5 [23]
DDR_B_D38 AC8 AN7 DDR_B_MA6
DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA6 [23]
DDR_B_D39 AC7 AN10 DDR_B_MA7
DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7 DDR_B_MA7 [23]
DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 DDR_B_MA8 [23]
DDR_B_D41 W7 AR11 DDR_B_MA9
DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 DDR_B_MA9 [23]
DDR_B_D42 V10 AH7 DDR_B_MA10
DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 DDR_B_MA10 [23]
DDR_B_D43 V11 AN11 DDR_B_MA11
DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 DDR_B_MA11 [23]
DDR_B_D44 W11 AR10 DDR_B_MA12
DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 DDR_B_MA12 [23]
DDR_B_D45 W10 AF9 DDR_B_MA13
DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 DDR_B_MA13 [23]
DDR_B_D46 V7 AR7 DDR_B_BG1
DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_BG1 [23]
DDR_B_D47 V8 AT9 DDR_B_ACT#
DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# [23]
DDR_B_D48 R11
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_PAR [23]
DDR_B_D50 P7 AR8 DDR_B_ALERT#
DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# [23]
DDR_B_D51 R8
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#0 [23]
DDR_B_D54 R7 BL9 DDR_B_DQS#1
3 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR_B_DQS#1 [23] 3
DDR_B_D55 P8 BG9 DDR_B_DQS#2
DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 DDR_B_DQS#2 [23]
DDR_B_D56 L11 BC9 DDR_B_DQS#3
DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR_B_DQS#3 [23]
DDR_B_D57 M11 AC9 DDR_B_DQS#4
DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR_B_DQS#4 [23]
DDR_B_D58 L7 W9 DDR_B_DQS#5
DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 DDR_B_DQS#5 [23]
DDR_B_D59 M8 R9 DDR_B_DQS#6
DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS#6 [23]
DDR_B_D60 L10 M9 DDR_B_DQS#7
DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS#7 [23]
DDR_B_D61 M10
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS0 [23]
DDR_B_D63 L8 BJ9 DDR_B_DQS1
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR_B_DQS1 [23]
BF9 DDR_B_DQS2
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS2 [23]
AW11 LP3/DDR4 BB9 DDR_B_DQS3
NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 DDR_B_DQS3 [23]
AY11 AA9 DDR_B_DQS4
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS4 [23]
AY8 V9 DDR_B_DQS5
NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 DDR_B_DQS5 [23]
AW8 P9 DDR_B_DQS6
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS6 [23]
AY10 L9 DDR_B_DQS7
NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS7 [23]
AW10
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9 For ECC DIMM
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA


+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13 +0.6V_A_VREFDQ
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ TP@ TC286
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
4 @ 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
CFL-H(3/8)DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 8 of 81
A B C D E
A B C D E

PEG&DMI
1 1

To DGPU
To DGPU
CFL-H (reversed)
(reversed) UC1C
[24] PEG_CRX_GTX_P15 CC197 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P15 E25 B25 PEG_CTX_GRX_P15 CC181 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P15
PEG_CTX_C_GRX_P15 [24]
CC198 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PEG_CTX_GRX_N15 CC182 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N15
[24] PEG_CRX_GTX_N15 PEG_RXN_0 PEG_TXN_0 PEG_CTX_C_GRX_N15 [24]

[24] PEG_CRX_GTX_P14 CC199 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P14 E24 B24 PEG_CTX_GRX_P14 CC183 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P14
PEG_CTX_C_GRX_P14 [24]
CC200 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PEG_CTX_GRX_N14 CC184 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N14
[24] PEG_CRX_GTX_N14 PEG_RXN_1 PEG_TXN_1 PEG_CTX_C_GRX_N14 [24]

[24] PEG_CRX_GTX_P13 CC202 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P13 E23 B23 PEG_CTX_GRX_P13 CC185 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P13 PEG_CTX_C_GRX_P13 [24]
CC201 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N13 D23 PEG_RXP_2 PEG_TXP_2 A23 PEG_CTX_GRX_N13 CC186 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N13
[24] PEG_CRX_GTX_N13 PEG_RXN_2 PEG_TXN_2 PEG_CTX_C_GRX_N13 [24]

[24] PEG_CRX_GTX_P12 CC204 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P12 E22 B22 PEG_CTX_GRX_P12 CC187 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P12 PEG_CTX_C_GRX_P12 [24]
CC203 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PEG_CTX_GRX_N12 CC188 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N12
[24] PEG_CRX_GTX_N12 PEG_RXN_3 PEG_TXN_3 PEG_CTX_C_GRX_N12 [24]

[24] PEG_CRX_GTX_P11 CC206 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P11 E21 B21 PEG_CTX_GRX_P11 CC189 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_P11 [24]
CC208 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_CTX_GRX_N11 CC191 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N11
[24] PEG_CRX_GTX_N11 PEG_RXN_4 PEG_TXN_4 PEG_CTX_C_GRX_N11 [24]

[24] PEG_CRX_GTX_P10 CC205 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P10 E20 B20 PEG_CTX_GRX_P10 CC190 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P10
PEG_CTX_C_GRX_P10 [24]
CC207 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PEG_CTX_GRX_N10 CC192 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N10
[24] PEG_CRX_GTX_N10 PEG_RXN_5 PEG_TXN_5 PEG_CTX_C_GRX_N10 [24]

[24] PEG_CRX_GTX_P9 CC209 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P9 E19 B19 PEG_CTX_GRX_P9 CC193 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P9
PEG_CTX_C_GRX_P9 [24]
CC210 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PEG_CTX_GRX_N9 CC195 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N9
[24] PEG_CRX_GTX_N9 PEG_RXN_6 PEG_TXN_6 PEG_CTX_C_GRX_N9 [24]
2 2

[24] PEG_CRX_GTX_P8 CC211 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P8 E18 B18 PEG_CTX_GRX_P8 CC194 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P8
PEG_CTX_C_GRX_P8 [24]
CC212 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PEG_CTX_GRX_N8 CC196 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N8
[24] PEG_CRX_GTX_N8 PEG_RXN_7 PEG_TXN_7 PEG_CTX_C_GRX_N8 [24]

[24] PEG_CRX_GTX_P7 CC213 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P7 D17 A17 PEG_CTX_GRX_P7 CC1 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_P7 [24]
CC214 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_CTX_GRX_N7 CC2 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N7
[24] PEG_CRX_GTX_N7 PEG_RXN_8 PEG_TXN_8 PEG_CTX_C_GRX_N7 [24]

[24] PEG_CRX_GTX_P6 CC215 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P6 F16 C16 PEG_CTX_GRX_P6 CC3 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_P6 [24]
CC216 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PEG_CTX_GRX_N6 CC4 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N6
[24] PEG_CRX_GTX_N6 PEG_RXN_9 PEG_TXN_9 PEG_CTX_C_GRX_N6 [24]

[24] PEG_CRX_GTX_P5 CC217 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P5 D15 A15 PEG_CTX_GRX_P5 CC5 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P5
PEG_CTX_C_GRX_P5 [24]
CC219 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PEG_CTX_GRX_N5 CC6 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N5
[24] PEG_CRX_GTX_N5 PEG_RXN_10 PEG_TXN_10 PEG_CTX_C_GRX_N5 [24]

[24] PEG_CRX_GTX_P4 CC218 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P4 F14 C14 PEG_CTX_GRX_P4 CC7 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P4
PEG_CTX_C_GRX_P4 [24]
CC220 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PEG_CTX_GRX_N4 CC8 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N4
[24] PEG_CRX_GTX_N4 PEG_RXN_11 PEG_TXN_11 PEG_CTX_C_GRX_N4 [24]

[24] PEG_CRX_GTX_P3 CC222 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P3 D13 A13 PEG_CTX_GRX_P3 CC9 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_P3 [24]
CC224 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PEG_CTX_GRX_N3 CC10 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N3
[24] PEG_CRX_GTX_N3 PEG_RXN_12 PEG_TXN_12 PEG_CTX_C_GRX_N3 [24]

[24] PEG_CRX_GTX_P2 CC221 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P2 F12 C12 PEG_CTX_GRX_P2 CC11 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_P2 [24]
CC223 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PEG_CTX_GRX_N2 CC12 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N2
[24] PEG_CRX_GTX_N2 PEG_RXN_13 PEG_TXN_13 PEG_CTX_C_GRX_N2 [24]

[24] PEG_CRX_GTX_P1 CC225 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P1 D11 A11 PEG_CTX_GRX_P1 CC13 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_P1 [24]
CC227 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PEG_CTX_GRX_N1 CC14 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N1
[24] PEG_CRX_GTX_N1 PEG_RXN_14 PEG_TXN_14 PEG_CTX_C_GRX_N1 [24]
CC226 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_P0 F10 C10 PEG_CTX_GRX_P0 CC15 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_P0
[24] PEG_CRX_GTX_P0 PEG_RXP_15 PEG_TXP_15 PEG_CTX_C_GRX_P0 [24]
CC228 DIS@ 1 2 0.22U_0201_6.3V PEG_CRX_C_GTX_N0 E10 B10 PEG_CTX_GRX_N0 CC16 DIS@ 1 2 0.22U_0201_6.3V PEG_CTX_C_GRX_N0
[24] PEG_CRX_GTX_N0 PEG_RXN_15 PEG_TXN_15 PEG_CTX_C_GRX_N0 [24]
+0.95VS_VCCIO
3 RC9 1 2 24.9_0402_1% PEG_RCOMP G2 3
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil

DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
[14] DMI_CRX_PTX_P0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_P0 [14]
DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0
[14] DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 [14]
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
[14] DMI_CRX_PTX_P1 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_P1 [14]
DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1
[14] DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 [14]
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
[14] DMI_CRX_PTX_P2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_P2 [14]
DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2
[14] DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 [14]
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
[14] DMI_CRX_PTX_P3 DMI_RXP_3 3 OF 13 DMI_TXP_3
DMI_CTX_PRX_P3 [14]
DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3
[14] DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 [14]
CFL-H_BGA1440
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
PEG/DMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 9 of 81
A B C D E
A B C D E

CFL-H
UC1E

[15] PCH_CPU_BCLK_P PCH_CPU_BCLK_P B31 BN25 CFG0


PCH_CPU_BCLK_N A32 BCLKP CFG_0 BN27
[15] PCH_CPU_BCLK_N BCLKN CFG_1 BN26 CFG2
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28
[15] PCH_CPU_PCIBCLK_P PCI_BCLKP CFG_3
[15] PCH_CPU_PCIBCLK_N PCH_CPU_PCIBCLK_N C36 BR20 CFG4
PCI_BCLKN CFG_4 BM20 CFG5
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
[15] PCH_CPU_24M_CLK_P CLK24P CFG_6
[15] PCH_CPU_24M_CLK_N PCH_CPU_24M_CLK_N D31 BP20 CFG7
@RF@ CLK24N CFG_7 BR23
10P_0402_50V8J 2 1 CC155 CPU_SVID_CLK CFG_8 BR22
1 1
CFG_9 BT23
03/14 From RF Team Request CFG_10 BT22
CFG_11 BM19
CFG_12 BR19
CFG_13 BP19
CPU_SVID_ALERT# BH31 CFG_14 BT19
ESD@ CPU_SVID_CLK BH32 VIDALERT# CFG_15
100P_0402_50V8J 1 2 CC156 VCCST_PWRGD CPU_SVID_DAT BH29 VIDSCK BN23
Sensitive H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23
ESD@ PROCHOT# CFG_16 BP22
100P_0402_50V8J 1 2 CC157 H_CPUPWRGD CFG_19
DDR_PG_CTRL BT13 BN22 The CFG signals have a default value of '1' if not terminated on the board.
DDR_VTT_CNTL CFG_18 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
Near CPU side 1 = (Default) Normal Operation;
From ESD Team Request BR27 XDP_BPM#0 TC98 TP@
0 = Stall.
BPM#_0 BT27 XDP_BPM#1 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
BPM#_1 TC99 TP@
BM31 XDP_BPM#2 TC101TP@ 1 = Normal operation
EC_VCCST_PG H13 BPM#_2 BT30 XDP_BPM#3 0 = Lane numbers reversed.
Sensitive VCCST_PWRGD BPM#_3 TC100TP@
CFG[4]: eDP enable:
H_CPUPWRGD BT31 1 = Disabled.
[18]H_CPUPWRGD PROCPWRGD 0 = Enabled.
H_PLTRST_CPU# BP35 BT28 CPU_XDP_TDO
[17]H_PLTRST_CPU# RESET# PROC_TDO CPU_XDP_TDO [18]
H_PM_SYNC_R BM34 BL32 CPU_XDP_TDI CFG[6:5]: PCI Express* Bifurcation:
[17]H_PM_SYNC_R PM_SYNC PROC_TDI CPU_XDP_TDI [18]
H_PM_DOWN_R RC22 1 2 20_0402_5% H_PM_DOWN BP31 BP28 CPU_XDP_TMS 00 = 1 x8, 2 x4 PCI Express*
[17] H_PM_DOWN_R PM_DOWN PROC_TMS CPU_XDP_TMS [18] 01 = reserved
BT34 BR28 CPU_XDP_TCK0
[17,48] H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 [18] 10 = 2 x8 PCI Express*
RC45 1 @ 2 0_0402_5% J31 11 = 1 x16 PCI Express*
[17] PCH_THERMTRIP#_R THERMTRIP# BP30 CPU_XDP_TRST#
pulled high in PCH side SKTOCC# BR33 PROC_TRST# BL30 XDP_PREQ# CFG[7]: PEG Training:
TP@ TC102 SKTOCC# PROC_PREQ# XDP_PREQ# [21]
TP@ TC97 PROC_SELECT# BN1 BP27 XDP_PRDY# 1 = (default) PEG Train immediately following RESET# de assertion.
PROC_SELECT# PROC_PRDY# XDP_PRDY# [21] 0 = PEG Wait for BIOS for training.
2 TP@ TC96 CATERR# BM30 *CFG Pin Use CMC debug on DDX03 R02 Schematic. 2
+1.05V_VCCST CATERR# CFG_RCOMP RC19
BT25 1 2 49.9_0402_1%
AT13 CFG_RCOMP
AW13 ZVM#
MSM# Trace Width/Space: 4 mil/ 12 mil
1

AU13 Max Trace Length: 600 mil XDP_PREQ#


TP@ TC94 RSVD1 T37 @
RC20 TP@ TC95 AY13 XDP_PRDY# T394 @
RSVD2
1K_0402_5%
5 OF 13
2

CFL-H_BGA1440
VCCST_PWRGD RC2521 2 60.4_0402_1% EC_VCCST_PG @
[48] VCCST_PWRGD
TMS/TDI pin CPU on-die termination
+1.05VS_VCCSTG CFG0 RC31 1 @ 2 1K_0402_5%
Place to PCH side +1.05VS_VCCSTG CFG2 RC32 1 2 1K_0402_5%
2

CPU_XDP_TMS 51_0402_5% 1 CMC@ 2 RC255


RC18 CPU_XDP_TDI 51_0402_5% 1 CMC@ 2 RC254 CFG4 RC33 1 2 1K_0402_5%
1K_0402_5% CPU_XDP_TDO 100_0402_1% 2 DCI@ 1 RC253

CFG5 RC36 1 @ 2 1K_0402_5%


1

H_PROCHOT# RC42 2 1 499_0402_1% H_PROCHOT#_R


[48] H_PROCHOT# CFG6 RC34 1 2 1K_0402_5%
Place to CPU side @

CPU_XDP_TCK0 51_0402_5% 1 DCI@ 2 RC256 CFG7 RC35 1 @ 2 1K_0402_5%


3 3

SVID ALERT +1.05V_VCCST


If need debug with INTEL. this cmc@ need pop

CPU_XDP_TRST# R387 1 @ 2 0_0402_5%


1

PCH_XDP_TRST# [21]
RC40
56_0402_1%

teknisi-indonesia.com
2

RC39 1 2 220_0402_5% CPU_SVID_ALERT#


[70] VR_SVID_ALERT#
+1.2V +3VS

SVID DATA

1
+1.05V_VCCST CC41
UC2 RC43
1 5 2 1 100K_0402_5%
NC VCC
2

DDR_PG_CTRL 2 0.1U_0201_10V6K
RC41

2
A 4 DDR_VTT_PG_CTRL
100_0402_5% Y DDR_VTT_PG_CTRL [67]
3
GND
74AUP1G07GW_TSSOP5
1

RC38 1 @ 2 0_0402_5% CPU_SVID_DAT


[70] VR_SVID_SDIO

4 SVID CLK 4

RC37 1 @ 2 0_0402_5% CPU_SVID_CLK


[70] VR_SVID_SCLK

Security Classification Compal Secret Data Compal Electronics, Inc.


571391_CFL_H_PDG_Rev0p5 Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

1. The total Length of Data and Clock (from CPU to each VR) must be equal (0.1
inch).
CFL-H(5/8)CFG,SVID
2. Route the Alert signal between the Clock and the Data signals. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
3. Place those resistors close CPU side. Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 10 of 81
A B C D E
A B C D E

GT
32000mA(Hexa Core GT2) +VCCCORE +VCCCORE +VCCCORE CFL-H +VCCCORE
+VCCGT CFL-H +VCCGT CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
AT37 VCCGT7 VCCGT86 BE36 AA37 VCC7 VCC70 AJ29 N32 VCC7 VCC70 Y32
AT38 VCCGT8 VCCGT87 BE37 AA38 VCC8 VCC71 AJ30 N35 VCC8 VCC71 Y33
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AV35 VCCGT24 VCCGT103 BG33 AC34 VCC24 VCC87 AL29 R32 VCC24
AV36 VCCGT25 VCCGT104 BG34 AC35 VCC25 VCC88 AL30 R33 VCC25
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW33 VCCGT29 VCCGT108 BH34 AD31 VCC29 VCC92 AL36 R37 VCC29
AW34 VCCGT30 VCCGT109 BH35 AD32 VCC30 VCC93 AL37 R38 VCC30
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY36 VCCGT40 VCCGT119 BJ24 AE31 VCC40 VCC103 AM35 U30 VCC40
AY37 VCCGT41 VCCGT120 BJ26 AE32 VCC41 VCC104 AM36 U31 VCC41
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA32 VCCGT48 VCCGT127 BK20 AF31 VCC48 VCC111 AN35 V14 VCC48
BA33 VCCGT49 VCCGT128 BK21 AF32 VCC49 VCC112 AN36 V31 VCC49
BA34 VCCGT50 VCCGT129 BK23 AF33 VCC50 VCC113 AN37 V32 VCC50
BA35 VCCGT51 VCCGT130 BK24 AF34 VCC51 VCC114 AN38 V33 VCC51
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 +VCCCORE W13 VCC57
BB34 VCCGT58 VCCGT137 BL24 AG32 VCC58 VCC121 AP37 W14 VCC58
BB35 VCCGT59 VCCGT138 BL25 AG33 VCC59 VCC122 AP38 W29 VCC59
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60

2
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
VCCGT62 VCCGT141 VCC62 RC10 VCC62 10 OF 13
BB38 BL28 AG36 W32
BC29 VCCGT63 VCCGT142 BL36 VCC63 100_0402_1% VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15

1
3 VCCGT66 VCCGT145 @ 3
BC32 BM16 AG37
VCCGT67 VCCGT146 9 OF 13 VCC_SENSE VCCCORE_SENSE [70]
BC35 BM17 AG38
VCCGT68 VCCGT147 VSS_SENSE VSSCORE_SENSE [70]
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
VCCGT70 VCCGT149

1
BC38 BN15 @
BD13 VCCGT71 VCCGT150 BN16 RC11
BD14 VCCGT72 VCCGT151 BN17
VCCGT73 VCCGT152 100_0402_1%
BD29 BN36
BD30 VCCGT74 VCCGT153 BN37

2
BD31 VCCGT75 VCCGT154 BN38
VCCGT76 VCCGT155 +VCCGT 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD32 BP15 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD33 VCCGT77 VCCGT156 BP16
VCCGT78 VCCGT157 3. RC10, RC11 should be placed within 2 inches (50.8 mm) of CPU
BD34 BP17
VCCGT79 VCCGT158
2

BP37 BR37
BP38 VCCGT159 VCCGT164 BT15 RC12
BR15 VCCGT160 VCCGT165 BT16
VCCGT161 VCCGT166 100_0402_1%
BR16 BT17
BR17 VCCGT162 VCCGT167 BT37
1

VCCGT163 VCCGT168

AH37
11 OFVSSGT_SENSE
13 VSSGT_SENSE [70]
AH38
VCCGT_SENSE VCCGT_SENSE [70]
1

CFL-H_BGA1440
@ RC13
100_0402_1%
2

4 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 4


2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC12, RC13 should be placed within 2 inches (50.8 mm) of CPU

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(6/8)VCC_CORE/GT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 11 of 81
A B C D E
A B C D E

+1.2V_VDDQ_CPU
Max: 3300mA

+VCCSA CFL-H +1.2V +1.2V


UC1L

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
+VCC_SA J30 AA6
K29 VCCSA1 VDDQ1 AE12
Max: 11100mA VCCSA2 VDDQ2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 AF5
VCCSA3 VDDQ3

CC17

CC18

CC19

CC20

CC153
CC152

CC154

CC24

CC25

CC27
CC26

CC28

CC29

CC30

CC31

CC32
K31 AF6
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6 @ @ @
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12
VCCSA18 VDDQ18 +0.95VS_VCCIO +1.05VS_VCCSTG
M33 K6 +1.2V_VCCPLL_OC
M34 VCCSA19 VDDQ19 L12
+VCC_IO M35 VCCSA20 VDDQ20 L6
Max: 6400mA M36 VCCSA21 VDDQ21 R6

1U_0201_6.3V6M
VCCSA22 VDDQ22

10U_0402_10V6M

10U_0402_10V6M

10U_0402_10V6M

1U_0201_6.3V6M
10U_0402_10V6M

1U_0201_6.3V6M
T6
+0.95VS_VCCIO VDDQ23 W6 1
VDDQ24 1 1 1 1 @ 1 1
Y12

CC40
VDDQ25

CC33

CC34

CC35

CC36
CC175

CC37
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC
VCCIO2 2
G17 +1.2V_VCCPLL_OC 2 2 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST +VCCSA 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +0.95VS_VCCIO: 10uF * 4 +1.2V_VCCPLL_OC: 1uF * 2 2
VCCIO10 VCCSTG2 571483_CFL_H_RVP_CRB_TDK_Rev0p5
H21 PLACE CAP BACKSIDE +1.05VS_VCCSTG: 1uF * 1
H26 VCCIO11 G30 +1.05V_VCCSFR

2
H27 VCCIO12 VCCSTG1
VCCIO13 Max: 150mA RC15
J15 H28
J16 VCCIO14 VCCPLL1 J28 100_0402_1%
J17 VCCIO15 VCCPLL2
J19 VCCIO16

1
J20 VCCIO17 M38 VCCSA_SENSE
VCCIO18 VCCSA_SENSE VCCSA_SENSE [70]
J21 M37 VSSSA_SENSE
VCCIO19 VSSSA_SENSE VSSSA_SENSE [70]
J26
J27 VCCIO20 H14 VCCIO_SENSE
VCCIO21 VCCIO_SENSE TC92 TP@

1
J14 VSSIO_SENSE TC93 TP@
12 OF 13 VSSIO_SENSE RC16 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
100_0402_1%
2. Maintain 25-mil separation distance away from any other dynamic signals.
CFL-H_BGA1440 3. RC15, RC16 should be placed within 2 inches (50.8 mm) of CPU

2
+1.05V_VCCSTU +1.05V_VCCST

60mA
RC1401 @ 2 0_0402_5%

1U_0201_6.3V6M

10U_0402_10V6M
1 @
1

CC38

CC178
2
2
3 3

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1

PLACE CAP BACKSIDE

+1.05V_VCCSFR
150mA
RC1431 @ 2 0_0402_5%

1U_0201_6.3V6M

10U_0402_10V6M

10U_0402_10V6M
1 1 @ 1 @

CC179

CC180
CC39
2 2 2

571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1

PLACE CAP BACKSIDE


4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(7/8)VCCSA/VCCIO/VDDQ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 12 of 81
A B C D E
A B C D E

CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP18 VSS_328 VSS_412 F21 E3 RSVD_TP5
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 E1 IST_TRIG
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP24 VSS_330 VSS_414 F25 D1 RSVD_TP4
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 RSVD_TP3
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 TP@ TC27 BR1 BK28
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP29 VSS_333 VSS_417 F3 BT2 RSVD_TP1 RSVD11 BJ28
1 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 TP@ TC29 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 RC6 1 @ 2 0_0402_5% A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 RC7 1 @ 2 0_0402_5% A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 [21] PCH_TRIGOUT_R PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC8 1 2 30_0402_5% CPU_TRIGOUT J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 [21] CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC51 TP@
AF2 AR36 BE4 BM25 C31 J32 C1
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC53 TP@
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC55 TP@
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC57 TP@
AG11 AR5 BF33 BM29 C9 J7 BH30 B2
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13
VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(8/8)GND/RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 13 of 81
A B C D E
A B C D E

CNP-H
UH1B
[9] DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 K34 J3
DMI0_RXN USB2N_1 USB20_N1 [56]
[9] DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 J35 J2 USB3.1 Port 1 (Left Back)
DMI0_RXP USB2P_1 USB20_P1 [56]
DMI_CRX_PTX_N0 C33 N13
[9] DMI_CRX_PTX_N0 DMI0_TXN USB2N_2 USB20_N2 [56]
[9] DMI_CRX_PTX_P0 DMI_CRX_PTX_P0 B33 N15 USB3.1 Port 2 (Right Back)
DMI0_TXP USB2P_2 USB20_P2 [56]
DMI_CTX_PRX_N1 G33 K4
[9] DMI_CTX_PRX_N1 DMI1_RXN USB2N_3 USB20_N3 [55]
[9] DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 F34 K3 USB3.1 Port 2 (Right Front) with AOU support
DMI1_RXP USB2P_3 USB20_P3 [55]
[9] DMI_CRX_PTX_N1 DMI_CRX_PTX_N1 C32 M10
DMI1_TXN USB2N_4 USB20_N4 [61]
DMI_CRX_PTX_P1 B32 L9 To IT8176
[9] DMI_CRX_PTX_P1 DMI1_TXP USB2P_4 USB20_P4 [61]
[9] DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 K32 M1
DMI2_RXN USB2N_5 USB20_N5 [60]
DMI_CTX_PRX_P2 J32 L2 For USB Type-C TBT port
[9] DMI_CTX_PRX_P2 DMI2_RXP USB2P_5 USB20_P5 [60]
1 [9] DMI_CRX_PTX_N2 DMI_CRX_PTX_N2 C31 K7 1
DMI2_TXN USB2N_6 USB20_N6 [61]
[9] DMI_CRX_PTX_P2 DMI_CRX_PTX_P2 B31 K6 To IT8295
DMI2_TXP USB2P_6 USB20_P6 [61]
DMI_CTX_PRX_N3 G30 L4
[9] DMI_CTX_PRX_N3 DMI3_RXN USB2N_7 USB20_N7 [42]
[9] DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 F30 L3 Camera
DMI3_RXP USB2P_7 USB20_P7 [42]
DMI_CRX_PTX_N3 C29 G4
[9] DMI_CRX_PTX_N3 DMI3_TXN USB2N_8 +3VALW
[9] DMI_CRX_PTX_P3 DMI_CRX_PTX_P3 B29 G5
A25 DMI3_TXP USB2P_8 M6
B25 RSVD USB2N_9 N8
P24 RSVD USB2P_9 H3 USB_OC2# RH201 1 2 10K_0402_5%
R24 RSVD USB2N_10 H2 USB_OC3# RH202 1 2 10K_0402_5%
C26 RSVD USB2P_10 R10 USB_OC1# RH203 1 2 10K_0402_5%
B26 RSVD USB2N_11 P9 USB_OC0# RH204 1 2 10K_0402_5%
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
C27 RSVD USB2N_13 N2
L26 RSVD USB2P_13 E5 USB20_N14
RSVD USB2N_14 USB20_N14 [49] USB2.0 P14 for integrated intel@Wireless-AC
M26 F6 USB20_P14
www.teknisi-indonesia.com USB20_P14 [49] BT
D29 RSVD USB2P_14
RSVD FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf
E28 AH36 USB_OC0#
K29 RSVD GPP_E9/USB2_OC0# AL40 USB_OC1#
M29 RSVD GPP_E10/USB2_OC1# AJ44 USB_OC2#
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3#
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXNGPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXPGPP_F16/USB2_OC5# AR37
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
P21 PCIE2_RXN/USB31_8_RXN F4 USB2_RCOMP RH8 1 2 113_0402_1%
2 B18 PCIE2_RXP/USB31_8_RXP USB2_COMP F3 USB2_VBUSSENSE RH9 1 2 1K_0402_5% FOLLOW MP projects 2
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID RH10 1 2 1K_0402_5%
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
C19 PCIE3_TXN/USB31_9_TXN GPD7
N18 PCIE3_TXP/USB31_9_TXP G45 PCIE_PTX_DRX_P24
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_P24 [49]
R18 G46 PCIE_PTX_DRX_N24
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PTX_DRX_N24 [49]
D20 Y41 PCIE_PRX_DTX_P24
PCIE4_TXN/USB31_10_TXN PCIE24_RXP PCIE_PRX_DTX_P24 [49]
C20 Y40 PCIE_PRX_DTX_N24
HM370 no support PCIE[1~7] F20 PCIE4_TXP/USB31_10_TXP
PCIE5_RXN
PCIE24_RXN
PCIE23_TXP
G48 PCIE_PTX_DRX_P23
PCIE_PRX_DTX_N24
PCIE_PTX_DRX_P23
[49]
[49]
G20 G49 PCIE_PTX_DRX_N23
PCIE5_RXP PCIE23_TXN PCIE_PTX_DRX_N23 [49]
B21 W44 PCIE_PRX_DTX_P23
PCIE5_TXN PCIE23_RXP PCIE_PRX_DTX_N23 PCIE_PRX_DTX_P23 [49]
A22 W43
PCIE5_TXP PCIE23_RXN PCIE_PRX_DTX_N23 [49]
K21 H48 PCIE_PTX_DRX_P22
J21 PCIE6_RXN
PCIE6_RXP
PCIE22_TXP
PCIE22_TXN
H47 PCIE_PTX_DRX_N22 PCIE_PTX_DRX_P22
PCIE_PTX_DRX_N22
[49]
[49]
To M.2
D21 U41 PCIE_PRX_DTX_P22
PCIE6_TXN PCIE22_RXP PCIE_PRX_DTX_P22 [49]
C21 U40 PCIE_PRX_DTX_N22
PCIE6_TXP PCIE22_RXN PCIE_PTX_DRX_P21
PCIE_PRX_DTX_N22 [49]
B23 F46
PCIE7_TXP PCIE21_TXP PCIE_PTX_DRX_P21 [49]
C23 G47 PCIE_PTX_DRX_N21
PCIE7_TXN PCIE21_TXN PCIE_PRX_DTX_P21 PCIE_PTX_DRX_N21 [49]
J24 R44
PCIE7_RXP PCIE21_RXP PCIE_PRX_DTX_N21 PCIE_PRX_DTX_P21 [49]
L24 T43
PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 [49]
F24
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0

3
@ 3

+3VALW

The 30 HSIO lanes on PCH-H supports the following configurations:


1. Up to 24 PCIe* Lanes

1

XA maximum of 16 PCIe* Ports (or devices) can be enabled
� When a GbE Port is enabled, the maximum number of PCIe* Ports (or
E
devices) that can be enabled reduces based off the following: RH12
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)

X PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe* 10K_0402_5%
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and

2
21-24 (PCIe* Controller #6) can be individually configured GPD_7
2. Up to 6 SATA Lanes STRAP

X A maximum of 6 SATA Ports (or devices) can be enabled
� SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
X

1
� SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
X
3. Up to 10 USB 3.1 Lanes RH11

X A maximum of 10 USB 3.1 Ports (or devices) can be enabled 10K_0402_5%
4. Up to 4 GbE Lanes @
� A maximum of 1 GbE Port (or device) can be enabled
X

2
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices

X x2 and x4 PCIe* NVMe SSD X'tal Input:
� x2 IntelR Optane? Memory Device
X High: Differential
� Express* (PCIe*)�chapter for the PCH PCIe* Controllers,configurations
� See the PCI
X Low: Single ended
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft check its function
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(1/8)DMI/PCIE/USB2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 14 of 81
A B C D E
A B C D E

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H


XTAL_24M_PCH_OUT RH17 1 EMI@ 2 33_0402_5% XTAL_24M_PCH_OUT_R UH1G
XTAL_24M_PCH_IN RH18 1 EMI@ 2 33_0402_5% XTAL_24M_PCH_IN_R TH74 TP@ BE33
GPP_A16/CLKOUT_48
D7 Y3 TP@ TH73
[10] PCH_CPU_24M_CLK_P CLKOUT_CPUNSSC_P CLKOUT_ITPXDP#
C6 Y4 TP@ TH72
[10] PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
RH16 1 2 1M_0402_5%
B8 B6 PCH_CPU_PCIBCLK_N
[10] PCH_CPU_BCLK_P CLKOUT_CPUBCLK_PCLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N [10]
24MHZ_18PF_XRCGB24M000F2P51R0 C8 A6 PCH_CPU_PCIBCLK_P
TXC SJ10000UJ00 [10] PCH_CPU_BCLK_N CLKOUT_CPUBCLK#CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P [10]
3 1 XTAL_24M_PCH_OUT_R U9 AJ6
3 1 XTAL_OUT CLKOUT_PCIE_N0 CLK_PCIE_N0 [57]
27P_0402_50V8J

1 Murata SJ10000UJ00 XTAL_24M_PCH_IN_R U10 AJ7 Thunderbolt 1


NC NC XTAL_IN CLKOUT_PCIE_P0 CLK_PCIE_P0 [57]

27P_0402_50V8J
1 1
YH1 SJ10000TP00 RH20 1 2 60.4_0402_1% XCLK_BIASREF T3 AH9
4 2 XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_N1 [49]
CH4

CH5
AH10 NGFF SSD
CLKOUT_PCIE_P1 CLK_PCIE_P1 [49]
XCLK_BIASREF PCH_RTCX1 BA49
2 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_N2 [50]
AE15 LAN
CLKOUT_PCIE_P2 CLK_PCIE_P2 [50]
BF31
[57] TBT_CLKREQ0# BE31 GPP_B5/SRCCLKREQ0# AE6
[49] SSD_CLKREQ1# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_N3 [49]
AR32 AE7 WLAN
[50] LAN_CLKREQ2# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 [49]
BB30
[49] WLAN_CLKREQ3# GPP_B8/SRCCLKREQ3#
BA30 AC2
PCH_RTCX1 [24] GPU_CLKREQ4# GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PEG_N4 [24] GPU
AN29 AC3
GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PEG_P4 [24]
AE47
PCH_RTCX2 AC48 GPP_H0/SRCCLKREQ6# AB2
AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3
RH19 1 2 10M_0402_5% AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
AC41 GPP_H3/SRCCLKREQ9# W4
AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
YH2 GPP_H6/SRCCLKREQ12#
AB48 W7
2 1 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15#
10P_0402_50V8J

1 32.768KHZ_9PF_X1A000141000200 1 AC14
10P_0402_50V8J

V2 CLKOUT_PCIE_N8 AC15
CH6 CH7 V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15 U2
2 Trace Space: 15 mil 2 EPSON SJ10000PW00 T2 CLKOUT_PCIE_N9 U3
Max Trace Length: 1000 mil T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 TXC SJ10000Q400 CLKOUT_PCIE_P14 AC9 2
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11
+3VS CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
AC6
CLKOUT_PCIE_P12 7 OF 13 R6
CLKIN_XTAL REFCLK_CNV [49] 1V@38.4MHZ
RH205 1 2 10K_0402_5% TBT_CLKREQ0# CNP-H_BGA874 Rev1.0

1
@
RH206 1 2 10K_0402_5% SSD_CLKREQ1# RH173
10K_0402_5%
RH207 1 2 10K_0402_5% LAN_CLKREQ2#

2
RH208 1 2 10K_0402_5% WLAN_CLKREQ3#

CNP-H
2 1 GPU_CLKREQ4# UH1M
RH189 DIS@ 10K_0402_5%
AW13 BD4 CLK_CNV_PRX_DTX_N
GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_N [49]
BE9 BE3 CLK_CNV_PRX_DTX_P
GPP_G1/SD_DATA0 CNV_WR_CLKP CLK_CNV_PRX_DTX_P [49]
For DDX03 R02 BF8
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0 CNV_PRX_DTX_N0 [49]
+1.8V_PRIM BG8 BB4
XTAL Frequency Select GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_P0 [49]
BE8 BA3 CNV_PRX_DTX_N1
GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 [49]
BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 [49]
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
CNV_WT_CLKN CLK_CNV_PTX_DRX_N [49]
AP3 BB6 CLK_CNV_PTX_DRX_P
3 RH26 1 2 4.7K_0402_5%CNV_BRI_PTX_DRX STRAP GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P [49] 3
AP2
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 [49]
AM7 BD7 CNV_PTX_DRX_P0
This signal has a weak internal pull-down 20K. GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P CNV_PTX_DRX_P0 [49]
0 = 38.4/19.2MHz XTAL frequency selected. BG6 CNV_PTX_DRX_N1
CNV_WT_D1N CNV_PTX_DRX_N1 [49]
1 = 24MHz XTAL frequency selected. (DDX03) AV6 BF6 CNV_PTX_DRX_P1
GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_PTX_DRX_P1 [49]
Notes: AY3 BA1 CNV_WT_RCOMP RH25 1 2 150_0402_1%
1. The internal pull-down is disabled after RSMRST# AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
de-asserts.
AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH21 1 2 100_0402_1%
2. This signal is in the primary well. GPP_J10 PCIE_RCOMPN
AW3 A13 PCIE_RCOMPP
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH22 1 2 200_0402_1%
CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH23 1 2 200_0402_1%
+1.8V_PRIM [49] CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP
AY2 BD1
VCCPSPI Select [49] CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P8 RH24 1
BA4 BE1 2 200_0402_1%
[49] CNV_RGI_PTX_DRX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
CNV_RGI_PRX_DTX AV3 BE2
[49] CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
AW2
@ GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD Y35
RH93 1 2 4.7K_0402_5% GPP_J9 STRAP VCCPSPI Select GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
The signal has a weak internal pull-down 20K RSVD3
0 = VCCPSPI is connected to 3.3V rail BC1
1 = VCCPSPI is connected to 1.8V rail 13 OF 13 RSVD1 AL35
Note: If VCCPSPI is connected to 1.8V rail, this pin TP TP@ TH101
strap must be a � 1�for the proper functionality #571483_CFL_H_RVP_CRB_TDK_Rev0p5
of the SPI (Flash) I/Os +1.8V_PRIM CNP-H_BGA874 Rev1.0
Recommend external test point
@
+1.8V_PRIM
M.2 CNV Mode Select RH1811 2 20K_0402_1% CNV_BRI_PRX_DTX 571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
RH1821 2 20K_0402_1% CNV_RGI_PRX_DTX
RH167 2 1 10K_0402_5% CNV_RGI_PTX_DRXSTRAP
4 4
@
RH168 2 1 10K_0402_5%

An external pull-up or pull-down is required.


0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
PCH(2/8)CLK/CNVI/SD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 15 of 81
A B C D E
A

CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8
AT6 GPP_I6/DDPB_CTRLDATA AN13
AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10
AP9 GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA AL9
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40
GPP_F23/DDPF_CTRLDATA AT49 DGPU_HOLD_RST#
GPP_F22/DDPF_CTRLCLK DGPU_HOLD_RST# [24] dGPU
AP41
EDP_HPD_CPU AN6 GPP_F14/PS_ON#
[41] EDP_HPD_CPU GPP_I4/EDP_HPD/DISP_MISC4

1
M45
GPP_K23/IMGCLKOUT1 L48
RV353 GPP_K22/IMGCLKOUT0 T45
100K_0402_5% GPP_K21 T46
5 OF 13 GPP_K20 AJ47 TBT_CIO_PLUG_EVENT#
TBT_CIO_PLUG_EVENT# [57]

2
GPP_H23/TIME_SYNC0
@RF@ Rev1.0
CNP-H_BGA874
10P_0402_50V8J 1 2 CH65 PCH_SPI_0_CLK
@

03/14 From RF Team Request CNP-H


UH1A PCH_PLTRST# CH74 1 2 100P_0402_50V8J
BE36 AV29 PCH_PLTRST#
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST#
+3V_SPI @ESD@
R15 Y47
#571391_CFL_H_PDG_Rev0p71 R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
RH3 2 1 1K_0402_5% PCH_SPI_0_D2_R RSVD1 GPP_K12/GSXDOUT Y48 provided by the PCH to expand the GPIOs
GPP_K13/GSXSLOAD W46
on a platform that needs more GPIOs than the
GPP_K14/GSXDIN ones provided by the PCH.
RH4 2 1 1K_0402_5% PCH_SPI_0_D3_R AL37 AA45
AN35 VSS GPP_K15/GSXSRESET#
TH11 TP@ TP
RH98 2 1 100K_0402_5% PCH_SPI_0_D0
PCH_SPI_0_D0 AU41 AL47 DGPU_PWROK
SPI0_MOSI GPP_E3/CPU_GP0 DGPU_PWROK [34] DGU +3VS
PCH_SPI_0_D1 BA45 AM45
+3V_1.8V_PGPPHK PCH_SPI_0_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TP_INT#
SPI0_CS0# GPP_B3/CPU_GP2 TP_INT# [52]
PCH_SPI_0_CLK AW47 BC33
RH99 2 1 100K_0402_5% GPP_H15 STRAP AW48 SPI0_CLK GPP_B4/CPU_GP3 DGPU_PWROK RH164 2 1 10K_0402_5%
TH19 TP@ SPI0_CS1#
#571182_CNL_PCH_H_EDS_V1_Rev0.7 AE44
PCH_SPI_0_D2 AY48 GPP_H18/SML4ALERT# AJ46 TBT_FORCE_PWR
External pull-up is required. Recommend 100K if pulled SPI0_IO2 GPP_H17/SML4DATA TBT_FORCE_PWR [57]
up to 3.3V or 75K if pulled up to 1.8V. PCH_SPI_0_D3 BA46 AE43 TP_INT# RH1592 @ 1 100K_0402_5%
SPI0_IO3 GPP_H16/SML4CLK TP@ TH140
571007_CFL_MOW_Archive_WW22_2017 AT40 AC47 GPP_H15 ORB for RTD3_CIO_PWR_EN
STUFF R on GPP_H15 SPI0_CS2# GPP_H15/SML3ALERT# AD48 TBT_USB_FORCE_PWR
GPP_H14/SML3DATA TBT_USB_FORCE_PWR [57]
BE19 AF47
+3VALW BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 GPP_H12
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 [19] +3VL_RTC
BF18 AD47
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
CMC@ XDP_SPI_SI GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
RH1921 2 1K_0402_1% BC17
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER#1M_0402_5% 2 1 RH6
CMC@ GPP_D21/SPI1_IO2 INTRUDER#
XDP_SPI_SIRH1651 2 1K_0402_1% PCH_SPI_0_D0
CNP-H_BGA874 Rev1.0 RVP: 330K
A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.

PCH_SPI_0_D1 RC2571 2 33_0402_5% PCH_SPI_0_D1_R


PCH_SPI_0_CLK RC2581 EMI@ 2 33_0402_5% PCH_SPI_0_CLK_R
PCH_SPI_0_D0 RC2591 2 33_0402_5% PCH_SPI_0_D0_R
PCH_SPI_0_D3 RC2601 2 33_0402_5% PCH_SPI_0_D3_R
From SOC

PCH_SPI_0_D2 1 2 PCH_SPI_0_D2_R
RC30 EMI@ 33_0402_5%
PCH PLTRST Buffer RH7 1 @ 2 0_0402_5%

+3VS

EC_SPI_CLK RC2611 EMI@ 2 33_0402_5% PCH_SPI_0_CLK_R


[48] EC_SPI_CLK @
EC_SPI_MOSI RC2621 2 33_0402_5% PCH_SPI_0_D0_R
[48] EC_SPI_MOSI CH11 2
EC_SPI_CS0# RC2631 2 33_0402_5% PCH_SPI_0_CS#0
From EC [48] EC_SPI_CS0#
EC_SPI_MISO RC2641 2 33_0402_5% PCH_SPI_0_D1_R
[48] EC_SPI_MISO 0.1U_0402_10V6K

5
@UH3
PCH_PLTRST# 1

P
B 4
Y PCI_RST# [24,48,49,50,57]
2
A

1
TC7SH08FU_SSOP5

3
RH183
100K_0201_1%
SPI ROM 16M Byte

2
+3V_SPI
@
UH2 CC1761 2 0.1U_0201_10V K X5R
PCH_SPI_0_CS#0 1 8
PCH_SPI_0_D1_R 2 CS# VCC 7 PCH_SPI_0_D3_R
PCH_SPI_0_D2_R 3 DO(IO1) IO 6 PCH_SPI_0_CLK_R
4 IO2 CLK 5 PCH_SPI_0_D0_R
GND DI(IO0)
1
W25Q128JVSIQ_SO8
CC177
10P_0402_50V8J
2 @EMI@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
PCH(3/8)DDC/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 16 of 81
A
A B C D E

CNP-H
UH1F
USB3_PTX_DRX_N1 F9 BB39
[56] USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD0 [48]
USB3_PTX_DRX_P1 F7 1.8V AW37
[56] USB3_PTX_DRX_P1 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [48] +1.8VS_3VS_PGPPA
[56] USB3_PRX_DTX_N1 USB3_PRX_DTX_N1 D11 (eSPI) GPP_A3/LAD2/ESPI_IO2 AV37
USB31_1_RXN LPC_AD2 [48]
[56] USB3_PRX_DTX_P1 USB3_PRX_DTX_P1 C11 BA38
LPC_AD3 [48]
USB2/3 MB PORT1/2 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3
USB3_PTX_DRX_N2 C3 PIRQA# RH169 1 2 10K_0402_5%
[56] USB3_PTX_DRX_N2 USB31_2_TXN
USB3_PTX_DRX_P2 D4 BE38
[56] USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# LPC_FRAME# [48]
1 [56] USB3_PRX_DTX_N2 USB3_PRX_DTX_N2 B9 AW35 KB_RST# RH190 1 2 10K_0402_5% 1
USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# SERIRQ [48]
[56] USB3_PRX_DTX_P2 USB3_PRX_DTX_P2 C9 BA36 PIRQA#
USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 KB_RST# SERIRQ RH200 1 2 10K_0402_5%
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38
C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#
G14 USB31_6_TXP BB36 CLK_LPC RH27 1 EMI@ 2 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC [48]
F14 BB34
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
B15 USB31_5_TXN T48
J13 USB31_5_TXP GPP_K19/SMI# T47
K13 USB31_5_RXN GPP_K18/NMI#
USB31_5_RXP
USB3_PTX_DRX_P3 G12 AH40
[55] USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2
USB3_PTX_DRX_N3 F11 AH35
[55] USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1
USB3_PRX_DTX_P3 C10 AL48
[55] USB3_PRX_DTX_P3
USB2/3 MB PORT3 [55] USB3_PRX_DTX_N3 USB3_PRX_DTX_N3 B10 USB31_3_RXP
USB31_3_RXN
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
AP47
AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47 DEVSLP4
USB31_4_TXN GPP_F6/SATA_DEVSLP4 DEVSLP4 [49]
J15 AP48
K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
USB31_4_RXN
CNP-H_BGA874 Rev1.0

CNP-H
2 UH1C 2
CL_CLK AR2 G36
TH55 TP@ CL_CLK PCIE9_RXN
CL_DATA AT5 F36
For Intel CLINK TH56 TP@ CL_DATA PCIE9_RXP
CL_RST# AU4 C34
TH57 TP@ CL_RST# PCIE9_TXN D34
PCIE9_TXP
www.teknisi-indonesia.com
P48
V47 GPP_K8
V48 GPP_K9 K37
W47 GPP_K10 PCIE10_RXN J37
GPP_K11 PCIE10_RXP C35
L47 PCIE10_TXN B35
L46 GPP_K0 PCIE10_TXP
U48 GPP_K1 F44
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45
N48 GPP_K3 PCIE15_RXP/SATA2_RXP B40
N47 GPP_K4 PCIE_15_SATA_2_TXN C40
P47 GPP_K5 PCIE15_TXP/SATA2_TXP
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
SATA_PTX_DRX_P0 C36 PCIE16_RXP/SATA3_RXP B41
[54] SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
To Thunderbolt
HDD [54] SATA_PTX_DRX_N0 SATA_PRX_DTX_P0 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
F39
[54] SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 G38 PCIE11_RXP/SATA0A_RXP K43
[54] SATA_PRX_DTX_N0 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 PCIE_PRX_TTX_N17 [57]
PCIE17_RXP/SATA4_RXP PCIE_PRX_TTX_P17 [57]
AR42 A42 PCIE_PTX_C_TRX_N17 TBT@ CH79 2 1 0.22U_0201_6.3V
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN PCIE_PTX_TRX_N17 [57]
AR48 B42 PCIE_PTX_C_TRX_P17 TBT@ CH78 2 1 0.22U_0201_6.3V
GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_TRX_P17 [57]
AU47
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE_PRX_TTX_N18 [57]
R40 PCIE_PRX_TTX_P18 [57]
3 PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42 PCIE_PTX_C_TRX_N18 TBT@ CH81 2 1 0.22U_0201_6.3V 3
[49] PCIE_PTX_DRX_N14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_TRX_N18 [57]
PCIE_PTX_DRX_P14 D39 D42 PCIE_PTX_C_TRX_P18 TBT@ CH80 2 1 0.22U_0201_6.3V
[49] PCIE_PTX_DRX_P14 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_TRX_P18 [57]
WLAN
PCIE_PRX_DTX_N14 D46
[49] PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 C47 PCIE14_RXN/SATA1B_RXN AK48
[49] PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
CH75 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_N13 B38 AH41
[50] PCIE_PTX_C_DRX_N13 CH76 1 2 0.1U_0201_10V6K PCIE_PTX_DRX_P13 C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43
[50] PCIE_PTX_C_DRX_P13 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 +1.05V_VCCST
LAN
PCIE_PRX_DTX_N13 C45 AK47
[50] PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47
[50] PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 SATAPCIE_4
GPP_F1/SATAXPCIE4/SATAGP4 SATAPCIE_4 [49]
E37 AM43 PCH_THERMTRIP#_R 2
PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 1
D38 AM47
PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 1K_0402_5% RH166
J41 AM48
H42 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7 RH166 close to PCH
PCIE12_RXN/SATA1A_RXN AU48 PCH_BKL_PWM
GPP_F21/EDP_BKLTCTL PCH_BKL_PWM [41]
TBT@ CH85 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_P20 B44 AV46 ENBKL
[57] PCIE_PTX_TRX_P20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_ENVDD ENBKL [41]
TBT@ CH84 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_N20 A44 AV44
[57] PCIE_PTX_TRX_N20 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD [41]
R37 #571391_CFL_H_PDG_Rev0p5.pdf
[57] PCIE_PRX_TTX_P20 PCIE20_RXP/SATA7_RXP
R35 AD3 PCH_THERMTRIP# RH158 1 2 620_0402_5%
[57] PCIE_PRX_TTX_N20 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R [10]
TBT@ CH82 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_P19 D43 AF2 RH13 1 2 13_0402_5% H_PECI
[57] PCIE_PTX_TRX_P19 PCIE19_TXP/SATA6_TXP PECI H_PECI [10,48]
TBT@ CH83 1 2 0.22U_0201_6.3V PCIE_PTX_C_TRX_N19 C44 AF3 H_PM_SYNC RH15 1 2 30_0402_5% H_PM_SYNC_R
[57] PCIE_PTX_TRX_N19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R [10]
N42 AG5
[57] PCIE_PRX_TTX_P19 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOWN_R H_PLTRST_CPU# [10]
M44 AE2
[57] PCIE_PRX_TTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN_R [10]
CNP-H_BGA874 Rev1.0

2
@
@
To Thunderbolt RH14
4
13_0402_5% 4

1
#571391_CFL_H_PDG_Rev0p5
12.2.10 PM_DOWN Topology

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE/SATA/USB3/eSPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 17 of 81
A B C D E
A B C D E

@RF@
1 2 HDA_BIT_CLK_R
CH66 2.2P_0402_50V8C
@RF@
1 2 HDA_SYNC_R
CH67 2.2P_0402_50V8C
@RF@
1 2 HDA_SDOUT_R
HDA_RST#_R RH2091 @ 2 33_0402_5% HDA_RST# CH68 2.2P_0402_50V8C
[45] HDA_RST#_R @RF@
HDA_BIT_CLK_R RH2101 2 33_0402_5% HDA_BIT_CLK 1 2 HDA_RST#_R
[45] HDA_BIT_CLK_R
HDA_SDOUT_R RH2111 2 33_0402_5% HDA_SDOUT CH69 2.2P_0402_50V8C
[45] HDA_SDOUT_R
HDA_SYNC_R RH2121 2 33_0402_5% HDA_SYNC 3/16 From RF Team Request
[45] HDA_SYNC_R
1 1
CNP-H +1.2V
UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#

2
[45] HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# PM_CLKRUN# [48]
HDA_SDOUT BF12
[19] HDA_SDOUT HDA_SDO/I2S0_TXD RH39
HDA_SYNC BG13 BF41
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC 470_0402_1%
HDA_RST# BE10 BD42
BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#

1
BE12 HDA_SDI1/I2S1_RXD BB46 DDR_DRAMRST#
I2S1_TXD/SNDW2_DATA DRAM_RESET# DDR_DRAMRST# [22,23]
BD12 BE32
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
GPP_B1/GSPI1_CS1#/TIME_SYNC1 2
BE29 CH11
CPU_DISPA_SDO_RRH28 1 2 30_0402_5% CPU_DISPA_SDO AM2 GPP_B0/GSPI0_CS1# R47 100P_0402_50V8J
[6] CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE
AN3 AP29 @ESD@
[6] CPU_DISPA_SDI_R RH29 1 HDACPU_SDI GPP_B11/I2S_MCLK 1
CPU_DISPA_BCLK_R 2 30_0402_5% CPU_DISPA_BCLK AM3 AU3 SYS_PWROK
[6] CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK SYS_PWROK [48] Near PCH
AV18 BB47 TBT_WAKE#
FOR Jefferson Peak RESET pin is glitch free,it GPP_D8/I2S2_SCLK WAKE# TBT_WAKE# [57]
AW18 BE40
GPP_D7/I2S2_RXD GPD6/SLP_A#
is recommended that a pull-down resistor of 75K [49] CLKREQ_CNV#
CLKREQ_CNV# BA17
GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN#
BF40
ohm on GPP_D5(CNV_RF_RESET#) CNV_RF_RESET# BE16 BC28 TP@
[49] CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# T415
BF15 BF42 PM_SLP_S3#
GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# PM_SLP_S3# [48,68]
BD16 BE42 PM_SLP_S4#
GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# [48,65,67]
AV16 BC42 TP@ T397
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
+3VL_RTC GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK
PCH_SRTCRST# GPD8/SUSCLK PM_BATLOW# SUSCLK [49]
RH31 1 2 20K_0402_1% BF44 PM_BATLOW# [57]
GPD0/BATLOW# BE35 SUSACK#_R
GPP_A15/SUSACK# TP@ T372
2 CH9 1 2 1U_0201_6.3V6M BE47 BC37 SUSWARN# TP@ T371 2
[48] EC_CLEAR_CMOS# PCH_SRTCRST# BD46 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
SRTCRST#
PCH_PWROK AY42 BG44 LAN_WAKE#
[48] PCH_PWROK PCH_PWROK GPD2/LAN_WAKE#
EC_RSMRST# BA47 BG42
[48] EC_RSMRST# RSMRST# GPD1/ACPRESENT AC_PRESENT [48]
RH32 1 2 20K_0402_1% EC_CLEAR_CMOS# BD39 SLP_SUS#
SLP_SUS# TP@ T373 --No Support Deep Sx
BE46 PBTN_OUT#_R RH48 1 @ 2 0_0402_5% PBTN_OUT#
GPD3/PWRBTN# PBTN_OUT# [48]
CH10 1 2 1U_0201_6.3V6M PCH_DPWROK AW41 AU2 SYS_RESET#
SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 SPKR
[19] SMBALERT# GPP_C2/SMBALERT# GPP_B14/SPKR SPKR [19,45]
CLRP2 1 2 SHORT PADS ECLR CMOS
SMB PCH_SMBCLK BE26 AE3 H_CPUPWRGD
Delay 18~25 ms (Link to DDR)[22,23] PCH_SMBCLK PCH_SMBDATA BF26 GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD [10]
[22,23] PCH_SMBDATA PCH_SML0ALERT# GPP_C1/SMBDATA XDP_ITP_PMODE
BF24 AL3
[19] PCH_SML0ALERT# GPP_C5/SML0ALERT# ITP_PMODE
PCH_SML0CLK BF25 AH4 CPU_XDP_TCK0
modified in 2017/12/03 GPP_C3/SML0CLK PCH_JTAGX CPU_XDP_TCK0 [10]
PCH_SML0DATA BE24 AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS [10]
[19] PCH_SML1ALERT# EC_SMB_CK2 BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO [10] Connect CPU & PCH
[25,41,46,48,51] EC_SMB_CK2 GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI [10]
SML1 EC_SMB_DA2 BE27 4 OF 13 AJ3 PCH_JTAG_TCK1
[25,41,46,48,51] EC_SMB_DA2 GPP_C7/SML1DATA PCH_JTAG_TCK TP@
T398
(Link to EC,DGPU) CNP-H_BGA874 Rev1.0

+3VALW @

+3VALW +3VALW

RH1712 @ 1 1K_0402_5% TBT_WAKE#

RH41 2 1 8.2K_0402_5% PM_BATLOW# RH219 1 2 10K_0402_5% PCH_PWROK


RH220 1 2 10K_0402_5% LAN_WAKE#
RH45 2 @ 1 100K_0402_5% AC_PRESENT RH221 1 2 10K_0402_5% EC_RSMRST#
3 RH222 1 2 10K_0402_5% SYS_RESET# 3
RH47 2 @ 1 100K_0402_5% PBTN_OUT#_R

+1.8VS_3VS_PGPPA

EC_RSMRST# RH52 2 @ 1 0_0402_5% PCH_DPWROK


LPC@ PM_CLKRUN#
RH44 2 1 100K_0402_5%

100K_0402_5% 1 @ 2 RH50 PCH_DPWROK


10k pull up

+3VS @ESD@
100P_0402_50V8J 1 2 CH71 SYS_RESET#
RH213 1 2 1K_0402_5% PCH_SML0CLK SYS_PWROK
RH214 1 2 1K_0402_5% PCH_SML0DATA
EC_SMB_CK2 @ESD@
RH215 1 2 1K_0402_5%
100P_0402_50V8J 1 2 CH72 SYS_PWROK

1
RH216 1 2 1K_0402_5% EC_SMB_DA2
RH188
@ESD@ 100K_0402_5%
100P_0402_50V8J 1 2 CH73 PCH_PWROK 2
+3VALW
Near PCH side
RH217 1 2 1K_0402_5% PCH_SMBCLK From ESD Team Request
RH218 1 2 1K_0402_5% PCH_SMBDATA

4 4

+1.05VALW

RH191 2 CMC@ 1 1K_0402_5% XDP_ITP_PMODE Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
PCH(5/8)PMU/HDA/SMBUS/DMIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 18 of 81
A B C D E
A B C D E

+3VS CNP-H
UH1K
RH223 1 2 1K_0402_5% I2C_1_SCL
RH224 1 2 1K_0402_5% I2C_1_SDA GSPI1_MOSI BA26 BA20
GPU_ID BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20
EC_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16
[48] EC_SCI# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
DGU GPU_EVENT# AW26 AN18
[25] GPU_EVENT# GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
+3VS GSPI0_MOSI BE30 BF14
ORB for RTD3_USB_PWR_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
1 T395 TP@ 1
GPU_ID1 BF29 GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17
RH76 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17
DGU [34] GPU_GC6_FB_EN_H GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH78 2 1 49.9K_0402_1% UART_2_PTXD_DRXD EDP_SW BB24
[41,48] EDP_SW GPP_C9/UART0A_TXD
EC_WL_OFF# BE23
[49] EC_WL_OFF# GPP_C8/UART0A_RXD
RH79 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS TBTA_HPD_PCH AP24
[57] TBTA_HPD_PCH GPP_C11/UART0A_CTS#
TBTB_HPD_PCH BA24
[57] TBTB_HPD_PCH GPP_C10/UART0A_RTS#
RH81 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45
BT_ON BD21 GPP_H20/ISH_I2C0_SCL AH46
DGPU_PWR_EN
[49] BT_ON GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
RH82 1 @ 2 10K_0402_5% Infrom BIOS Team HDMI_HPD_PCH AW24
[43] HDMI_HPD_PCH GPP_C14/UART1_RTS#/ISH_UART1_RTS#
DP_HPD_PCH AP21 AH47
[44] DP_HPD_PCH GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL TP@ T366
RH193 1 DIS@ 2 10K_0402_5% DGU [34,48] DGPU_PWR_EN DGPU_PWR_EN AU24 AH48
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA TP@ T367
UART_2_PCTS_DRTS AV21
UART_2_PRTS_DCTS AW21 GPP_C23/UART2_CTS#
+3V_1.8V_PGPPHK UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34 DGPU_PRSNT#
[49] UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32 SKU_ID
[49] UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
RH1001 @ 2 4.7K_0402_5% GPP_H12 I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34
GPP_H12 [16] [52] I2C_1_SCL GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
TP I2C_1_SDA BF21 BD34
This signal has a weak internal pull-down. [52] I2C_1_SDA GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
STRAP BC22 BF35
0 = Master Attached Flash Sharing (MAFS) enabled (Default) BF23 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BD38 GSYNC_STRAP
1 = Slave Attached Flash Sharing (SAFS) enabled. GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
Notes:
1. This signal is in the primary well. BE15
Warning: This strap must be configured to � 0� if the BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
eSPI or LPC strap is configured to � 0� GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CNP-H_BGA874 Rev1.0
+3VALW
@
2
RH97 1 ESPI@2 4.7K_0402_5% PCH_SML0ALERT# RH118 1 @ 2 0_0402_5%
For BIOS setting dGPU present 2

PCH_SML0ALERT# [18] [48] ME_EN HDA_SDOUT [18]


This signal has a weak internal Pull-down. STRAP +1.8VS_3VS_PGPPA
0 = LPC is selected (for EC 9022).(Default) This signal has a weak internal Pull-down.
LOW - dGPU exist
1 = eSPI is selected (for EC 9042). 0 = Enable security measures defined in the Flash Descriptor. (Default) Funct i on GPP_A22
Notes: 1 = Disable Flash Descriptor Security (override). This UMA@
DGPU_PRSNT# 1 2
1. The internal Pull-down is disabled after RSMRST#
de-asserts.
strap should only be asserted high using external 17" 1 RH155 10K_0402_5%
Pull-up in manufacturing/debug environments ONLY.
2. This signal is in the primary well. Notes: +3VS
1. The internal Pull-down is disabled after PCH_PWROK is high. +3VS 15" 0 1 DIS@ 2
2. This signal is in the primary well. RH156 10K_0402_5%
SKU_ID RH198 1 17@ 2 10K_0201_5%
GPU_ID1 RH226 1 @ 2 10K_0201_5%
RH95 1 @ 2 4.7K_0402_5% SMBALERT# RH199 1 15@ 2 10K_0201_5%
SMBALERT# [18]
RH225 1 @ 2 10K_0201_5% Funct i on GPP_A17
This signal has a weak internal Pull-down. STRAP
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default) GSYNC 1
1 = Enable Intel ME Crypto Transport Layer Security
+3VS
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS. +3VS NOGSYNC 0
Notes: GSYNC@
1. The internal Pull-down is disabled after RSMRST# GSYNC_STRAP RH196 1 2 10K_0201_5%
de-asserts.
GPU_ID 1 2
GPU_ID1 GPU_ID
2. This signal is in the primary well. RH194 @ 10K_0201_5%
Funct i on GPP_B16 GPP_B21 RH197 1 2 10K_0201_5%
RH195 1 @ 2 10K_0201_5% NOGSYNC@
To stuff RH63 for ORB Debug used ,otherwise un-stuff. N18G0 dGPU 0 0
RH63 1 2 150K_0402_1% PCH_SML1ALERT#
@ PCH_SML1ALERT# [18] N18G1 dGPU 0 1
This signal has an internal pull-down. STRAP RH225 N18G0@ RH195 N18G0@
3 0 = Disable IntelR DCI-OOB (Default) 3
1 = Enable IntelR DCI-OOB N18G2 dGPU 1 0
1. The internal pull-down is disabled after RSMRST# de-asserts.
2. When used as PCHHOT# and strap low, a 150K
pull-up is needed to ensure it does not override the
N18G0 N18G0 N18G3 dGPU 1 1
internal pull-down strap sampling.
CFL_H_PDG_REV0.71(SML1ALERT#) 10K_0201_5% 10K_0201_5%
>If USB 3.0 Port 1 is used for 4-wire DCI.OOB (BSSB), and alternate functionality is also
used on the pin, pull up to V3.3S with >100K resistor to avoid noise.
>If USB 3.0 Port 1 is used for DCI.OOB (BSSB) 4-wire BSSB, and NO alternate functionality RH225 N18G1@ RH194 N18G1@
is used, leave float.
+3VS>If DCI.OOB (BSSB) 2+2 functionality is used, pull up to V3.3S with a 4.7K resistor.

N18G1 N18G1
RH94 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP
The signal has a weak internal Pull-down.
10K_0201_5% 10K_0201_5%
0 = Disable � No Reboot�mode. (Default)
1 = Enable �No Reboot�mode (PCH will disable the SCI capability is available on all GPIOs
TCO Timer system reboot feature). This function is RH226 N18G2@ RH195 N18G2@ PCH GPIOs that can be routed to generate SMI# or NMI:
useful when running ITP/XDP. �
E GPP_B14, GPP_B20, GPP_B23
Notes: � GPP_C[23:22]
E
1. The internal Pull-down is disabled after � GPP_D[4:0]
E
PCH_PWROK is high. N18G2 N18G2 � GPP_E[8:0]
E
2. This signal is in the primary well. � GPP_I[3:0]
E
� GPP_G[7:0] (support SMI# only).
E
10K_0201_5% 10K_0201_5%
The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
RH226 N18G3@ RH194 N18G3@ except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
@ GSPI1_MOSI
RH96 1 2 150K_0402_1% STRAP All GPIOs have programmable internal pull-up/pull-down resistors which are off by default.
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.
This Signal has a weak internal Pull-down.
4 0: SPI (Default) N18G3 N18G3 4
1: LPC
Notes:
1. The internal Pull-down is disabled after PCH_PWROK is high. 10K_0201_5% 10K_0201_5%
2. This signal is in the primary well.

RH53 2 @ 1 100K_0402_5% SPKR


SPKR [18,45]
Security Classification Compal Secret Data Compal Electronics, Inc.
Top Swap Override Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
0 = Disable � Top Swap�mode. (Default)
STRAP PCH(6/8)GPIO/I2C/UART/STRAP
1 = Enable � Top Swap�mode. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
The internal Pull-down is disabled after PCH_PWROK is high. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 19 of 81
A B C D E
A B C D E

GPIO Group Voltage

GPPA LPC: 3.3V


+1.05VALW
eSPI: 1.8V *
+1.8VS_3VS_PGPPA +1.05VALW
+3VS GPPB
CNP-H +3V_PHVC 3.3V
UH1H GPPC
5.95A AA22 AW9
5.95A RC73 1 @ 2 0_0603_5%
AA23 VCCPRIM_1P051
VCCPRIM_1P052
VCCPRIM_3P32
0.182A
+VCCRTCEXT GPPD 1.8V for SOC_DMIC *
AB20 BF47 +VCCRTCEXT 3.3V for IR_DMIC
HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT
AB22 BG47 +3V_USB2

1U_0201_6.3V6M
AB23 VCCPRIM_1P054 DCPRTC2 GPPE
3.3V

0.1U_0402_10V6K
1 AB27 VCCPRIM_1P055 V23 +3V_SPI
0.095A 1 GPPF

CH62
AB28 VCCPRIM_1P056 VCCPRIM_3P35
close to VCCPRIM balls

CH25
AB30 VCCPRIM_1P057 AN44 0.042A
1 AD20 VCCPRIM_1P058 VCCSPI GPPG 3.3V 1
2 VCCPRIM_1P059
AD23 BC49 2
VCCPRIM_1P0510 VCCRTC1 +3VL_RTC @
AD27 BD49 +3VALW GPPH
AD28 VCCPRIM_1P0511 VCCRTC2
GPPK 3.3V
AD30 VCCPRIM_1P0512 AN21 0.195A +3V_PHVLDO
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8
VCCPRIM_1P0516 VCCPRIM_3P33 +3V_1.8V_PGPPHK GPPI 3.3V Only
+1.05VALW AF27 BB7 0.97A
6.6A VCCPRIM_1P0517 VCCPRIM_3P34
AF30
VCCPRIM_1P0518 AC35 0.262A +3VALW GPPJ

22U_0603_6.3V6M

1U_0201_6.3V6M
6.6A U26 VCCPGPPHK1 AC36 1.8V Only
1 U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A

CH12

CH13
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36 +3V_1.8V_PGPPD
close to VCCPRIM balls VCCPRIM_1P0525 VCCPGPPEF2
GPD 3.3V Only
V27
V28 VCCPRIM_1P0526 AN24 0.14A
2 2
V30 VCCPRIM_1P0527 VCCPGPPD AN26
+1.05V_FUSE V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.334A +3V_1.8V_PGPPA
VCCPRIM_1P0529 VCCPGPPBC2
+1.05V_CNV_HVLDO +3VALW +1.8V_PRIM
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
PLACE 3-5MM FROM PACKAGE EDGE 0.2A AE17 AT44 0.106A

1U_0201_6.3V6M
+1.05V_VCCUSB VCCPRIM_1P0515 VCCPRIM_3P31 BE48

4.7U_0402_6.3V6M
0.42A W22 VCCDSW_3P31 BE49 0.113A +3VALW_HDA 1 1

CH29
+1.05V_VCCDSW VCCDUSB_1P051 VCCDSW_3P32 +3VALW
+1.05V_VCCDSW W23

CH35
VCCDUSB_1P052 BB14 0.00767A
+1.05V_VCCDSW VCCHDA @
+1.05V_VCCCLPLLEBB BG45 AG19 2 2
BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20

1U_0201_6.3V6M
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15
1 +1.05V_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15

CH16
0.015A D1 VCCPRIM_1P86 BB11 0.766A
+1.05VALW +1.05V_FUSE @ VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PRIM Close to BB11
E1
0.213A C49 VCCPRIM_1P0522 AF19 0.882A +1.8V_PHVLDO
2 +1.05V_VCCAMPHYPLL VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH1721 @ 2 0.01_0402_1% (External VRM mode RH172 unmount)
+1.05V_XTAL VCCAMPHYPLL_1P052 VCCPRIM_1P82 +1.8V_PRIM
E49 For DDX03 R02
RH56 1 @ 2 0_0603_5% VCCAMPHYPLL_1P053 0.193A
AG31 +1.05V_FHV1
+1.05V_CNV_HVLDO 0.00428A P2 VCCPRIM_1P0520 AF31 0.0895A
+1.05V_SRC VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05V_FHV0 +1.24V_PRIM_MAR
2 P3 AK22 2
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN
+1.05V_OCPLL1 W20
RH57 1 @ 2 0_0603_5% VCCA_SRC_1P052 Short pins AJ22,AJ23,AK22,AK23 together
+1.05V_OC AJ22

4.7U_0402_6.3V6M
VCCDPHY_1P241 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71 1
0.0198A C1 AJ23 Internal LDO
+1.05V_VCCUSB C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5

CH36
VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19
VCCA_BCLK_1P05 K47 VCCMPHY_SENSE
RH58 1 @ 2 0_0603_5% +1.05V_BCLKPLL2 VCCMPHY_SENSE TP@ TH139 +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY 2
0.021A B1 K46 VSSMPHY_SENSE
VCCAPLL_1P051 VSSMPHY_SENSE TP@ TH138
B2
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053 RH174 1 @ 2 0_0402_5%
0.1U_0402_10V6K

1 CNP-H_BGA874 Rev1.0
RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
CH14

2 +3VALW +1.8V_PRIM
@
+1.05VALW +3V_1.8V_PGPPHK
+1.05V_SRC
+3VALW
+3V_PHVC @
RH139 1 @ 2 0_0603_5% RH146 1 2 0_0402_5%

0.1U_0402_10V6K
RH85 1 @ 2 0_0603_5% RH90 1 @ 2 0_0603_5% 1
+1.05V_VCCCLPLLEBB

CH32
+3V_USB2
+1.05V_OCPLL1
RH59 1 @ 2 0_0603_5% 2
@
RH86 1 @ 2 0_0603_5% RH91 1 @ 2 0_0603_5%
+3V_SPI
0.1U_0201_10V6K

1U_0201_6.3V6M

1 1 +3VALW
CH15

CH21

RH138 1 @ 2 0_0603_5%
2 2

0.1U_0402_10V6K
+3V_PHVLDO 1

CH33
RH125 1 @ 2 0_0603_5%
3 2 3

0.1U_0402_10V6K
@

1U_0201_6.3V6M
+1.05V_VCCAZPLL 1 1
+1.05V_OC

CH30
+3VALW

CH31
RH84 1 @ 2 0_0603_5%
RH87 1 @ 2 0_0603_5% 2 2
@
+3V_1.8V_PGPPD
1P_0402_50V8

0.1U_0402_10V6K
1P_0402_50V8

1 1 1

0.1U_0201_10V6K
CH24

CH22
CH17

1 @

CH34
RH141 1 2 0.01_0402_1% RH1481 @ 2 0_0402_5%
2 2 2
@ @ @
2 +3V_1.8V_PGPPA

+1.05V_BCLKPLL2 RH143 1 @ 2 0_0603_5%


+1.8V_PRIM
+1.8VALW
+1.05V_VCCAMPHYPLL RH88 1 @ 2 0_0603_5%
+3VALW_HDA
1U_0201_6.3V6M

RH61 1 @ 2 0_0603_5% 1
22U_0603_6.3V6M

RH161 1 @ 2 0_0603_5% RH187 1 @ 2 0_0603_5%


CH23
1U_0201_6.3V6M

1
1

CH18

1P_0402_50V8

1P_0402_50V8
2
CH19

1 1
+3VL_RTC +RTCVCC

CH63
CH64
2

@ 2
W=20mils 2 2
+1.05V_FHV1 @ @
RH1861 @ 2 0_0402_5%

RH119 1 @ 2 0_0603_5% 1U_0201_6.3V6M


1
+1.05V_XTAL
CH77
+1.05V_FHV0
2
4 4
RH83 1 @ 2 0_0603_5% RH120 1 @ 2 0_0603_5%
22U_0603_6.3V6M
1

CH20
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(7/8)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 20 of 81
A B C D E
A B C D E

CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14 TP@ TH1
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
VSS VSS VSS VSS RSVD8 TP@ TH2
1 A28 AL17 BG37 M34 U37 TP@ TH3 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
VSS VSS VSS VSS RSVD5 TP@ TH4
A33 AL24 BG48 M5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
VSS VSS VSS VSS RSVD3 TP@ TH5
A4 AL29 C25 N16 R32 TP@ TH6
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
VSS VSS VSS VSS RSVD2 TP@ TH7
A47 AM1 C48 N37 AH14 TP@ TH8
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PREQ# [10]
AA20 AN16 D30 P46 AM5 XDP_PRDY#
VSS VSS VSS VSS PRDY# XDP_PRDY# [10]
AA25 AN34 D33 R12 AM4 PCH_XDP_TRST# [10]
AA27 VSS VSS AN38 D8 VSS VSS R16 CPU_TRST# AK3 PCH_TRIGOUT RH1 1 2 30_0402_5% PCH_TRIGOUT_R
VSS VSS VSS VSS TRIGGER_OUT PCH_TRIGOUT_R [13]
AA28 AP4 E10 R26 AK2 CPU_TRIGOUT_R
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R [13]
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC17 VSS VSS AT21 E33 VSS VSS T4
AC33 VSS VSS AT24 E35 VSS VSS T49
AC38 VSS VSS AT26 E40 VSS VSS T5
AC4 VSS VSS AT29 E42 VSS VSS T7
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AF25 VSS VSS BA14 J47 VSS VSS W28
AF28 VSS VSS BA44 J48 VSS VSS W30
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
VSS VSS
teknisi-indonesia.com
AK27 BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(8/8)GND/RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 21 of 81
A B C D E
5 4 3 2 1

CHANNEL-A BOT REVERSE TYPE


[7]
[7]
DDR_A_CLK0
DDR_A_CLK#0
(4 mm)
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
CK0#(C)
REVERSE
DQ0
DQ1
8
7
DDR_A_D5
DDR_A_D0

Interleaved Memory
DDR_A_CLK1 138 20 DDR_A_D2
[7] DDR_A_CLK1 CK1(T) DQ2
DDR_A_CLK#1 140 21 DDR_A_D3
[7] DDR_A_CLK#1 CK1#(C) DQ3 4 DDR_A_D1
DDR_A_CKE0 109 DQ4 3 DDR_A_D4
[7] DDR_A_CKE0 DDR_A_CKE1 CKE0 DQ5 DDR_A_D6
110 16
TOP: JDIMM1 CONN Non-ECC DIMM [7] DDR_A_D[0..15]
[7] DDR_A_CKE1

[7] DDR_A_CS#0
DDR_A_CS#0 149
CKE1

S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS0 [7]
DDR_A_CS#1 157 11 DDR_A_DQS#0
[7] DDR_A_D[16..31] [7] DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 [7]
162
+3VS +3VS +3VS 165 S2#/C0 28 DDR_A_D8
D [7] DDR_A_D[32..47] S3#/C1 DQ8 DDR_A_D12 D
29
DDR_A_ODT0 155 DQ9 41 DDR_A_D14
[7] DDR_A_D[48..63] [7] DDR_A_ODT0 ODT0 DQ10

1
1

DDR_A_ODT1 161 42 DDR_A_D11


[7] DDR_A_ODT1 ODT1 DQ11 DDR_A_D9
RD1 RD4 RD2 24
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE [7] DDR_A_BG0 DDR_A_BG1 BG0 DQ13 DDR_A_D10
113 38
[7] DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D15
111 141 150 37
+1.2V +1.2V [7] DDR_A_BA0
2

2
2

SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 112 VDD1 VDD11 142 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 [7] DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 [7]
117 147 32
VDD3 VDD13 DDR_A_MA0 DQS1#(C) DDR_A_DQS#1 [7]
118 148 144
VDD4 VDD14 [7] DDR_A_MA0 A0
1

1
123 153 DDR_A_MA1 133 50 DDR_A_D17
VDD5 VDD15 [7] DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D20
124 154 132 49
VDD6 VDD16 [7] DDR_A_MA2 DDR_A_MA3 A2 DQ17 DDR_A_D23
@ RD3 @ RD5 @ RD6 129 159 131 62
VDD7 VDD17 [7] DDR_A_MA3 DDR_A_MA4 A3 DQ18 DDR_A_D18
0_0402_5% 0_0402_5% 0_0402_5% 130 160 128 63
VDD8 VDD18 [7] DDR_A_MA4 DDR_A_MA5 A4 DQ19 DDR_A_D16
135 163 126 46
[7] DDR_A_MA5
2

2
+3VS 136 VDD9 VDD19 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21
VDD10 [7] DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D19
122 58
[7] DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D22
255 258 125 59
VDDSPD VTT +0.6VS [7] DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
[7] DDR_A_MA9 A9 DQS2(T) DDR_A_DQS2 [7]

0.1U_0201_10V6K

2.2U_0402_6.3V6M
164 257 DDR_A_MA10 146 53 DDR_A_DQS#2
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM 2 2
+0.6V_DDR_VREFCA VREFCA VPP1 259
+2.5V [7] DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 [7]
VPP2 [7] DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D25
119 70
[7] DDR_A_MA12 A12 DQ24

CD1
DDR_A_MA13 DDR_A_D28

CD2
1 99 158 71
VSS VSS [7] DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D30
2 102 151 83
SPD ADDRESS FOR CHANNEL A : 1 1 5 VSS
VSS
VSS
VSS
103
[7]
[7]
DDR_A_MA14_WE#
DDR_A_MA15_CAS#
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
156 A14_WE#
A15_CAS#
DQ26
DQ27
84 DDR_A_D31
DDR_A_D24
6 106 152 66
WRITE ADDRESS: 0XA0 9
10
VSS
VSS
VSS
VSS
107
167
[7] DDR_A_MA16_RAS#
DDR_A_ACT# 114
A16_RAS# DQ28
DQ29
67
79
DDR_A_D29
DDR_A_D27
READ ADDRESS: 0XA1 PLACE NEAR TO PIN 14
15
VSS
VSS
VSS
VSS
168
171
[7] DDR_A_ACT#
DDR_A_PAR 143
ACT# DQ30
DQ31
80
76
DDR_A_D26
DDR_A_DQS3
[7] DDR_A_PAR DDR_A_DQS3 [7]
SA0 = 0; SA1 = 0; SA2 = 0. 18
19
VSS
VSS
VSS
VSS
172
175 RD7 2
[7] DDR_A_ALERT#
1 240_0402_1%
DDR_A_ALERT#
DIMM1_CHA_EVENT#
116
134
PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_A_DQS#3
DDR_A_DQS#3 [7]
+1.2V
DDR4 POR OPERATING SPEED: 1867 MT/S 22
23
VSS
VSS
VSS
VSS
176
180
[18,23] DDR_DRAMRST#
108 EVENT#
RESET# DQ32
174
173
DDR_A_D32
DDR_A_D37
VSS VSS DQ33
STRETCH GOAL IS 2133 MT/S 26
27 VSS VSS
181
184 PCH_SMBDATA 254 DQ34
187
186
DDR_A_D35
DDR_A_D39
VSS VSS [18,23] PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_A_D36
30 185 1 253 170
VSS VSS [18,23] PCH_SMBCLK SCL DQ36 DDR_A_D33
C 31 188 CD91 169 C
35 VSS VSS 189 100P_0402_50V8J SA2_CHA_DIM1 166 DQ37 183 DDR_A_D34
36 VSS VSS 192 ESD@ SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_A_D38
Layout Note: Layout Note: VSS VSS 2 SA1 DQ39
39 193 SA0_CHA_DIM1 256 179 DDR_A_DQS4
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 [7]
43 VSS VSS 197
Near JDIMM1 DQS4#(C) DDR_A_DQS#4 [7]
44 VSS VSS 201 92 195 DDR_A_D44
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D45
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*1 VSS VSS CB3_NC DQ43
52 209 88 191 DDR_A_D41
1uF*2 1uF*2 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D40
57 VSS
VSS
VSS
VSS
213 For ECC DIMM 100 CB5_NC
CB6_NC
DQ45
DQ46
203 DDR_A_D46
10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1 1 1 1 60 214 104 204 DDR_A_D47


VSS VSS CB7_NC DQ47
CD4

CD5

CD6

CD8

CD9
CD3

CD7

61 217 97 200 DDR_A_DQS5


VSS VSS DQS8(T) DQS5(T) DDR_A_DQS#5 DDR_A_DQS5 [7]
64 218 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 [7]
65 222
2 2 @ 2 2 @ 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D50
72 VSS VSS 227
+1.2V 33 DM0#/DBI0# DQ49 228 DDR_A_D53
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D55
77 VSS VSS 231 75 DM2#/DBI2# DQ51 211 DDR_A_D52
78 VSS VSS 234 178 DM3#/DBI3# DQ52 212 DDR_A_D49
81 VSS VSS 235 199 DM4#/DBI4# DQ53 224 DDR_A_D54
82 VSS VSS 238 220 DM5#/DBI5# DQ54 225 DDR_A_D51
85 VSS VSS 239 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 [7]
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 [7]
89 244
90 VSS VSS 247
Layout Note: VSS VSS
93 248
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 237 DDR_A_D60
98 VSS VSS 252 DQ56 236 DDR_A_D57
VSS VSS DQ57 249 DDR_A_D62
262 261 DQ58 250 DDR_A_D58
GND GND DQ59 232 DDR_A_D56
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D59
2.2uF*1 DQ62
ME@ 246 DDR_A_D63
B 0.1uF*1 DQ63 242 DDR_A_DQS7 B
DQS7(T) DDR_A_DQS#7 DDR_A_DQS7 [7]
2 2@ 240
DQS7#(C) DDR_A_DQS#7 [7]
CD12
CD11 2.2U_0402_6.3V6M
0.1U_0201_10V6K
Part Number:SP07001FYH0
1 1 Part Value:S SOCKET FOX_AS0A826-H4RB-7H 260P DDR4 LOTES_ADDR0206-P001A
ME@
+1.2V

DIMM Side CPU Side

2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 @ 2 1K_0402_1%

CD13

1
0.1U_0402_10V6K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V 1uF*8 +1.2V 2
1 signals
330uF*1 +1.2V
2

CD15
RD10 CD14 0.022U_0402_25V7K
2
1K_0402_1% 0.1U_0201_10V6K
1
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

2
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16

CD17

CD18

CD19

CD20

CD21

CD22

CD23

+ CD32 RD11
CD26

CD27

CD28

CD29

CD30
CD24

CD31
CD25

330U_D3_2.5VY_R6M 24.9_0402_1%
SGA00006A00
2 2 2 2 2 2 2 @ 2 @ 2 2 2 2 2 2 2 2 2
@

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
DDRIV_CHA: DIMM0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 22 of 81
5 4 3 2 1
5 4 3 2 1

CHANNEL-B BOT STD (4 mm)


TOP: JDIMM3 CONN Non-ECC DIMM Interleaved Memory [8] DDR_B_D[0..15]
[8]
[8]
[8]
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
137
139
138
140
JDIMM3A
CK0(T)
CK0#(C)
CK1(T)
STD
DQ0
DQ1
DQ2
8
7
20
21
DDR_B_D0
DDR_B_D1
DDR_B_D7
DDR_B_D3
[8] DDR_B_CLK#1 CK1#(C) DQ3 DDR_B_D5
4
+3VS +3VS +3VS [8] DDR_B_D[16..31] DDR_B_CKE0 DQ4 DDR_B_D4
109 3
[8] DDR_B_CKE0 DDR_B_CKE1 CKE0 DQ5 DDR_B_D2
110 16
[8] DDR_B_D[32..47] [8] DDR_B_CKE1 CKE1 DQ6 DDR_B_D6
17
DQ7

1
1

DDR_B_CS#0 149 13 DDR_B_DQS0


D [8] DDR_B_D[48..63] [8] DDR_B_CS#0 DDR_B_CS#1 S0# DQS0(T) DDR_B_DQS#0 DDR_B_DQS0 [8] D
RD19 RD21 157 11
[8] DDR_B_CS#1 S1# DQS0#(C) DDR_B_DQS#0 [8]
0_0402_5% @ RD20 @ 0_0402_5% JDIMM3B 162
@ STD S2#/C0 DDR_B_D9
0_0402_5% 165 28
111 141 S3#/C1 DQ8 29 DDR_B_D14
+1.2V +1.2V
2

2
2

SA0_CHB_DIM3 SA1_CHB_DIM3 SA2_CHB_DIM3 112 VDD1 VDD11 142 DDR_B_ODT0 155 DQ9 41 DDR_B_D13
VDD2 VDD12 [8] DDR_B_ODT0 DDR_B_ODT1 ODT0 DQ10 DDR_B_D15
117 147 161 42
VDD3 VDD13 [8] DDR_B_ODT1 ODT1 DQ11 DDR_B_D8
118 148 24
VDD4 VDD14 DQ12
1

1
123 153 DDR_B_BG0 115 25 DDR_B_D10
VDD5 VDD15 [8] DDR_B_BG0 DDR_B_BG1 BG0 DQ13 DDR_B_D11
RD23 124 154 113 38
VDD6 VDD16 [8] DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D12
@ RD22 @ 0_0402_5% @ RD24 129 159 150 37
VDD7 VDD17 [8] DDR_B_BA0 DDR_B_BA1 BA0 DQ15 DDR_B_DQS1
0_0402_5% 0_0402_5% 130 160 145 34
VDD8 VDD18 [8] DDR_B_BA1 BA1 DQS1(T) DDR_B_DQS#1 DDR_B_DQS1 [8]
135 163 32
DDR_B_DQS#1 [8]
2

2
+3VS 136 VDD9 VDD19 DDR_B_MA0 144 DQS1#(C)
VDD10 [8] DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D17
133 50
[8] DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D18
255 258 132 49
VDDSPD VTT +0.6VS [8] DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
[8] DDR_B_MA3 A3 DQ18

2.2U_0402_6.3V6M
164 257 DDR_B_MA4 128 63 DDR_B_D21
+0.6V_DDRB_VREFCA VREFCA VPP1 +2.5V [8] DDR_B_MA4 A4 DQ19

0.1U_0201_10V6K
2 2 259 DDR_B_MA5 126 46 DDR_B_D16
VPP2 [8] DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D22
127 45
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM [8] DDR_B_MA6 A6 DQ21

CD60
DDR_B_MA7 DDR_B_D23

CD61
1 99 122 58
VSS VSS [8] DDR_B_MA7 DDR_B_MA8 A7 DQ22 DDR_B_D20
2 102 125 59
1 1 VSS VSS [8] DDR_B_MA8 DDR_B_MA9 A8 DQ23 DDR_B_DQS2
5 103 121 55
VSS VSS [8] DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 [8]
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107
[8] DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 [8]
VSS VSS [8] DDR_B_MA11 A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168
[8]
[8]
DDR_B_MA12
DDR_B_MA13
DDR_B_MA12
DDR_B_MA13
119
158 A12 DQ24
70
71
DDR_B_D25
DDR_B_D30
VSS VSS A13 DQ25
READ ADDRESS: 0XA3 15
18 VSS
VSS
VSS
VSS
171
172
[8]
[8]
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
151
156 A14_WE#
A15_CAS#
DQ26
DQ27
83
84
DDR_B_D29
DDR_B_D24
DDR_B_MA16_RAS# 152 66 DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
[8] DDR_B_MA16_RAS# A16_RAS# DQ28
DQ29
67 DDR_B_D27
23 180 DDR_B_ACT# 114 79 DDR_B_D31
DDR4 POR OPERATING SPEED: 1867 MT/S 26 VSS
VSS
VSS
VSS
181
[8] DDR_B_ACT# ACT# DQ30
DQ31
80 DDR_B_D26
27 184 DDR_B_PAR 143 76 DDR_B_DQS3
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185
[8] DDR_B_PAR
[8] DDR_B_ALERT#
DDR_B_ALERT#
DIMM3_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
[8]
[8]
31 188 RD25 2 1 240_0402_1% 134
C 35 VSS VSS 189
+1.2V 108 EVENT# 174 DDR_B_D39 C
VSS VSS [18,22] DDR_DRAMRST# RESET# DQ32 DDR_B_D35
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D36
Place near JDIMM3.257,259 Place near JDIMM3.258 VSS VSS 1 DQ34
40 196 CD92 PCH_SMBDATA 254 186 DDR_B_D32
VSS VSS [18,22] PCH_SMBDATA PCH_SMBCLK SDA DQ35 DDR_B_D38
43 197 100P_0402_50V8J 253 170
VSS VSS [18,22] PCH_SMBCLK SCL DQ36 DDR_B_D34
44 201 ESD@ 169
47 VSS VSS 202 2 SA2_CHB_DIM3 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 SA1_CHB_DIM3 260 SA2 DQ38 182 DDR_B_D33
+2.5V 10uF*2 +0.6VS 10uF*1 51 VSS VSS 206
Near JDIMM3 SA0_CHB_DIM3 256 SA1 DQ39 179 DDR_B_DQS4
VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 [8]
52 209 177
1uF*2 1uF*2 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 [8]
57 VSS VSS 213 92 195 DDR_B_D41
VSS VSS CB0_NC DQ40
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 60 214 91 194 DDR_B_D45


61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D46
VSS VSS CB2_NC DQ42
CD62

CD63

CD68
CD64

CD66
CD65

CD67

64 218 105 208 DDR_B_D43


65 VSS VSS 222 88 CB3_NC DQ43 191 DDR_B_D40
2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D44
@ @ 69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D42
72 VSS VSS 227 104 CB6_NC DQ46 204 DDR_B_D47
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_B_DQS#5 DDR_B_DQS5 [8]
77 231 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_B_DQS#5 [8]
78 234
81 VSS VSS 235 216 DDR_B_D51
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V 33 DM0#/DBI0# DQ49 228 DDR_B_D55
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D53
89 VSS VSS 244 75 DM2#/DBI2# DQ51 211 DDR_B_D48
90 VSS VSS 247 178 DM3#/DBI3# DQ52 212 DDR_B_D54
93 VSS VSS 248 199 DM4#/DBI4# DQ53 224 DDR_B_D49
94 VSS VSS 251 220 DM5#/DBI5# DQ54 225 DDR_B_D50
Layout Note: VSS VSS DM6#/DBI6# DQ55
98 252 241 221 DDR_B_DQS6
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 [8]
FROM THE JDIMM3 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 [8]
262 261
GND GND

B FOX_AS0A826-H4SB-7H 237 DDR_B_D56 B


DQ56 236 DDR_B_D57
ME@ DQ57
+0.6V_DDRB_VREFCA 249 DDR_B_D60
2.2uF*1 DQ58 250 DDR_B_D63
0.1uF*1 DQ59 232 DDR_B_D61
Part Number:SP07001CEA0 DQ60 233 DDR_B_D59
2 2@ DQ61
CD70 245 DDR_B_D58
CD69 2.2U_0402_6.3V6M Part Value:S SOCKET FOX_AS0A826-H4SB-7H 260P DDR4 DQ62 246 DDR_B_D62
0.1U_0201_10V6K DQ63 242 DDR_B_DQS7
1 1 +1.2V DQS7(T) DDR_B_DQS#7 DDR_B_DQS7 [8]
240
DQS7#(C) DDR_B_DQS#7 [8]

FOX_AS0A826-H4SB-7H
ME@

Layout Note:
2
DIMM Side CPU Side

2
CD71
Place near JDIMM3 @ RD26
0.1U_0402_10V6K
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ

1
10uF*6
1 RD27 2
+1.2V 1uF*8 +1.2V 2_0402_1%
VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2

2 1
signals
1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

RD28 CD72
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD81 1K_0402_1% 0.1U_0201_10V6K CD82


1
CD74

CD75

CD76

CD77
CD73

CD78

CD79

CD80

0.1U_0201_10V6K 0.022U_0402_25V7K
1 2
CD90
CD83

CD84

CD85

CD86

CD87

CD88

CD89

A A

2
2 2 2 2 2 2 2 @ 2 @ 2 2 2 2 2 2 2 2
RD29
24.9_0402_1%

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIV_CHB: DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 23 of 81
5 4 3 2 1
A B C D E

GC OFF 1.0 GPU Power ON/OFF


1 2 +1V8_AON

RG3
10K_0201_5%

5
VCC
DGPU_HOLD_RST# 1
[16] DGPU_HOLD_RST# IN B DGPU_PEX_RST#
4 RG5371 @ 2 0_0201_5%
OUT Y DGPU_PEX_RST# [25]
2

GND
[16,48,49,50,57] PCI_RST# IN A

1
UG10 RG562
NL17SZ08DFT2G_SC70-5 100K_0402_5%

3
1 1

2
+1.0VS_DGPU

4.7U_0402_6.3V6M
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 1

CG19

CG23

CG24

CG25

CG26
CG20

CG21

CG22
PEX_DVDD

CG27
CG29

CG28
2 2 2 2 2 2 2 2 2 2 2
+1V8_MAIN
PEX_CVDD

2
+1V8_AON
RG1537
10K_0201_5% UV1A @
Under GPU

2
1/22 PCI_EXPRESS

1
RG2 @ +1.0VS_DGPU +1.0VS_DGPU
10K_0201_5% T418 PAD~D BK44
PEX_WAKE_N BB35
PEX_DVDD_1
Near GPU

2
DGPU_PEX_RST#_R

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
RG4 1 @ 2 BK26 BB36

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
1
PEX_RST_N PEX_DVDD_2 BC35
PEX_DVDD_3 1 1 1 1 1 1 1 1 2 2 2 1 1
CLKREQ_PEG#0_R

CG12

CG13

CG14

CG15

CG18
CG11

CG16

CG17
1 3 0_0201_5% BL26 BC36
[15] GPU_CLKREQ4# PEX_CLKREQ_N PEX_DVDD_4

CG6

CG1

CG2
CG5

CG7
BD33

S
QG510 BM26 PEX_DVDD_5 BD36
[15] CLK_PEG_P4 PEX_REFCLK PEX_DVDD_6 2 2 2 2 2 2 2 2 1 1 1 2 2
MESS138W-G_SOT323-3 BM27
[15] CLK_PEG_N4 PEX_REFCLK_N BB33
BG26 PEX_CVDD_1 BC33
[9] PEG_CRX_GTX_P0 PEX_TX0 PEX_CVDD_2
BH26
[9] PEG_CRX_GTX_N0 PEX_TX0_N
BL27
[9] PEG_CTX_C_GRX_P0 PEX_RX0
BK27
[9] PEG_CTX_C_GRX_N0 PEX_RX0_N +1V8_MAIN +1V8_MAIN
BF26
[9] PEG_CRX_GTX_P1 PEX_TX1
BE26 BB26
[9] PEG_CRX_GTX_N1 PEX_TX1_N PEX_HVDD_1
Near GPU

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
BB27

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
BK29 PEX_HVDD_2 BB29
[9] PEG_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD_3 1 1 1 1 1 1 1 1 2 2 2 1 1

CG31

CG34

CG35

CG36

CG37

CG38
CG32

CG33
BL29 BB32
[9] PEG_CTX_C_GRX_N1 PEX_RX1_N PEX_HVDD_4

CG8

CG9

CG10

CG3

CG4
2 BC26 2
BF27 PEX_HVDD_5 BC27
[9] PEG_CRX_GTX_P2 PEX_TX2 PEX_HVDD_6 2 2 2 2 2 2 2 2 1 1 1 2 2
BG27 BC29
[9] PEG_CRX_GTX_N2 PEX_TX2_N PEX_HVDD_7 BC30
BM29 PEX_HVDD_8 BC32
[9] PEG_CTX_C_GRX_P2 PEX_RX2 PEX_HVDD_9
BM30 BD27
[9] PEG_CTX_C_GRX_N2 PEX_RX2_N PEX_HVDD_10 BD30
[9] PEG_CRX_GTX_P3
[9] PEG_CRX_GTX_N3
BG29
BH29 PEX_TX3
PEX_TX3_N
PEX_HVDD_11
Under GPU
BL30
[9] PEG_CTX_C_GRX_P3 PEX_RX3
BK30
[9] PEG_CTX_C_GRX_N3 PEX_RX3_N +1V8_MAIN
BF29
[9] PEG_CRX_GTX_P4 PEX_TX4
BE29
[9] PEG_CRX_GTX_N4 PEX_TX4_N
Under GPU

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
BK32 1 1 1 1 1
[9] PEG_CTX_C_GRX_P4 PEX_RX4

CG41

CG40
BL32
[9] PEG_CTX_C_GRX_N4 PEX_RX4_N

CG45

CG43

CG42
BF30
[9] PEG_CRX_GTX_P5 PEX_TX5 2 2 2 2 2
BG30
[9] PEG_CRX_GTX_N5 PEX_TX5_N BB30 +1V8_MAIN
BM32 PEX_PLL_HVDD

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
[9] PEG_CTX_C_GRX_P5 PEX_RX5
BM33 1 1
[9] PEG_CTX_C_GRX_N5 PEX_RX5_N

CG39

CG30
BG32
[9] PEG_CRX_GTX_P6 PEX_TX6
BH32
[9] PEG_CRX_GTX_N6 PEX_TX6_N 2 2
[9] PEG_CTX_C_GRX_P6
[9] PEG_CTX_C_GRX_N6
BL33
BK33 PEX_RX6
PEX_RX6_N
PEX_HVDD
[9] PEG_CRX_GTX_P7
BF32
BE32 PEX_TX7 PEX_PLL_HVDD
[9] PEG_CRX_GTX_N7

[9] PEG_CTX_C_GRX_P7
BK35
BL35
PEX_TX7_N

PEX_RX7
Under GPU
[9] PEG_CTX_C_GRX_N7 PEX_RX7_N
BF33
[9] PEG_CRX_GTX_P8 PEX_TX8
BG33
[9] PEG_CRX_GTX_N8 PEX_TX8_N

[9] PEG_CTX_C_GRX_P8
BM35
PEX_RX8
1.0VS_DGPU 0.47U 16 PCS 1V8_MAIN 0.47U 12 PCS
BM36
[9] PEG_CTX_C_GRX_N8 PEX_RX8_N

[9] PEG_CRX_GTX_P9
BG35
PEX_TX9
1.0VS_DGPU 10U 3 PCS 1V8_MAIN 10U 3 PCS
BH35
[9] PEG_CRX_GTX_N9 PEX_TX9_N

[9] PEG_CTX_C_GRX_P9
BL36
PEX_RX9
1.0VS_DGPU 4.7U 3 PCS 1V8_MAIN 4.7U 3 PCS
BK36
[9] PEG_CTX_C_GRX_N9 PEX_RX9_N

3 [9] PEG_CRX_GTX_P10
BF35
PEX_TX10
1.0VS_DGPU 22U 2PCS 1V8_MAIN 22U 2PCS 3
BE35
[9] PEG_CRX_GTX_N10 PEX_TX10_N
BK38
[9] PEG_CTX_C_GRX_P10 PEX_RX10
BL38
[9] PEG_CTX_C_GRX_N10 PEX_RX10_N
BF36
[9] PEG_CRX_GTX_P11 PEX_TX11
BG36
[9] PEG_CRX_GTX_N11 PEX_TX11_N
BM38
[9] PEG_CTX_C_GRX_P11 PEX_RX11
BM39
[9] PEG_CTX_C_GRX_N11 PEX_RX11_N
BG38
[9] PEG_CRX_GTX_P12 PEX_TX12
BH38
[9] PEG_CRX_GTX_N12 PEX_TX12_N
BL39
[9] PEG_CTX_C_GRX_P12 PEX_RX12
BK39
[9] PEG_CTX_C_GRX_N12 PEX_RX12_N
BF38
[9] PEG_CRX_GTX_P13 PEX_TX13
BE38
[9] PEG_CRX_GTX_N13 PEX_TX13_N
BK41
[9] PEG_CTX_C_GRX_P13 PEX_RX13
BL41
[9] PEG_CTX_C_GRX_N13 PEX_RX13_N
BF39
[9] PEG_CRX_GTX_P14 PEX_TX14
BG39
[9] PEG_CRX_GTX_N14 PEX_TX14_N
BM41
[9] PEG_CTX_C_GRX_P14 PEX_RX14
BM42
[9] PEG_CTX_C_GRX_N14 PEX_RX14_N
BH41
[9] PEG_CRX_GTX_P15 PEX_TX15
BG41
[9] PEG_CRX_GTX_N15 PEX_TX15_N
BL42 BL44 PEX_TERMP 2 1
[9] PEG_CTX_C_GRX_P15 PEX_RX15 PEX_TERMP
BK42
[9] PEG_CTX_C_GRX_N15 PEX_RX15_N RG23
2.49K_0402_1%

N18E-G3-ES-A1_FCBGA2228

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(1/9) PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 24 of 81
A B C D E
A B C D E

RG1542 1 2 10K_0201_5%
DGPU_PEX_RST# [24]

5
QG6A

G
UV1T @ VGA_SMB_CK2 4 3 PJT138KA 2N SOT363-6
EC_SMB_CK2 [18,41,46,48,51]

D
12/22 MISC 1

2
QG6B For EC
PJT138KA 2N SOT363-6

G
OVERT# BG5 BJ8 VGA_SMB_CK2 VGA_SMB_DA2 1 6
OVERT I2CS_SCL VGA_SMB_DA2 EC_SMB_DA2 [18,41,46,48,51]

D
BH8 For EC
1 I2CS_SDA 1
BF12
TS_VREF BG9 I2CC_SCL_R +1V8_AON
I2CC_SCL BH9 I2CC_SDA_R +1V8_AON
I2CC_SDA For NVVDD VR
RG1543 1 2 10K_0201_5% DGPU_PEX_RST#

1.8K_0402_1%

1.8K_0402_1%
1

1
BG8 RG19 1 2 1.8K_0402_5%
I2CB_SCL

RG1529

RG1530
BF8 RG20 1 2 1.8K_0402_5%
I2CB_SDA

5
BJ1 QG523A

G
2

2
THERMDN I2CC_SCL_R 4 3 PJT138KA 2N SOT363-6
VGA_I2CC_SDA_R_Q [73]

D
BJ2
THERMDP

2
QG523B For NVVDD VR

G
DG2 I2CC_SDA_R 1 6 PJT138KA 2N SOT363-6
VGA_I2CC_SCL_R_Q [73]

D
BD6 RB751S40T1G_SOD523-2
GPIO0 GPU_GC6_FB_EN NVVDD_VID [73]
BB5
GPIO1 GC6_EVENT#_D GPU_GC6_FB_EN [34]
BD1 2 1
GPIO2 GPU_EVENT# [19]
BJ9 BE4
[39] ADC_IN_P ADC_IN GPIO3 1V8_MAIN_EN
BJ11 BE1
[39] ADC_IN_N ADC_IN_N GPIO4 FRAME_LOCK# 1V8_MAIN_EN [34]
BG2
GPIO5 BD2 NVVDD_PSI#
GPIO6 GPU_INV_PWM NVVDD_PSI# [73]
BD7
GPIO7 BH4 +3VS
GPIO8 THERM_ALERT# VRAM_VDD_CTL [77]
BJ3 DG11
GPIO9 BD3 MEM_VREF RB751S40T1G_SOD523-2
GPIO10 MEM_VREF [35,36,37,38]

1
@ T10 PAD~D JTAG_TCLK BK24 BH3 DGPU_ENVDD DGPU_ENVDD RG1555 1 2 10K_0201_5%
JTAG_TMS JTAG_TCK GPIO11 GPU_PROHOT_NV DGPU_ENVDD [41]
@ T11 PAD~D BL23 BE6 2 1 RG517
JTAG_TDI JTAG_TMS GPIO12 GPU_PROHOT [48,65]
@ T12 PAD~D BM23 BB1 10K_0201_5%
@ T13 PAD~D JTAG_TDO BM24 JTAG_TDI GPIO13 BG4 TBTA_HPD_GPU#
JTAG_TDO GPIO14 TBTA_HPD_GPU# [57]

5
JTAG_TRST# BL24 BG1 TBTB_HPD_GPU#
TBTB_HPD_GPU# [57]

2
JTAG_TRST_N GPIO15 BE2

G
GPIO16 BH1 EDP_HPD_GPU# FRAME_LOCK# 4 3
GPIO17 GSYNC# [42]

D
BE3
GPIO18 DP_HPD_GPU# [44]
BK23 BD4 QG506A
NVJTAG_SEL GPIO19 BE5 GPU_FGC6_EN PJT138KA 2N SOT363-6
GPIO20 LCD_BLEN GPU_FGC6_EN [34]
2 BA5 2
GPIO21
1

BB6
RG518 RG26 GPIO22 BG3
10K_0201_5% 10K_0201_5% GPIO23 BD5 DONGLE_DET# PAD~D T417@
GPIO24 BB2 FB_VDD_PSI
GPIO25 FP_FUSE FB_VDD_PSI [77] DGPU_PEX_RST#
BE7 RG1556 1 2 10K_0201_5%
FP_FUSE [29]
2

GPIO26 BA4
GPIO27 ADC_MUX_SEL HDMI_HPD_GPU# [43]
BB4
GPIO28 ADC_MUX_SEL [39]

2
BA3 IDLE_IN_SW
GPIO29 BB3 PAD~D T24 @

G
GPIO30 THERM_ALERT# 1 6
THERM_ALERT#_EC_R [48]

D
1
QG506B
Pin Name Default Function RG1504 PJT138KA 2N SOT363-6
10K_0402_5%
JTAG_TRST L JTAG support N18E-G3-ES-A1_FCBGA2228
DGPU_PEX_RST# RG1559 1 2 10K_0201_5%

2
NVJTAG_SEL L Test Mode --> Disable

OVERT# 1 6 GPU_OVERT#
H Test Mode --> Enable GPU_OVERT# [34]

QG515A
L2N7002DW1T1G 2N SC88-6

+1V8_AON

+3VS
OVERT# RG9 1 2 10K_0201_5%

GC6_EVENT#_D RG8 1 2 10K_0201_5%


1

+3VS
RG566 FRAME_LOCK# RG502 1 2 10K_0201_5%
2.2K_0201_5%
GPU_PROHOT_NV RG16 1 2 10K_0201_5%
1

3 3
2

RG567 VGA_SMB_CK2 RG17 1 2 1.8K_0402_5%


100K_0201_5% TO EC
GPU_ENBKL [41] VGA_SMB_DA2 RG18 1 2 1.8K_0402_5%
+1V8_AON
2

1V8_MAIN_EN RG27 1 2 10K_0201_5%


D
2 G QG525B
1

S
PJT138KA 2N SOT363-6 NVVDD_PSI# RG15 1 2 10K_0201_5%
RG500
1
3

10K_0201_5% THERM_ALERT# RG504 1 2 10K_0201_5%


LCD_BLEN
D
5 G QG525A
S
PJT138KA 2N SOT363-6 ADC_MUX_SEL RG522 1 2 10K_0201_5%
2
4

EDP_HPD_GPU#
3

GPU_FGC6_EN RG21 1 2 10K_0201_5%


QG515B
L2N7002DW1T1G 2N SC88-6 GPU_GC6_FB_EN RG22 1 2 10K_0201_5%
+3VS RG5071 @ 2 0_0201_5% 5
[41] EDP_HPD_GPU VRAM_VDD_CTL RG1539 1 2 10K_0201_5%
4
1

MEM_VREF RG24 1 2 100K_0201_5%


1

+3VS
RG536 RV700 GPU_INV_PWM RG1538 1 @ 2 100K_0201_5%
2.2K_0201_5% 100K_0402_5%
DGPU_ENVDD RG1540 1 @ 2 100K_0201_5%
2
1

RG535 LCD_BLEN RG1541 1 @ 2 100K_0201_5%


100K_0201_5%
GPU_BKL_PWM [41]
2

2 G
D
QG524B
SB00000PV00 Change to SB00000EO00
S
PJT138KA 2N SOT363-6
1
3

GPU_INV_PWM
D
4 5 G
4
S

QG524A
4

PJT138KA 2N SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(2/9) GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 25 of 81
A B C D E
A B C D E

UV1N @

7/22 IFPAB

DL-DVI DVI/HDMI DP

BH11
SDA SDA IFPA_AUX_SDA_N BG11 GPU_DPA_AUXN [57]
SCL SCL IFPA_AUX_SCL GPU_DPA_AUXP [57]
RG36
1K_0402_1% BF21
2 1 IFPAB_RSET BD23 TXC TXC IFPA_L3_N BG21 GPU_DPA_N3 [57]
IFPAB_RSET TXC TXC IFPA_L3 GPU_DPA_P3 [57]

TXD0 TXD0
BG23
1 IFPA_L2_N BH23 GPU_DPA_N2 [57] 1
TXD0 TXD0 IFPA_L2 GPU_DPA_P2 [57]
+IFPX_PLLVDD BD21
IFPAB_PLLVDD
BF23

0.47U_0201_6.3V6K
TXD1 TXD1 IFPA_L1_N BE23 GPU_DPA_N1 [57]
1 TXD1 TXD1 IFPA_L1 GPU_DPA_P1 [57]

CG312
BF24
GDDR6 VRAM Strap2 Strap1 Strap0 RAMCFG
TXD2 TXD2 IFPA_L0_N GPU_DPA_N0 [57]
2 BG24
TXD2 TXD2 IFPA_L0 GPU_DPA_P0 [57] Samsung , K4Z80325BC-HC14 L L L 0X0
Micron , MT61K256M32JE-14:A L L H 0X1
Hynix , H56C8H24MJR-S2C L H L 0X2 +1V8_AON

Under GPU SDA IFPB_AUX_SDA_N


BG12
BH12 GPU_DPB_AUXN [57]
+1V8_AON
SCL IFPB_AUX_SCL GPU_DPB_AUXP [57]
+1.0VS_DGPU

BL18
IFPB_L3_N GPU_DPB_N3 [57]

2
2

2
TXC
BB18 BK18 UV1U @
BB17 IFP_IOVDD_2 TXC IFPB_L3 GPU_DPB_P3 [57] RG80 RG79 RG78 RG83 RG82 RG81 RG84 RG85 RG86
14/22 MISC 2
IFP_IOVDD_1 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 10K_0402_1% 100K_0402_1%
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

1 1 1 1 1 BB20 BK20 X76@ X76@ X76@ GSYNC@ @ BJ4 ROM_CS# @ @ @


IFP_IOVDD_3 TXD3 TXD0 IFPB_L2_N GPU_DPB_N2 [57] ROM_CS_N
CG891

CG892
CG6805

CG893

CG894

BB21 BL20

1
TXD3 TXD0

1
IFP_IOVDD_4 IFPB_L2 GPU_DPB_P2 [57] BK2 ROM_SI
ROM_SI BK4 ROM_SO
2 2 2 2 2 BM20 STRAP0 BL3 ROM_SO BK3 ROM_SCLK 1 2 DGPU_ROM_SCLK
TXD4 TXD1 IFPB_L1_N BM21 GPU_DPB_N1 [57] STRAP1 BL4 STRAP0 ROM_SCLK RG100 33_0402_5%
TXD4 TXD1 IFPB_L1 GPU_DPB_P1 [57] STRAP1
STRAP2 BM4
STRAP3 BM5 STRAP2
STRAP3

2
2

2
BL21 STRAP4 BK5
Under GPU
TXD5 TXD2 IFPB_L0_N GPU_DPB_N0 [57] STRAP4
TXD5 TXD2 BK21 STRAP5 BJ5 @EMI@ RG87 RG88 RG89
IFPB_L0 GPU_DPB_P0 [57] STRAP5 CG895 100K_0402_1% 10K_0402_1% 100K_0402_1%

2
IFPAB 20P_0402_50V8

2
2
@

1
1

1
RG92 RG91 RG90 RG95 RG94 RG93 BF9 GPU_BUFRST# T416
N18E-G3-ES-A1_FCBGA2228 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% BUFRST_N PAD~D
X76@ X76@ X76@ NOGSYNC@ @
+1.0VS_DGPU

1
1
4.7U_0402_6.3V6M

N18E-G3-ES-A1_FCBGA2228
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 SP-08867: Partner must use N18E


CG6809
CG6812

CG6807

CG6806

CG6811
CG6814

CG6813

CG6808

CG6810

GPU Secondary PCI DeviceID for


G-SYNC display enablement.
2 2 2 2 2 2 2 2 2
2 2

Near GPU GSYNC VBIOS ROM


+1V8_AON
+1V8_AON

1
RG74 1
10K_0402_5%
CG66
0.1U_0201_10V6K

Under GPU

2
+IFPX_PLLVDD UV1V @ 2
13/22 XTAL/PLL 33_0402_5% UG34
ROM_CS# RG75 1 2 ROM_CS#_R 1 8
BD12 ROM_SO RG76 1 @ 2 DGPU_ROM_SO_R 2 CS# VCC 7
SP_PLLVDD 0_0402_5% 3 DO(IO1) HOLD#(IO3) 6 DGPU_ROM_SCLK
0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

BC12 4 WP#(IO2) CLK 5 DGPU_ROM_SI 1 2 ROM_SI


1 1 VID_PLLVDD GND DI(IO0)
CG907
CG896

RG77 33_0402_5%
W25Q80EWSSIG_SO8
2 2

U42
GPCPLL_AVDD0
AF11
GPCPLL_AVDD1
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

1 1 1 BB24
XSN_PLLVDD
CG908

CG909

CG910

2 2 2

@ +1V8_AON
RG1497
BJ6 BK6 XTALOUTBUFF_R 1 2
EXT_REFCLK_FL XTAL_OUTBUFF
BL6 BM6
XTAL_IN XTAL_OUT 100K_0402_5%
1
1
1

3 @ 3
RG1498 RG1496 RG98
10K_0402_5% 10K_0402_5% N18E-G3-ES-A1_FCBGA2228 100K_0402_5%

RG99
2
2
2

10M_0402_5%
1 2
@ 1
CG6825 YG1
18P_0402_50V8J
XTALIN 1 3 XTALOUT
2 1 3
2 NC NC 2
CG75 CG76
2 4
12P_0402_50V8J 12P_0402_50V8J
1 1

27MHZ_10PF_7R27000001

TXC SJ1000TQ00

Murata SJ10000UI00

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(3/9) Strap, XTAL, IFP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 26 of 81
A B C D E
A B C D E

1 www.teknisi-indonesia.com 1

RV672
100K_0201_1%
2 1
UV1O @ UV1P @ 2 1
RG1499 8/22 IFPC 9/22 IFPD

2
1K_0402_1%
1 IFPCD_RSET BD20
IFPCD_RSET
HDMI 2.0 eDP DVI/HDMI DP
RV671
100K_0201_1%
DVI/HDMI DP

+IFPX_PLLVDD BD18 BL9 BF11


IFPCD_PLLVDD SDA IFPC_AUX_SDA_N HDMI_CTRLDAT [43] SDA IFPD_AUX_SDA_N GPU_EDP_AUXN [41]
BK9 BE11
SCL IFPC_AUX_SCL HDMI_CTRLCLK [43] SCL IFPD_AUX_SCL GPU_EDP_AUXP [41]
0.47U_0201_6.3V6K

1
CG6503

TXC
BF17 TMDS_TXCN [43] TXC BM14 GPU_EDP_TXN3 [41]
IFPC_L3_N BE17 IFPD_L3_N BM15
TXC IFPC_L3 TMDS_TXCP [43] TXC IFPD_L3 GPU_EDP_TXP3 [41]
2 BF18 BL15
TXD0 IFPC_L2_N TMDS_TX0N [43] TXD0 IFPD_L2_N GPU_EDP_TXN2 [41]
TXD0
BG18 TMDS_TX0P [43] TXD0
BK15 GPU_EDP_TXP2 [41]
IFPC_L2 IFPD_L2
IFPC BG20
IFPD BK17
TXD1 IFPC_L1_N TMDS_TX1N [43] TXD1 IFPD_L1_N GPU_EDP_TXN1 [41]
TXD1 BH20 TMDS_TX1P [43] TXD1 BL17 GPU_EDP_TXP1 [41]
IFPC_L1 IFPD_L1
2
Under GPU TXD2
TXD2
IFPC_L0_N
IFPC_L0
BF20
BE20
TMDS_TX2N [43]
TMDS_TX2P [43]
TXD2
TXD2
IFPD_L0_N
IFPD_L0
BM17
BM18
GPU_EDP_TXN0 [41]
GPU_EDP_TXP0 [41]
2

+1.0VS_DGPU BB23 +1.0VS_DGPU BC18


BC17 IFP_IOVDD_5 BC20 IFP_IOVDD_7
IFP_IOVDD_6 IFP_IOVDD_8

N18E-G3-ES-A1_FCBGA2228 N18E-G3-ES-A1_FCBGA2228

UV1Q @
10/22 IFPE
3
RG1500
1K_0402_1%
mini DP DVI/HDMI DP
3

2 1 IFPEF_RSET BD17 SDA BL8


IFPE_RSET IFPE_AUX_SDA_N mDP_AUX#_SDA [44]
SCL BK8
+1V8_MAIN +IFPX_PLLVDD IFPE_AUX_SCL mDP_AUX_SCL [44]

1 2
Under GPU BD15
TXC IFPE_L3_N
BG14
BH14
GPU_mDP_N3 [44]
IFPE_PLLVDD TXC IFPE_L3 GPU_mDP_P3 [44]
22U_0603_6.3V6M

4.7U_0402_6.3V6M

LG9 BF14
0.47U_0201_6.3V6K

TXD0 IFPE_L2_N GPU_mDP_N2 [44]


PBY160808T-300Y-N_2P 1 1 TXD0 BE14 GPU_mDP_P2 [44]
IFPE_L2
1

CG6507

CG6804

CG6509

TXD1 BF15 GPU_mDP_N1 [44]


IFPE_L1_N BG15
TXD1 GPU_mDP_P1 [44]
2

2 2 IFPE_L1
IFPE
TXD2
BG17 GPU_mDP_N0 [44]
IFPE_L0_N BH17
TXD2 GPU_mDP_P0 [44]
Near GPU IFPE_L0

+1.0VS_DGPU BC21
BC23 IFP_IOVDD_9
IFP_IOVDD_10

N18E-G3-ES-A1_FCBGA2228

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(4/9) eDP, HDMI, DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 27 of 81
A B C D E
A B C D E

UV1R @ USB-C Display Interface


6/22 IFPF/USB-C

USB-C DP
1 1
10K_0201_5% 2 1 RG1505 USB_DVDD BB15 SBU2
BM9
BC15 USB_DVDD_1 IFPF_AUX_SDA_N BM8
USB_DVDD_2 SBU1 IFPF_AUX_SCL

RX1
BK11
IFPF_L3_N BL11
RX1 IFPF_L3
TX1
BM11
IFPF_L2_N BM12
TX1 IFPF_L2
TX2
BL12
IFPF_L1_N BK12
TX2 IFPF_L1
10K_0201_5% 2 1 RG1507 USB_HVDD1 AW10
AW11 USB_HVDD_1 BK14
USB_HVDD_2 RX2 IFPF_L0_N
RX2
BL14
AW9 IFPF_L0
+1V8_AON USB_PLL_HVDD
1 1
1

CG7084 CG7083 CG7082 BA1


22U_0603_6.3V6M 0.47U_0201_6.3V6K 0.47U_0201_6.3V6K USB_L0_N BA2
2

2 2 USB_L0
BA7
USB_L1_N BA8
Near GPU Under GPU USB_L1
10K_0201_5% 2 1 RG1509 USB_VDDP BE12
USB_VDDP +1V8_AON +1V8_AON

2.2K_0201_5%
@

2.2K_0201_5%
@

2
RG1545

RG1546
1

1
BB8
USB_SCL BB7
USB_SDA
2 2
BG6
USB_TERMP0
BH6
USB_TERMP1
BA6
USB_RBIAS IFPF/USB-C

N18E-G3-ES-A1_FCBGA2228

UV1S @ NVLink Interface


11/22 NVHS

AM1
NVHS0_RX0 AN1
NVHS0_RX0_N
AN2
NVHS0_RX1 AN3
NVHS0_RX1_N
AR3
NVHS0_RX2 AR2
NVHS0_RX2_N
AR1
NVHS0_RX3 AT1
NVHS0_RX3_N
RG1506 1 2 10K_0201_5% NVHS_VDD AT10 AT2
AT9 NVHS_DVDD_1 NVHS0_RX4 AT3
AV10 NVHS_DVDD_2 NVHS0_RX4_N
RG1558 N18G1@ AV11 NVHS_DVDD_3 AV3
NVHS_DVDD_4 NVHS0_RX5 AV2
3
AR10 NVHS0_RX5_N 3
+1.0VS_DGPU RG1558 1 N18G2@2 0_0201_5% AT11 NVHS_CVDD_1 AV1
NVHS_CVDD NVHS_CVDD_2 NVHS0_RX6 AW1
RG1557 1 N18G3@2 0_0402_5% NVHS0_RX6_N
0_0201_5% AW2
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

NVHS0_RX7 AW3
RG1558 N18G0@ NVHS0_RX7_N
1 1
N18G3@

N18G3@
CG7103

CG7102

AM7
NVHS0_TX0 AM8
NVHS0_TX0_N
NVHS_CVDD 2 2 AN7
NVHS0_TX1 AN6
NVHS0_TX1_N
0_0201_5%
RG1508 1 2 10K_0201_5% NVHS_HVDD AM10 AR6
AM11 NVHS_HVDD_1 NVHS0_TX2 AR5
AN10 NVHS_HVDD_2 NVHS0_TX2_N
AN11 NVHS_HVDD_3 AR7
AR11 NVHS_HVDD_4 NVHS0_TX3 AR8
NVHS_HVDD_5 NVHS0_TX3_N
RG1547 1 2 10K_0201_5% NVHS_PLL_HVDD AN9 AT7
NVHS_PLL_HVDD NVHS0_TX4 AT6
NVHS0_TX4_N
AV6
NVHS0_TX5 AV5
NVHS0_TX5_N
AV7
NVHS0_TX6 AV8
NVHS0_TX6_N
AW7
NVHS0_TX7 AW6
NVHS0_TX7_N

AM3 AM6
NVHS_TERMP NVHS_REFCLK AM5
NVHS_REFCLK_N

4 AM2 4
EXT_REFCLK_SLI

N18E-G3

NVHS RX/TX N/A

N18E-G3-ES-A1_FCBGA2228

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(5/9) USB-C, NVLink
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 28 of 81
A B C D E
5 4 3 2 1

UV1K @ +1V8_AON
20/22 NC/1V8
+NVVDD +NVVDD +NVVDD +NVVDD +NVVDD +NVVDD
UV1M @ +1.35VS_VGA +1.35VS_VGA BA10
@ UV1J @ UV1L @ 1V8_AON_1 BB14
UV1I 22/22 VDD_3/3
1V8_AON_2
17/22 VDD_1/3 18/22 VDD_2/3 19/22 FBVDDQ BC14
1V8_AON_3
AA13 AE28 AH39 AP23 BG45 R23 AA10 AT43 +1V8_AON
AA14 VDD_001 VDD_076 AE29 AH40 VDD_145 VDD_219 AP24 BG46 VDD_382 VDD_465 R24 AA11 FBVDDQ_01 FBVDDQ_32 K12
AA15 VDD_002 VDD_077 AE30 AJ13 VDD_146 VDD_220 AP25 BG47 VDD_383 VDD_466 R25 AA42 FBVDDQ_02 FBVDDQ_33 K14 UG48
AA16 VDD_003 VDD_078 AE31 AJ40 VDD_147 VDD_221 AP26 BG48 VDD_384 VDD_467 R26 AA43 FBVDDQ_03 FBVDDQ_34 K15 6 1 FP_FUSE_GPU BD14 BD24
AA17 VDD_004 VDD_079 AE32 AK13 VDD_148 VDD_222 AP27 BG49 VDD_385 VDD_468 R27 AC10 FBVDDQ_04 FBVDDQ_35 K17 5 VIN1 VOUT1 2 FP_FUSE_SRC NC_1 BM44
VDD_005 VDD_080 VDD_149 VDD_223 VDD_386 VDD_469 FBVDDQ_05 FBVDDQ_36 VIN2 VOUT2 NC_2

2.21K_0402_1%
2.2U_0402_6.3V6M
AA18 AE33 AK14 AP28 BG50 R28 AC11 K18 BM45
VDD_006 VDD_081 VDD_150 VDD_224 VDD_387 VDD_470 FBVDDQ_06 FBVDDQ_37 NC_3

1
AA19 AE34 AK15 AP29 BG51 R29 AC42 K20 4 3 1
D VDD_007 VDD_082 VDD_151 VDD_225 VDD_388 VDD_471 FBVDDQ_07 FBVDDQ_38 VSS EN D

CG1127

RG253
2.2U_0402_6.3V6M
AA20 AE35 AK16 AP30 BG52 R30 AC43 K21
AA21 VDD_008 VDD_083 AE36 AK17 VDD_152 VDD_226 AP31 BH44 VDD_389 VDD_472 R31 AD10 FBVDDQ_08 FBVDDQ_39 K23 GS7616SC-R_SOT363-6
VDD_009 VDD_084 VDD_153 VDD_227 VDD_390 VDD_473 FBVDDQ_09 FBVDDQ_40 1

CG174
AA22 AE37 AK18 AP32 BH45 R32 AD11 K24
AA23 VDD_010 VDD_085 AE38 AK19 VDD_154 VDD_228 AP33 BH47 VDD_391 VDD_474 R33 AD42 FBVDDQ_10 FBVDDQ_41 K26 2

2
AA24 VDD_011 VDD_086 AE39 AK20 VDD_155 VDD_229 AP34 BH48 VDD_392 VDD_475 R34 AD43 FBVDDQ_11 FBVDDQ_42 K27
AA25 VDD_012 VDD_087 AE40 AK21 VDD_156 VDD_230 AP35 BH49 VDD_393 VDD_476 R35 AF10 FBVDDQ_12 FBVDDQ_43 K29 2 N18E-G3-ES-A1_FCBGA2228
AA26 VDD_013 VDD_088 AF13 AK22 VDD_157 VDD_231 AP36 BH50 VDD_394 VDD_477 R36 AF43 FBVDDQ_13 FBVDDQ_44 K30
AA27 VDD_014 VDD_089 AF14 AK23 VDD_158 VDD_232 AP37 BH51 VDD_395 VDD_478 R37 AG10 FBVDDQ_14 FBVDDQ_45 K32
AA28 VDD_015 VDD_090 AF15 AK24 VDD_159 VDD_233 AP38 BH52 VDD_396 VDD_479 R38 AG11 FBVDDQ_15 FBVDDQ_46 K33
AA29 VDD_016 VDD_091 AF16 AK25 VDD_160 VDD_234 AP39 BJ44 VDD_397 VDD_480 R39 AG42 FBVDDQ_16 FBVDDQ_47 K35
AA30 VDD_017 VDD_092 AF17 AK26 VDD_161 VDD_235 AP40 BJ45 VDD_398 VDD_481 R40 AG43 FBVDDQ_17 FBVDDQ_48 K36
AA31 VDD_018 VDD_093 AF18 AK27 VDD_162 VDD_236 AR13 BJ46 VDD_399 VDD_482 T13 AJ10 FBVDDQ_18 FBVDDQ_49 K38
VDD_019 VDD_094 VDD_163 VDD_237 VDD_400 VDD_483 FBVDDQ_19 FBVDDQ_50 [25] FP_FUSE
AA32 AF24 AK28 AR40 BJ47 T40 AJ11 K39
VDD_020 VDD_095 VDD_164 VDD_238 VDD_401 VDD_484 FBVDDQ_20 FBVDDQ_51

1
AA33 AF25 AK29 AT13 BJ48 U13 AJ42 K41 +1V8_AON
AA34 VDD_021 VDD_096 AF26 AK30 VDD_165 VDD_239 AT14 BJ49 VDD_402 VDD_485 U14 AJ43 FBVDDQ_21 FBVDDQ_52 L14 RG666
AA35 VDD_022 VDD_097 AF30 AK31 VDD_166 VDD_240 AT15 BJ50 VDD_403 VDD_486 U15 AK10 FBVDDQ_22 FBVDDQ_53 L15
VDD_023 VDD_098 VDD_167 VDD_241 VDD_404 VDD_487 FBVDDQ_23 FBVDDQ_54 10K_0201_5%
AA36 AF31 AK32 AT16 BJ51 U16 AK11 L18
AA37 VDD_024 VDD_099 AF32 AK33 VDD_168 VDD_242 AT17 BJ52 VDD_405 VDD_488 U17 AK42 FBVDDQ_24 FBVDDQ_55 L20 1 1 1

2
AA38 VDD_025 VDD_100 AF33 AK34 VDD_169 VDD_243 AT18 BK47 VDD_406 VDD_489 U18 AK43 FBVDDQ_25 FBVDDQ_56 L21
AA39 VDD_026 VDD_101 AF34 AK35 VDD_170 VDD_244 AT19 BK48 VDD_407 VDD_490 U19 AM42 FBVDDQ_26 FBVDDQ_57 L23 CG6815 CG6817 CG6816
AA40 VDD_027 VDD_102 AF40 AK36 VDD_171 VDD_245 AT20 BK49 VDD_408 VDD_491 U20 AM43 FBVDDQ_27 FBVDDQ_58 L24 0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
AB13 VDD_028 VDD_103 AG13 AK37 VDD_172 VDD_246 AT21 BK50 VDD_409 VDD_492 U21 AN43 FBVDDQ_28 FBVDDQ_59 L26 2 2 2
AB40 VDD_029 VDD_104 AG19 AK38 VDD_173 VDD_247 AT22 BK51 VDD_410 VDD_493 U22 AR42 FBVDDQ_29 FBVDDQ_60 L27
AC13 VDD_030 VDD_105 AG20 AK39 VDD_174 VDD_248 AT23 BK52 VDD_411 VDD_494 U23 AR43 FBVDDQ_30 FBVDDQ_61 L30
AC14 VDD_031 VDD_106 AG21 AK40 VDD_175 VDD_249 AT24 BL46 VDD_412 VDD_495 U24 R42 FBVDDQ_31 FBVDDQ_62 L32
AC15
AC16
AC17
VDD_032
VDD_033
VDD_034
VDD_107
VDD_108
VDD_109
AG22
AG23
AG27
AL13
AL40
AM13
VDD_176
VDD_177
VDD_178
VDD_250
VDD_251
VDD_252
AT25
AT26
AT27
BL47
BL48
BL49
VDD_413
VDD_414
VDD_415
VDD_496
VDD_497
VDD_498
U25
U26
U27
R43
U10
U11
FBVDDQ_76
FBVDDQ_77
FBVDDQ_78
FBVDDQ_63
FBVDDQ_64
FBVDDQ_65
L33
L35
L36
Under GPU
AC18 VDD_035 VDD_110 AG28 AM14 VDD_179 VDD_253 AT28 BL50 VDD_416 VDD_499 U28 U43 FBVDDQ_79 FBVDDQ_66 L39
AC19 VDD_036 VDD_111 AG29 AM15 VDD_180 VDD_254 AT29 BL51 VDD_417 VDD_500 U29 V10 FBVDDQ_80 FBVDDQ_67 M10 +1V8_AON
AC20 VDD_037 VDD_112 AG35 AM16 VDD_181 VDD_255 AY26 BL52 VDD_418 VDD_501 U30 V42 FBVDDQ_81 FBVDDQ_68 M43
AC21 VDD_038 VDD_113 AG36 AM17 VDD_182 VDD_321 AY27 BM47 VDD_419 VDD_502 U31 V43 FBVDDQ_82 FBVDDQ_69 P10
AC22 VDD_039 VDD_114 AG37 AM18 VDD_183 VDD_322 AY28 BM48 VDD_420 VDD_503 U32 Y10 FBVDDQ_83 FBVDDQ_70 P11
AC23 VDD_040 VDD_115 AG38 AM19 VDD_184 VDD_323 AY29 BM49 VDD_421 VDD_504 U33 Y11 FBVDDQ_84 FBVDDQ_71 P42
VDD_041 VDD_116 VDD_185 VDD_324 VDD_422 VDD_505 FBVDDQ_85 FBVDDQ_72 1 1 1 1 1 1
AC24 AG39 AM20 AY30 BM50 U34 Y42 P43
AC25 VDD_042 VDD_117 AG40 AM21 VDD_186 VDD_325 AY31 BM51 VDD_423 VDD_506 U35 Y43 FBVDDQ_86 FBVDDQ_73 R10 CG6818 CG6822 CG6823 CG6819 CG6821 CG6820
AC26 VDD_043 VDD_118 AH13 AM22 VDD_187 VDD_326 AY32 N13 VDD_424 VDD_507 U36 FBVDDQ_87 FBVDDQ_74 R11 4.7U_0402_6.3V6M4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
AC27 VDD_044 VDD_119 AH14 AM23 VDD_188 VDD_327 AY33 N14 VDD_425 VDD_508 U37 FBVDDQ_75 2 2 2 2 2 2
C C
AC28 VDD_045 VDD_120 AH15 AM24 VDD_189 VDD_328 AY34 N15 VDD_426 VDD_509 U38
AC29 VDD_046 VDD_121 AH16 AM25 VDD_190 VDD_329 AY35 N16 VDD_427 VDD_510 U39
AC30 VDD_047 VDD_122 AH17 AM26 VDD_191 VDD_330 AY36 N17 VDD_428 VDD_511 U40
AC31 VDD_048 VDD_123 AH18 AM27 VDD_192 VDD_331 AY37 N18 VDD_429 VDD_512 V13 E52 FB_VDDQ_SENSE_R 1 2
AC32
AC33
AC34
VDD_049
VDD_050
VDD_051
VDD_124
VDD_125
VDD_126
AH19
AH20
AH21
AM28
AM29
AM30
VDD_193
VDD_194
VDD_195
VDD_332
VDD_333
VDD_334
AY38
AY39
AY40
N19
N20
N21
VDD_430
VDD_431
VDD_432
VDD_513
VDD_514
VDD_515
V40
W13
W14
FBVDDQ_SENSE RG35 2_0402_1%
FB_VDDQ_SENSE [77]
Near GPU
AC35 VDD_052 VDD_127 AH22 AM31 VDD_196 VDD_335 AY43 N22 VDD_433 VDD_516 W15 P45 FB_VREF
AC36 VDD_053 VDD_128 AH23 AM32 VDD_197 VDD_336 AY45 N23 VDD_434 VDD_517 W16 FB_VREF
AC37 VDD_054 VDD_129 AH24 AM33 VDD_198 VDD_337 BA43 N24 VDD_435 VDD_518 W17 +1.35VS_VGA
AC38 VDD_055 VDD_130 AH25 AM34 VDD_199 VDD_338 BA44 N25 VDD_436 VDD_519 W18
AC39 VDD_056 VDD_131 AH26 AM35 VDD_200 VDD_339 BA45 N26 VDD_437 VDD_520 W19
AC40 VDD_057 VDD_132 AH27 AM36 VDD_201 VDD_340 BA46 N27 VDD_438 VDD_521 W20
AD13 VDD_058 VDD_133 AH28 AM37 VDD_202 VDD_341 BA47 N28 VDD_439 VDD_522 W21 R44 FBCAL_VDDQ RG67 1 2 40.2_0402_1%
AD40 VDD_059 VDD_134 AH29 AM38 VDD_203 VDD_342 BB38 N29 VDD_440 VDD_523 W22 FB_CAL_PD_VDDQ
AE13 VDD_060 VDD_135 AH30 AM39 VDD_204 VDD_343 BB39 N30 VDD_441 VDD_524 W23 P44 FBCAL_GND RG68 1 2 40.2_0402_1%
AE14 VDD_061 VDD_136 AH31 AM40 VDD_205 VDD_344 BB45 N31 VDD_442 VDD_525 W24 FB_CAL_PU_GND
AE15 VDD_062 VDD_137 AH32 AN13 VDD_206 VDD_345 BB46 N32 VDD_443 VDD_526 W25 R45 FBCAL_TERM RG69 1 2 40.2_0402_1%
AE16 VDD_063 VDD_138 AH33 AN40 VDD_207 VDD_346 BB47 N33 VDD_444 VDD_527 W26 FB_CAL_TERM_GND
AE17 VDD_064 VDD_139 AH34 AP13 VDD_208 VDD_347 BB48 N34 VDD_445 VDD_528 W27
AE18 VDD_065 VDD_140 AH35 AP14 VDD_209 VDD_348 BC38 N35 VDD_446 VDD_529 W28
AE19 VDD_066 VDD_141 AH36 AP15 VDD_210 VDD_349 BC39 N36 VDD_447 VDD_530 W29 N18E-G3-ES-A1_FCBGA2228
AE20 VDD_067 VDD_142 AH37 AP16 VDD_211 VDD_350 BC40 N37 VDD_448 VDD_531 W30
AE21 VDD_068 VDD_143 AH38 AP17 VDD_212 VDD_351 BC41 N38 VDD_449 VDD_532 W31 FB_VREF
AE22 VDD_069 VDD_144 AV28 AP18 VDD_213 VDD_352 BC45 N39 VDD_450 VDD_533 W32
AE23 VDD_070 VDD_286 AV29 AP19 VDD_214 VDD_353 BC47 N40 VDD_451 VDD_534 W33
VDD_071 VDD_287 VDD_215 VDD_354 VDD_452 VDD_535

1
AE24 AV30 AP20 BC49 P13 W34 1
AE25 VDD_072 VDD_288 AV31 AP21 VDD_216 VDD_355 BD39 P40 VDD_453 VDD_536 W35 RG59
AE26 VDD_073 VDD_289 AV32 AP22 VDD_217 VDD_356 BE48 R13 VDD_454 VDD_537 W36 CG6826
VDD_074 VDD_290 VDD_218 VDD_369 VDD_455 VDD_538 49.9_0402_1%
AE27 AV33 BD41 BE49 R14 W37 3.9P_0402_50V8C
AT30 VDD_075 VDD_291 AV34 BD46 VDD_357 VDD_370 BE50 R15 VDD_456 VDD_539 W38 2

2
AT31 VDD_256 VDD_292 AV35 BD47 VDD_358 VDD_371 BE51 R16 VDD_457 VDD_540 W39
AT32 VDD_257 VDD_293 AV36 BD48 VDD_359 VDD_372 BE52 R17 VDD_458 VDD_541 W40
AT33 VDD_258 VDD_294 AV37 BD49 VDD_360 VDD_373 BF42 R18 VDD_459 VDD_542 Y13
AT34 VDD_259 VDD_295 AV38 BD50 VDD_361 VDD_374 BF44 R19 VDD_460 VDD_543 Y40
AT35 VDD_260 VDD_296 AV39 BD51 VDD_362 VDD_375 BF45 R20 VDD_461 VDD_544
AT36 VDD_261 VDD_297 AV40 BE41 VDD_363 VDD_376 BF47 R21 VDD_462
B
AT37 VDD_262 VDD_298 AV42 BE42 VDD_364 VDD_377 BF49 R22 VDD_463 B

AT38 VDD_263 VDD_299 AV43 BE43 VDD_365 VDD_378 BF51 VDD_464


AT39 VDD_264 VDD_300 AV44 BE46 VDD_366 VDD_379 BG43
AT40 VDD_265 VDD_301 AW13 BE47 VDD_367 VDD_380 BG44
AT42 VDD_266 VDD_302 AW40 VDD_368 VDD_381
AU13 VDD_267 VDD_303 AW42
AU40 VDD_268 VDD_304 AW43 BK45
VDD_269 VDD_305 VDD_SENSE NVVDD_VDD_SENSE [73]
AU43 AW44 BL45
AV13 VDD_270 VDD_306 AW45 GND_SENSE NVVDD_VSS_SENSE [73]
AV14 VDD_271 VDD_307 AY13
AV15 VDD_272 VDD_308 AY14
AV16 VDD_273 VDD_309 AY15 N18E-G3-ES-A1_FCBGA2228 N18E-G3-ES-A1_FCBGA2228
VDD_274 VDD_310 Sense pin connect to Power Module
AV17 AY16
AV18 VDD_275 VDD_311 AY17 (VGA NCP81611MNTXGES)
AV19 VDD_276 VDD_312 AY18
AV20 VDD_277 VDD_313 AY19
AV21 VDD_278 VDD_314 AY20
AV22 VDD_279 VDD_315 AY21
AV23 VDD_280 VDD_316 AY22
AV24 VDD_281 VDD_317 AY23
AV25 VDD_282 VDD_318 AY24
AV26 VDD_283 VDD_319 AY25
AV27 VDD_284 VDD_320
VDD_285

N18E-G3-ES-A1_FCBGA2228

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(6/9) Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 29 of 81
5 4 3 2 1
5 4 3 2 1

UV1F @
15/22 GND_1/3 UV1G @ UV1H @
16/22 GND_2/3 21/22 GND_3/3
A2 AH6
A26 GND_001 GND_122 AH8 AR20 B52 BL40 N51
A29 GND_002 GND_123 AJ14 AR21 GND_238 GND_361 B7 BL43 GND_482 GND_592 N6
A3 GND_003 GND_124 AJ15 AR22 GND_239 GND_362 BA48 BL5 GND_483 GND_593 N8
A32 GND_004 GND_125 AJ16 AR23 GND_240 GND_363 BA9 BL7 GND_484 GND_594 P14
A50 GND_005 GND_126 AJ17 AR24 GND_241 GND_364 BB49 BM2 GND_485 GND_595 P15
A51 GND_006 GND_127 AJ18 AR25 GND_242 GND_365 BC13 BM3 GND_486 GND_596 P16
AA49 GND_007 GND_128 AJ19 AR26 GND_243 GND_366 BC16 C1 GND_487 GND_597 P17
D
AA8 GND_008 GND_129 AJ2 AR27 GND_244 GND_367 BC19 C29 GND_488 GND_598 P18 D
AB10 GND_009 GND_130 AJ20 AR28 GND_245 GND_368 BC2 C33 GND_489 GND_599 P19
AB14 GND_010 GND_131 AJ21 AR29 GND_246 GND_369 BC22 C5 GND_490 GND_600 P20
AB15 GND_011 GND_132 AJ22 AR30 GND_247 GND_370 BC25 C51 GND_491 GND_601 P21
AB16 GND_012 GND_133 AJ23 AR31 GND_248 GND_371 BC28 C52 GND_492 GND_602 P22
AB17 GND_013 GND_134 AJ24 AR32 GND_249 GND_372 BC31 D10 GND_493 GND_603 P23
AB18 GND_014 GND_135 AJ25 AR33 GND_250 GND_373 BC34 D12 GND_494 GND_604 P24
AB19 GND_015 GND_136 AJ26 AR34 GND_251 GND_374 BC37 D13 GND_495 GND_605 P25
AB2 GND_016 GND_137 AJ27 AR35 GND_252 GND_375 BC4 D16 GND_496 GND_606 P26
AB20 GND_017 GND_138 AJ28 AR36 GND_253 GND_376 BC51 D19 GND_497 GND_607 P27
AB21 GND_018 GND_139 AJ29 AR37 GND_254 GND_377 BC6 D22 GND_498 GND_608 P28
AB22 GND_019 GND_140 AJ30 AR38 GND_255 GND_378 BC8 D24 GND_499 GND_609 P29
AB23 GND_020 GND_141 AJ31 AR39 GND_256 GND_379 BD26 D25 GND_500 GND_610 P30
AB24 GND_021 GND_142 AJ32 AR4 GND_257 GND_380 BD29 D28 GND_501 GND_611 P31
AB25 GND_022 GND_143 AJ33 AR52 GND_258 GND_381 BD32 D30 GND_502 GND_612 P32
AB26 GND_023 GND_144 AJ34 AR9 GND_259 GND_382 BD35 D31 GND_503 GND_613 P33
AB27 GND_024 GND_145 AJ35 AT4 GND_260 GND_383 BD38 D34 GND_504 GND_614 P34
AB28 GND_025 GND_146 AJ36 AT5 GND_261 GND_384 BD52 D37 GND_505 GND_615 P35
AB29 GND_026 GND_147 AJ37 AT51 GND_262 GND_385 BE10 D4 GND_506 GND_616 P36
AB30 GND_027 GND_148 AJ38 AT52 GND_263 GND_386 BE13 D40 GND_507 GND_617 P37
AB31 GND_028 GND_149 AJ39 AT8 GND_264 GND_387 BE15 D43 GND_508 GND_618 P38
AB32 GND_029 GND_150 AJ9 AU10 GND_265 GND_388 BE16 D46 GND_509 GND_619 P39
AB33 GND_030 GND_151 AK1 AU14 GND_266 GND_389 BE18 D49 GND_510 GND_620 P51
AB34 GND_031 GND_152 AK44 AU15 GND_267 GND_390 BE19 D7 GND_511 GND_621 R49
AB35 GND_032 GND_153 AK47 AU16 GND_268 GND_391 BE21 E2 GND_512 GND_622 R52
AB36 GND_033 GND_154 AL10 AU17 GND_269 GND_392 BE22 E4 GND_513 GND_623 T10
AB37 GND_034 GND_155 AL14 AU18 GND_270 GND_393 BE24 E48 GND_514 GND_624 T14
AB38 GND_035 GND_156 AL15 AU19 GND_271 GND_394 BE25 E5 GND_515 GND_625 T15
AB39 GND_036 GND_157 AL16 AU2 GND_272 GND_395 BE27 E51 GND_516 GND_626 T16
AB4 GND_037 GND_158 AL17 AU20 GND_273 GND_396 BE28 E8 GND_517 GND_627 T17
AB43 GND_038 GND_159 AL18 AU21 GND_274 GND_397 BE30 F10 GND_518 GND_628 T18
AB45 GND_039 GND_160 AL19 AU22 GND_275 GND_398 BE31 F13 GND_519 GND_629 T19
AB47 GND_040 GND_161 AL2 AU23 GND_276 GND_399 BE33 F16 GND_520 GND_630 T2
AB49 GND_041 GND_162 AL20 AU24 GND_277 GND_400 BE34 F17 GND_521 GND_631 T20
AB51 GND_042 GND_163 AL21 AU25 GND_278 GND_401 BE36 F19 GND_522 GND_632 T21
AB6 GND_043 GND_164 AL22 AU26 GND_279 GND_402 BE37 F21 GND_523 GND_633 T22
AB8 GND_044 GND_165 AL23 AU27 GND_280 GND_403 BE39 F22 GND_524 GND_634 T23
AD14 GND_045 GND_166 AL24 AU28 GND_281 GND_404 BE40 F25 GND_525 GND_635 T24
C C
AD15 GND_046 GND_167 AL25 AU29 GND_282 GND_405 BF2 F28 GND_526 GND_636 T25
AD16 GND_047 GND_168 AL26 AU30 GND_283 GND_406 BF4 F31 GND_527 GND_637 T26
AD17 GND_048 GND_169 AL27 AU31 GND_284 GND_407 BF41 F34 GND_528 GND_638 T27
AD18 GND_049 GND_170 AL28 AU32 GND_285 GND_408 BF6 F35 GND_529 GND_639 T28
AD19 GND_050 GND_171 AL29 AU33 GND_286 GND_409 BG10 F37 GND_530 GND_640 T29
AD20 GND_051 GND_172 AL30 AU34 GND_287 GND_410 BG13 F40 GND_531 GND_641 T30
AD21 GND_052 GND_173 AL31 AU35 GND_288 GND_411 BG16 F43 GND_532 GND_642 T31
AD22 GND_053 GND_174 AL32 AU36 GND_289 GND_412 BG19 F44 GND_533 GND_643 T32
AD23 GND_054 GND_175 AL33 AU37 GND_290 GND_413 BG22 F46 GND_534 GND_644 T33
AD24 GND_055 GND_176 AL34 AU38 GND_291 GND_414 BG25 F52 GND_535 GND_645 T34
AD25 GND_056 GND_177 AL35 AU39 GND_292 GND_415 BG28 F7 GND_536 GND_646 T35
AD26 GND_057 GND_178 AL36 AU4 GND_293 GND_416 BG31 G2 GND_537 GND_647 T36
AD27 GND_058 GND_179 AL37 AU45 GND_294 GND_417 BG34 G38 GND_538 GND_648 T37
AD28 GND_059 GND_180 AL38 AU47 GND_295 GND_418 BG37 G4 GND_539 GND_649 T38
AD29 GND_060 GND_181 AL39 AU49 GND_296 GND_419 BG40 G47 GND_540 GND_650 T39
AD30 GND_061 GND_182 AL4 AU51 GND_297 GND_420 BG42 G49 GND_541 GND_651 T4
AD31 GND_062 GND_183 AL43 AU6 GND_298 GND_421 BG7 G51 GND_542 GND_652 T43
AD32 GND_063 GND_184 AL45 AU8 GND_299 GND_422 BH15 G6 GND_543 GND_653 T45
AD33 GND_064 GND_185 AL47 AV4 GND_300 GND_423 BH18 H1 GND_544 GND_654 T47
AD34 GND_065 GND_186 AL49 AV45 GND_301 GND_424 BH2 H10 GND_545 GND_655 T49
AD35 GND_066 GND_187 AL51 AV9 GND_302 GND_425 BH21 H13 GND_546 GND_656 T51
AD36 GND_067 GND_188 AL6 AW14 GND_303 GND_426 BH24 H16 GND_547 GND_657 T6
AD37 GND_068 GND_189 AL8 AW15 GND_304 GND_427 BH27 H19 GND_548 GND_658 T8
AD38 GND_069 GND_190 AM4 AW16 GND_305 GND_428 BH30 H22 GND_549 GND_659 U7
AD39 GND_070 GND_191 AM9 AW17 GND_306 GND_429 BH33 H25 GND_550 GND_660 U9
AD44 GND_071 GND_192 AN14 AW18 GND_307 GND_430 BH36 H28 GND_551 GND_661 V14
AE10 GND_072 GND_193 AN15 AW19 GND_308 GND_431 BH39 H31 GND_552 GND_662 V15
AE2 GND_073 GND_194 AN16 AW20 GND_309 GND_432 BH42 H34 GND_553 GND_663 V16
AE4 GND_074 GND_195 AN17 AW21 GND_310 GND_433 BH5 H37 GND_554 GND_664 V17
AE43 GND_075 GND_196 AN18 AW22 GND_311 GND_434 BJ10 H40 GND_555 GND_665 V18
AE45 GND_076 GND_197 AN19 AW23 GND_312 GND_435 BJ12 H43 GND_556 GND_666 V19
AE47 GND_077 GND_198 AN20 AW24 GND_313 GND_436 BJ13 J1 GND_557 GND_667 V20
AE49 GND_078 GND_199 AN21 AW25 GND_314 GND_437 BJ14 J12 GND_558 GND_668 V21
AE51 GND_079 GND_200 AN22 AW26 GND_315 GND_438 BJ15 J17 GND_559 GND_669 V22
AE6 GND_080 GND_201 AN23 AW27 GND_316 GND_439 BJ16 J20 GND_560 GND_670 V23
AE8 GND_081 GND_202 AN24 AW28 GND_317 GND_440 BJ17 J38 GND_561 GND_671 V24
AF1 GND_082 GND_203 AN25 AW29 GND_318 GND_441 BJ18 J49 GND_562 GND_672 V25
B
AF19 GND_083 GND_204 AN26 AW30 GND_319 GND_442 BJ19 J52 GND_563 GND_673 V26
B
AF20 GND_084 GND_205 AN27 AW31 GND_320 GND_443 BJ20 K13 GND_564 GND_674 V27
AF21 GND_085 GND_206 AN28 AW32 GND_321 GND_444 BJ21 K16 GND_565 GND_675 V28
AF22 GND_086 GND_207 AN29 AW33 GND_322 GND_445 BJ22 K19 GND_566 GND_676 V29
AF23 GND_087 GND_208 AN30 AW34 GND_323 GND_446 BJ23 K2 GND_567 GND_677 V30
AF27 GND_088 GND_209 AN31 AW35 GND_324 GND_447 BJ24 K22 GND_568 GND_678 V31
AF28 GND_089 GND_210 AN32 AW36 GND_325 GND_448 BJ25 K25 GND_569 GND_679 V32
AF29 GND_090 GND_211 AN33 AW37 GND_326 GND_449 BJ26 K28 GND_570 GND_680 V33
AF35 GND_091 GND_212 AN34 AW38 GND_327 GND_450 BJ27 K31 GND_571 GND_681 V34
AF36 GND_092 GND_213 AN35 AW39 GND_328 GND_451 BJ28 K34 GND_572 GND_682 V35
AF37 GND_093 GND_214 AN36 AW4 GND_329 GND_452 BJ29 K37 GND_573 GND_683 V36
AF38 GND_094 GND_215 AN37 AW46 GND_330 GND_453 BJ30 K4 GND_574 GND_684 V37
AF39 GND_095 GND_216 AN38 AW5 GND_331 GND_454 BJ31 K40 GND_575 GND_685 V38
AF45 GND_096 GND_217 AN39 AW52 GND_332 GND_455 BJ32 K45 GND_576 GND_686 V39
AF5 GND_097 GND_218 AN4 AW8 GND_333 GND_456 BJ33 K47 GND_577 GND_687 V49
AG14 GND_098 GND_219 AN5 AY10 GND_334 GND_457 BJ34 K49 GND_578 GND_688 V52
AG15 GND_099 GND_220 AN8 AY2 GND_335 GND_458 BJ35 K51 GND_579 GND_689 W10
AG16 GND_100 GND_221 AP10 AY4 GND_336 GND_459 BJ36 K6 GND_580 GND_690 W2
AG17 GND_101 GND_222 AP2 AY47 GND_337 GND_460 BJ37 K8 GND_581 GND_691 W4
AG18 GND_102 GND_223 AP4 AY49 GND_338 GND_461 BJ38 M52 GND_582 GND_692 W43
AG24 GND_103 GND_224 AP43 AY51 GND_339 GND_462 BJ39 M6 GND_583 GND_693 Y9
AG25 GND_104 GND_225 AP45 AY6 GND_340 GND_463 BJ40 N10 GND_584 GND_726
AG26 GND_105 GND_226 AP47 AY8 GND_341 GND_464 BJ41 N2 GND_585
AG3 GND_106 GND_227 AP49 B1 GND_342 GND_465 BJ42 N4 GND_586
AG30 GND_107 GND_228 AP51 B10 GND_343 GND_466 BJ43 N43 GND_587
AG31 GND_108 GND_229 AP6 B13 GND_344 GND_467 BJ7 N45 GND_588
AG32 GND_109 GND_230 AP8 B16 GND_345 GND_468 BK1 N47 GND_589
AG33 GND_110 GND_231 AR14 B19 GND_346 GND_469 BL1 N49 GND_590
AG34 GND_111 GND_232 AR15 B2 GND_347 GND_470 BL10 BL37 GND_591
AG44 GND_112 GND_233 AR16 B22 GND_348 GND_471 BL13 GND_481
AH10 GND_113 GND_234 AR17 B25 GND_349 GND_472 BL16
AH2 GND_114 GND_235 AR18 B28 GND_350 GND_473 BL19 N18E-G3-ES-A1_FCBGA2228
AH4 GND_115 GND_236 AR19 B31 GND_351 GND_474 BL2
AH43 GND_116 GND_237 BL34 B34 GND_352 GND_475 BL22
AH45 GND_117 GND_480 BC24 B37 GND_353 GND_476 BL25
AH47 GND_118 GND_F B40 GND_354 GND_477 BL28
AH49 GND_119 B43 GND_355 GND_478 BL31
AH51 GND_120 B46 GND_356 GND_479 B5
A A
GND_121 B48 GND_357 GND_359 B51
GND_358 GND_360
N18E-G3-ES-A1_FCBGA2228
N18E-G3-ES-A1_FCBGA2228

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(7/9) GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 30 of 81
5 4 3 2 1
A B C D E

UV1B @ UV1C @
2/22 FBA 3/22 FBB

U51 Y51 H32 B35


[35] FB_A_D0 FBA_D0 FBA_CMD0 FB_A_CMD1 FB_A_CMD0 [35] [36] FB_B_D0 FBB_D0 FBB_CMD0 FB_B_CMD1 FB_B_CMD0 [36]
U48 Y52 D32 A35
[35] FB_A_D1 FBA_D1 FBA_CMD1 FB_A_CMD1 [35] [36] FB_B_D1 FBB_D1 FBB_CMD1 FB_B_CMD1 [36]
U50 Y49 A33 D35
[35] FB_A_D2 FBA_D2 FBA_CMD2 FB_A_CMD2 [35] [36] FB_B_D2 FBB_D2 FBB_CMD2 FB_B_CMD2 [36]
U49 AA52 B32 A36
1 [35] FB_A_D3 FBA_D3 FBA_CMD3 FB_A_CMD3 [35] [36] FB_B_D3 FBB_D3 FBB_CMD3 FB_B_CMD3 [36] 1
R51 AA51 E32 B36
[35] FB_A_D4 FBA_D4 FBA_CMD4 FB_A_CMD4 [35] [36] FB_B_D4 FBB_D4 FBB_CMD4 FB_B_CMD4 [36]
R50 AA50 G32 C36
[35] FB_A_D5 FBA_D5 FBA_CMD5 FB_A_CMD5 [35] [36] FB_B_D5 FBB_D5 FBB_CMD5 FB_B_CMD5 [36]
R47 AC50 J30 C38
[35] FB_A_D6 FBA_D6 FBA_CMD6 FB_A_CMD6 [35] [36] FB_B_D6 FBB_D6 FBB_CMD6 FB_B_CMD6 [36]
U46 AC51 F32 B38
[35] FB_A_D7 FBA_D7 FBA_CMD7 FB_A_CMD7 [35] [36] FB_B_D7 FBB_D7 FBB_CMD7 FB_B_CMD7 [36]
V46 AC52 H36 A38
[35] FB_A_D8 FBA_D8 FBA_CMD8 FB_A_CMD8 [35] [36] FB_B_D8 FBB_D8 FBB_CMD8 FB_B_CMD8 [36]
Y45 AC49 G36 D38
[35] FB_A_D9 FBA_D9 FBA_CMD9 FB_A_CMD9 [35] [36] FB_B_D9 FBB_D9 FBB_CMD9 FB_B_CMD9 [36]
Y47 AD52 J36 A39
[35] FB_A_D10 FBA_D10 FBA_CMD10 FB_A_CMD10 [35] [36] FB_B_D10 FBB_D10 FBB_CMD10 FB_B_CMD10 [36]
Y46 AD51 F36 B39
[35] FB_A_D11 FBA_D11 FBA_CMD11 FB_A_CMD11 [35] [36] FB_B_D11 FBB_D11 FBB_CMD11 FB_B_CMD11 [36]
V50 AD50 F33 C39
[35] FB_A_D12 FBA_D12 FBA_CMD12 FB_A_CMD13 FB_A_CMD12 [35] [36] FB_B_D12 FBB_D12 FBB_CMD12 FB_B_CMD13 FB_B_CMD12 [36]
V47 AF50 D33 C41
[35] FB_A_D13 FBA_D13 FBA_CMD13 FB_A_CMD13 [35] [36] FB_B_D13 FBB_D13 FBB_CMD13 FB_B_CMD13 [36]
U52 AF51 J32 B41
[35] FB_A_D14 FBA_D14 FBA_CMD14 FB_A_CMD14 [35] [36] FB_B_D14 FBB_D14 FBB_CMD14 FB_B_CMD14 [36]
V51 AF52 G33 A41
[35] FB_A_D15 FBA_D15 FBA_CMD15 FB_A_CMD15 [35] [36] FB_B_D15 FBB_D15 FBB_CMD15 FB_B_CMD15 [36]
AJ44 AN50 E45 B49
[35] FB_A_D16 FBA_D16 FBA_CMD16 FB_A_CMD17 FB_A_CMD16 [35] [36] FB_B_D16 FBB_D16 FBB_CMD16 FB_B_CMD17 FB_B_CMD16 [36]
AG48 AN51 D45 A49
[35] FB_A_D17 FBA_D17 FBA_CMD17 FB_A_CMD17 [35] [36] FB_B_D17 FBB_D17 FBB_CMD17 FB_B_CMD17 [36]
AJ45 AN52 F45 A48
[35] FB_A_D18 FBA_D18 FBA_CMD18 FB_A_CMD18 [35] [36] FB_B_D18 FBB_D18 FBB_CMD18 FB_B_CMD18 [36]
AG49 AM49 G45 D47
[35] FB_A_D19 FBA_D19 FBA_CMD19 FB_A_CMD19 [35] [36] FB_B_D19 FBB_D19 FBB_CMD19 FB_B_CMD19 [36]
AF46 AM52 D42 A47
[35] FB_A_D20 FBA_D20 FBA_CMD20 FB_A_CMD20 [35] [36] FB_B_D20 FBB_D20 FBB_CMD20 FB_B_CMD20 [36]
AF47 AM51 E42 B47
[35] FB_A_D21 FBA_D21 FBA_CMD21 FB_A_CMD21 [35] [36] FB_B_D21 FBB_D21 FBB_CMD21 FB_B_CMD21 [36]
AF48 AM50 F42 C47
[35] FB_A_D22 FBA_D22 FBA_CMD22 FB_A_CMD22 [35] [36] FB_B_D22 FBB_D22 FBB_CMD22 FB_B_CMD22 [36]
AD47 AK50 H41 C45
[35] FB_A_D23 FBA_D23 FBA_CMD23 FB_A_CMD23 [35] [36] FB_B_D23 FBB_D23 FBB_CMD23 FB_B_CMD23 [36]
AD49 AK51 E41 B45
[35] FB_A_D24 FBA_D24 FBA_CMD24 FB_A_CMD24 [35] [36] FB_B_D24 FBB_D24 FBB_CMD24 FB_B_CMD24 [36]
AD48 AK52 F39 A45
[35] FB_A_D25 FBA_D25 FBA_CMD25 FB_A_CMD25 [35] [36] FB_B_D25 FBB_D25 FBB_CMD25 FB_B_CMD25 [36]
AC46 AJ49 E39 D44
[35] FB_A_D26 FBA_D26 FBA_CMD26 FB_A_CMD26 [35] [36] FB_B_D26 FBB_D26 FBB_CMD26 FB_B_CMD26 [36]
AC47 AJ52 D39 A44
[35] FB_A_D27 FBA_D27 FBA_CMD27 FB_A_CMD27 [35] [36] FB_B_D27 FBB_D27 FBB_CMD27 FB_B_CMD27 [36]
AA47 AJ51 F38 B44
[35] FB_A_D28 FBA_D28 FBA_CMD28 FB_A_CMD29 FB_A_CMD28 [35] [36] FB_B_D28 FBB_D28 FBB_CMD28 FB_B_CMD29 FB_B_CMD28 [36]
AA46 AJ50 E38 C44
[35] FB_A_D29 FBA_D29 FBA_CMD29 FB_A_CMD29 [35] [36] FB_B_D29 FBB_D29 FBB_CMD29 FB_B_CMD29 [36]
AA45 AG50 D36 C42
[35] FB_A_D30 FBA_D30 FBA_CMD30 FB_A_CMD30 [35] [36] FB_B_D30 FBB_D30 FBB_CMD30 FB_B_CMD30 [36]
Y44 AG51 E36 B42
[35] FB_A_D31 FBA_D31 FBA_CMD31 FB_A_CMD31 [35] +1.35VS_VGA [36] FB_B_D31 FBB_D31 FBB_CMD31 FB_B_CMD31 [36] +1.35VS_VGA
AW51 AF49 M50 D41
[35] FB_A_D32 FBA_D32 FBA_CMD32 FB_A_CMD32 [35] [36] FB_B_D32 FBB_D32 FBB_CMD32 FB_B_CMD32 [36]
BA52 AG52 @ P48 A42 @
[35] FB_A_D33 FBA_D33 FBA_CMD33 FB_A_DEBUG0 FB_A_CMD33 [35] [36] FB_B_D33 FBB_D33 FBB_CMD33 FB_B_DEBUG0 FB_B_CMD33 [36]
AW50 Y50 1 RG1478 2 60.4_0402_1% M51 C35 1 RG1446 2 60.4_0402_1%
[35] FB_A_D34 FBA_D34 FBA_CMD34 FB_A_DEBUG1 [36] FB_B_D34 FBB_D34 FBB_CMD34 FB_B_DEBUG1
BA51 AR50 1 RG1476 2 60.4_0402_1% M49 B50 1 RG1451 2 60.4_0402_1%
[35] FB_A_D35 FBA_D35 FBA_CMD35 [36] FB_B_D35 FBB_D35 FBB_CMD35
BA50 @ P47 @
[35] FB_A_D36 FBA_D36 [36] FB_B_D36 FBB_D36
BB50 P52
[35] FB_A_D37 FBA_D37 [36] FB_B_D37 FBB_D37
BA49 R46
[35] FB_A_D38 FBA_D38 [36] FB_B_D38 FBB_D38
AW49 AA44 P46 J35
[35] FB_A_D39 FBA_D39 FBA_DBG_RFU1 [36] FB_B_D39 FBB_D39 FBB_DBG_RFU1
AV48 AN44 L50 J41
[35] FB_A_D40 FBA_D40 FBA_DBG_RFU2 [36] FB_B_D40 FBB_D40 FBB_DBG_RFU2
2 AT49 L51 2
[35] FB_A_D41 FBA_D41 [36] FB_B_D41 FBB_D41
AT47 L52
[35] FB_A_D42 FBA_D42 [36] FB_B_D42 FBB_D42
AT48 L49
[35] FB_A_D43 FBA_D43 [36] FB_B_D43 FBB_D43
AT46 AG45 M46 H42
[35] FB_A_D44 FBA_D44 FBA_CLK0 FB_A_CLK0 [35] [36] FB_B_D44 FBB_D44 FBB_CLK0 FB_B_CLK0 [36]
AV51 AG46 L47 G42
[35] FB_A_D45 FBA_D45 FBA_CLK0_N FB_A_CLK#0 [35] [36] FB_B_D45 FBB_D45 FBB_CLK0_N FB_B_CLK#0 [36]
AV52 AK46 M48 F47
[35] FB_A_D46 FBA_D46 FBA_CLK1 FB_A_CLK1 [35] [36] FB_B_D46 FBB_D46 FBB_CLK1 FB_B_CLK1 [36]
AV49 AK45 M47 E47
[35] FB_A_D47 FBA_D47 FBA_CLK1_N FB_A_CLK#1 [35] [36] FB_B_D47 FBB_D47 FBB_CLK1_N FB_B_CLK#1 [36]
AJ48 D48
[35] FB_A_D48 FBA_D48 [36] FB_B_D48 FBB_D48
AJ46 C50
[35] FB_A_D49 FBA_D49 [36] FB_B_D49 FBB_D49
AJ47 C48
[35] FB_A_D50 FBA_D50 [36] FB_B_D50 FBB_D50
AK49 C49
[35] FB_A_D51 FBA_D51 [36] FB_B_D51 FBB_D51
AM47 E49
[35] FB_A_D52 FBA_D52 [36] FB_B_D52 FBB_D52
AM46 E50
[35] FB_A_D53 FBA_D53 [36] FB_B_D53 FBB_D53
AN48 F49
[35] FB_A_D54 FBA_D54 [36] FB_B_D54 FBB_D54
AN49 F48
[35] FB_A_D55 FBA_D55 [36] FB_B_D55 FBB_D55
AM44 U45 F50 J33
[35] FB_A_D56 FBA_D56 FBA_WCK01 FB_A_WCK01 [35] [36] FB_B_D56 FBB_D56 FBB_WCK01 FB_B_WCK01 [36]
AM45 U44 D52 H33
[35] FB_A_D57 FBA_D57 FBA_WCK01_N FB_A_WCK#01 [35] [36] FB_B_D57 FBB_D57 FBB_WCK01_N FB_B_WCK#01 [36]
AN45 V45 J50 G35
[35] FB_A_D58 FBA_D58 FBA_WCKB01 FB_A_WCKB01 [35] [36] FB_B_D58 FBB_D58 FBB_WCKB01 FB_B_WCKB01 [36]
AN46 V44 H48 H35
[35] FB_A_D59 FBA_D59 FBA_WCKB01_N FB_A_WCKB#01 [35] [36] FB_B_D59 FBB_D59 FBB_WCKB01_N FB_B_WCKB#01 [36]
AR48 AC45 H51 J39
[35] FB_A_D60 FBA_D60 FBA_WCK23 FB_A_WCK23 [35] [36] FB_B_D60 FBB_D60 FBB_WCK23 FB_B_WCK23 [36]
AN47 AC44 J51 H39
[35] FB_A_D61 FBA_D61 FBA_WCK23_N FB_A_WCK#23 [35] [36] FB_B_D61 FBB_D61 FBB_WCK23_N FB_B_WCK#23 [36]
AR47 AD46 H49 F41
[35] FB_A_D62 FBA_D62 FBA_WCKB23 FB_A_WCKB23 [35] [36] FB_B_D62 FBB_D62 FBB_WCKB23 FB_B_WCKB23 [36]
AR46 AD45 H52 G41
[35] FB_A_D63 FBA_D63 FBA_WCKB23_N FB_A_WCKB#23 [35] [36] FB_B_D63 FBB_D63 FBB_WCKB23_N FB_B_WCKB#23 [36]
AV47 L46
FBA_WCK45 FB_A_WCK45 [35] FBB_WCK45 FB_B_WCK45 [36]
AV46 L45
FBA_WCK45_N FB_A_WCK#45 [35] FBB_WCK45_N FB_B_WCK#45 [36]
U47 AW48 C32 M44
[35] FB_A_DBI0 FBA_DQM0 FBA_WCKB45 FB_A_WCKB45 [35] [36] FB_B_DBI0 FBB_DQM0 FBB_WCKB45 FB_B_WCKB45 [36]
Y48 AW47 E33 M45
[35] FB_A_DBI1 FBA_DQM1 FBA_WCKB45_N FB_A_WCKB#45 [35] [36] FB_B_DBI1 FBB_DQM1 FBB_WCKB45_N FB_B_WCKB#45 [36]
AG47 AR45 E44 H47
[35] FB_A_DBI2 FBA_DQM2 FBA_WCK67 FB_A_WCK67 [35] [36] FB_B_DBI2 FBB_DQM2 FBB_WCK67 FB_B_WCK67 [36]
AC48 AR44 G39 H46
[35] FB_A_DBI3 FBA_DQM3 FBA_WCK67_N FB_A_WCK#67 [35] [36] FB_B_DBI3 FBB_DQM3 FBB_WCK67_N FB_B_WCK#67 [36]
BB51 AT45 P49 J47
[35] FB_A_DBI4 FBA_DQM4 FBA_WCKB67 FB_A_WCKB67 [35] [36] FB_B_DBI4 FBB_DQM4 FBB_WCKB67 FB_B_WCKB67 [36]
AV50 AT44 L48 J46
[35] FB_A_DBI5 FBA_DQM5 FBA_WCKB67_N FB_A_WCKB#67 [35] [36] FB_B_DBI5 FBB_DQM5 FBB_WCKB67_N FB_B_WCKB#67 [36]
AM48 D50
[35] FB_A_DBI6 FBA_DQM6 [36] FB_B_DBI6 FBB_DQM6
AR49 H50
[35] FB_A_DBI7 FBA_DQM7 [36] FB_B_DBI7 FBB_DQM7

R48 B33
[35] FB_A_EDC0 FBA_DQS_WP0 [36] FB_B_EDC0 FBB_DQS_WP0
V48 E35
[35] FB_A_EDC1 FBA_DQS_WP1 +FBX_PLLAVDD +1V8_MAIN [36] FB_B_EDC1 FBB_DQS_WP1 +FBX_PLLAVDD
AF44 G44
3 [35] FB_A_EDC2 FBA_DQS_WP2 [36] FB_B_EDC2 FBB_DQS_WP2 3
AA48 H38
[35] FB_A_EDC3 FBA_DQS_WP3 [36] FB_B_EDC3 FBB_DQS_WP3
BB52 100MHz P50
[35] FB_A_EDC4 FBA_DQS_WP4 [36] FB_B_EDC4 FBB_DQS_WP4
AT50 J48
[35] FB_A_EDC5
AK48 FBA_DQS_WP5 30ohm, Bead [36] FB_B_EDC5
D51 FBB_DQS_WP5
[35] FB_A_EDC6 FBA_DQS_WP6 [36] FB_B_EDC6 FBB_DQS_WP6
AR51 AN42 1 2 F51 L38
[35] FB_A_EDC7 FBA_DQS_WP7 FBA_PLL_AVDD [36] FB_B_EDC7 FBB_DQS_WP7 FBB_PLL_AVDD
22U_0603_6.3V6M
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

LG6
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
W45 1 1 1 PBY160808T-300Y-N_2P Y16 1
GND_694 GND_702
1
CG61

CG64

CG63

CG62

CG569
W47 Y17
W49 GND_695 Y18 GND_703
W51 GND_696 Y19 GND_704
2

W6 GND_697 2 2 2 Y20 GND_705 2


W8 GND_698 Y21 GND_706
Y14 GND_699 Y22 GND_707
+FBX_PLLAVDD Y15 GND_700 Y23 GND_708
GND_701 GND_709

AF42
L29 FB_REFPLL_AVDD0 Under GPU Near GPU Under GPU
0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

FB_REFPLL_AVDD1
1 1
CG60
CG59

N18E-G3-ES-A1_FCBGA2228 +1.35VS_VGA +1.35VS_VGA N18E-G3-ES-A1_FCBGA2228


2 2
10K_0402_1%

10K_0402_1%

10K_0402_1%
10K_0402_1%
1

1
1

1
RG1479

RG1483

RG1484
RG1480

For CKE_A teknisi-indonesia.com


Under GPU
2

2
2

FB_A_CMD10 FB_B_CMD10

4 FB_A_CMD26 FB_B_CMD26 4

FB_A_CMD2 FB_B_CMD2

FB_A_CMD18 FB_B_CMD18
2

2
2

2
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
RG1481

RG1482

RG1486

RG1485

For Reset Security Classification Compal Secret Data Compal Electronics, Inc.
1

1
1

Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(8/9) MEM Interface_AB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 31 of 81
A B C D E
A B C D E

UV1D @ UV1E @
4/22 FBC 5/22 FBD

C6 C11 AK8 AD2


[37] FB_C_D0 FBC_D0 FBC_CMD0 FB_C_CMD1 FB_C_CMD0 [37] [38] FB_D_D0 FBD_D0 FBD_CMD0 FB_D_CMD1 FB_D_CMD0 [38]
D6 B11 AK4 AD1
[37] FB_C_D1 FBC_D1 FBC_CMD1 FB_C_CMD1 [37] [38] FB_D_D1 FBD_D1 FBD_CMD1 FB_D_CMD1 [38]
A6 A11 AK2 AD4
[37] FB_C_D2 FBC_D2 FBC_CMD2 FB_C_CMD2 [37] [38] FB_D_D2 FBD_D2 FBD_CMD2 FB_D_CMD2 [38]
B6 D11 AK3 AC1
1 [37] FB_C_D3 FBC_D3 FBC_CMD3 FB_C_CMD3 [37] [38] FB_D_D3 FBD_D3 FBD_CMD3 FB_D_CMD3 [38] 1
B4 A12 AK5 AC2
[37] FB_C_D4 FBC_D4 FBC_CMD4 FB_C_CMD4 [37] [38] FB_D_D4 FBD_D4 FBD_CMD4 FB_D_CMD4 [38]
A4 B12 AK6 AC3
[37] FB_C_D5 FBC_D5 FBC_CMD5 FB_C_CMD5 [37] [38] FB_D_D5 FBD_D5 FBD_CMD5 FB_D_CMD5 [38]
B3 C12 AK9 AA3
[37] FB_C_D6 FBC_D6 FBC_CMD6 FB_C_CMD6 [37] [38] FB_D_D6 FBD_D6 FBD_CMD6 FB_D_CMD6 [38]
C4 C14 AK7 AA2
[37] FB_C_D7 FBC_D7 FBC_CMD7 FB_C_CMD7 [37] [38] FB_D_D7 FBD_D7 FBD_CMD7 FB_D_CMD7 [38]
D9 B14 AG4 AA1
[37] FB_C_D8 FBC_D8 FBC_CMD8 FB_C_CMD8 [37] [38] FB_D_D8 FBD_D8 FBD_CMD8 FB_D_CMD8 [38]
C9 A14 AF9 AA4
[37] FB_C_D9 FBC_D9 FBC_CMD9 FB_C_CMD9 [37] [38] FB_D_D9 FBD_D9 FBD_CMD9 FB_D_CMD9 [38]
E9 D14 AG6 Y1
[37] FB_C_D10 FBC_D10 FBC_CMD10 FB_C_CMD10 [37] [38] FB_D_D10 FBD_D10 FBD_CMD10 FB_D_CMD10 [38]
B9 A15 AG7 Y2
[37] FB_C_D11 FBC_D11 FBC_CMD11 FB_C_CMD11 [37] [38] FB_D_D11 FBD_D11 FBD_CMD11 FB_D_CMD11 [38]
B8 B15 AJ4 Y3
[37] FB_C_D12 FBC_D12 FBC_CMD12 FB_C_CMD13 FB_C_CMD12 [37] [38] FB_D_D12 FBD_D12 FBD_CMD12 FB_D_CMD13 FB_D_CMD12 [38]
A8 C15 AJ5 V3
[37] FB_C_D13 FBC_D13 FBC_CMD13 FB_C_CMD13 [37] [38] FB_D_D13 FBD_D13 FBD_CMD13 FB_D_CMD13 [38]
F6 C17 AJ6 V2
[37] FB_C_D14 FBC_D14 FBC_CMD14 FB_C_CMD14 [37] [38] FB_D_D14 FBD_D14 FBD_CMD14 FB_D_CMD14 [38]
E6 B17 AG5 V1
[37] FB_C_D15 FBC_D15 FBC_CMD15 FB_C_CMD15 [37] [38] FB_D_D15 FBD_D15 FBD_CMD15 FB_D_CMD15 [38]
F18 B24 Y6 L3
[37] FB_C_D16 FBC_D16 FBC_CMD16 FB_C_CMD17 FB_C_CMD16 [37] [38] FB_D_D16 FBD_D16 FBD_CMD16 FB_D_CMD17 FB_D_CMD16 [38]
G18 A24 Y5 L2
[37] FB_C_D17 FBC_D17 FBC_CMD17 FB_C_CMD17 [37] [38] FB_D_D17 FBD_D17 FBD_CMD17 FB_D_CMD17 [38]
E18 D23 V5 L1
[37] FB_C_D18 FBC_D18 FBC_CMD18 FB_C_CMD18 [37] [38] FB_D_D18 FBD_D18 FBD_CMD18 FB_D_CMD18 [38]
H18 A23 Y4 M4
[37] FB_C_D19 FBC_D19 FBC_CMD19 FB_C_CMD19 [37] [38] FB_D_D19 FBD_D19 FBD_CMD19 FB_D_CMD19 [38]
D15 B23 AA6 M1
[37] FB_C_D20 FBC_D20 FBC_CMD20 FB_C_CMD20 [37] [38] FB_D_D20 FBD_D20 FBD_CMD20 FB_D_CMD20 [38]
E15 C23 AA5 M2
[37] FB_C_D21 FBC_D21 FBC_CMD21 FB_C_CMD21 [37] [38] FB_D_D21 FBD_D21 FBD_CMD21 FB_D_CMD21 [38]
G17 C21 AC5 M3
[37] FB_C_D22 FBC_D22 FBC_CMD22 FB_C_CMD22 [37] [38] FB_D_D22 FBD_D22 FBD_CMD22 FB_D_CMD22 [38]
H17 B21 AC4 P3
[37] FB_C_D23 FBC_D23 FBC_CMD23 FB_C_CMD23 [37] [38] FB_D_D23 FBD_D23 FBD_CMD23 FB_D_CMD23 [38]
J15 A21 AD7 P2
[37] FB_C_D24 FBC_D24 FBC_CMD24 FB_C_CMD24 [37] [38] FB_D_D24 FBD_D24 FBD_CMD24 FB_D_CMD24 [38]
H15 D20 AC6 P1
[37] FB_C_D25 FBC_D25 FBC_CMD25 FB_C_CMD25 [37] [38] FB_D_D25 FBD_D25 FBD_CMD25 FB_D_CMD25 [38]
E14 A20 AF6 R4
[37] FB_C_D26 FBC_D26 FBC_CMD26 FB_C_CMD26 [37] [38] FB_D_D26 FBD_D26 FBD_CMD26 FB_D_CMD26 [38]
F14 B20 AD6 R1
[37] FB_C_D27 FBC_D27 FBC_CMD27 FB_C_CMD27 [37] [38] FB_D_D27 FBD_D27 FBD_CMD27 FB_D_CMD27 [38]
H11 C20 AF7 R2
[37] FB_C_D28 FBC_D28 FBC_CMD28 FB_C_CMD29 FB_C_CMD28 [37] [38] FB_D_D28 FBD_D28 FBD_CMD28 FB_D_CMD29 FB_D_CMD28 [38]
G11 C18 AF8 R3
[37] FB_C_D29 FBC_D29 FBC_CMD29 FB_C_CMD29 [37] [38] FB_D_D29 FBD_D29 FBD_CMD29 FB_D_CMD29 [38]
F11 B18 AF2 U3
[37] FB_C_D30 FBC_D30 FBC_CMD30 FB_C_CMD30 [37] [38] FB_D_D30 FBD_D30 FBD_CMD30 FB_D_CMD30 [38]
E11 A18 AF3 U2
[37] FB_C_D31 FBC_D31 FBC_CMD31 FB_C_CMD31 [37] +1.35VS_VGA [38] FB_D_D31 FBD_D31 FBD_CMD31 FB_D_CMD31 [38] +1.35VS_VGA
J29 A17 F4 V4
[37] FB_C_D32 FBC_D32 FBC_CMD32 FB_C_CMD32 [37] [38] FB_D_D32 FBD_D32 FBD_CMD32 FB_D_CMD32 [38]
F30 D17 @ E1 U1 @
[37] FB_C_D33 FBC_D33 FBC_CMD33 FB_C_DEBUG0 FB_C_CMD33 [37] [38] FB_D_D33 FBD_D33 FBD_CMD33 FB_D_DEBUG0 FB_D_CMD33 [38]
H29 A9 1 RG1410 2 60.4_0402_1% F3 AD3 1 RG1412 2 60.4_0402_1%
[37] FB_C_D34 FBC_D34 FBC_CMD34 FB_C_DEBUG1 [38] FB_D_D34 FBD_D34 FBD_CMD34 FB_D_DEBUG1
G30 C24 1 RG1411 2 60.4_0402_1% F5 J3 1 RG1413 2 60.4_0402_1%
[37] FB_C_D35 FBC_D35 FBC_CMD35 [38] FB_D_D35 FBD_D35 FBD_CMD35
B30 @ D2 @
[37] FB_C_D36 FBC_D36 [38] FB_D_D36 FBD_D36
A30 D1
[37] FB_C_D37 FBC_D37 [38] FB_D_D37 FBD_D37
H30 C3
[37] FB_C_D38 FBC_D38 [38] FB_D_D38 FBD_D38
C30 J14 C2 AC9
[37] FB_C_D39 FBC_D39 FBC_DBG_RFU1 [38] FB_D_D39 FBD_D39 FBD_DBG_RFU1
D27 J23 J5 P9
[37] FB_C_D40 FBC_D40 FBC_DBG_RFU2 [38] FB_D_D40 FBD_D40 FBD_DBG_RFU2
2 J26 J4 2
[37] FB_C_D41 FBC_D41 [38] FB_D_D41 FBD_D41
F27 L8
[37] FB_C_D42 FBC_D42 [38] FB_D_D42 FBD_D42
G27 J2
[37] FB_C_D43 FBC_D43 [38] FB_D_D43 FBD_D43
C27 G15 F1 Y8
[37] FB_C_D44 FBC_D44 FBC_CLK0 FB_C_CLK0 [37] [38] FB_D_D44 FBD_D44 FBD_CLK0 FB_D_CLK0 [38]
B27 F15 F2 Y7
[37] FB_C_D45 FBC_D45 FBC_CLK0_N FB_C_CLK#0 [37] [38] FB_D_D45 FBD_D45 FBD_CLK0_N FB_D_CLK#0 [38]
A27 H21 H4 R8
[37] FB_C_D46 FBC_D46 FBC_CLK1 FB_C_CLK1 [37] [38] FB_D_D46 FBD_D46 FBD_CLK1 FB_D_CLK1 [38]
G29 J21 H5 R7
[37] FB_C_D47 FBC_D47 FBC_CLK1_N FB_C_CLK#1 [37] [38] FB_D_D47 FBD_D47 FBD_CLK1_N FB_D_CLK#1 [38]
H20 V7
[37] FB_C_D48 FBC_D48 [38] FB_D_D48 FBD_D48
D18 V8
[37] FB_C_D49 FBC_D49 [38] FB_D_D49 FBD_D49
G20 V6
[37] FB_C_D50 FBC_D50 [38] FB_D_D50 FBD_D50
E20 V9
[37] FB_C_D51 FBC_D51 [38] FB_D_D51 FBD_D51
F23 U4
[37] FB_C_D52 FBC_D52 [38] FB_D_D52 FBD_D52
E21 R5
[37] FB_C_D53 FBC_D53 [38] FB_D_D53 FBD_D53
D21 R6
[37] FB_C_D54 FBC_D54 [38] FB_D_D54 FBD_D54
E23 U8
[37] FB_C_D55 FBC_D55 [38] FB_D_D55 FBD_D55
G24 F8 P6 AJ8
[37] FB_C_D56 FBC_D56 FBC_WCK01 FB_C_WCK01 [37] [38] FB_D_D56 FBD_D56 FBD_WCK01 FB_D_WCK01 [38]
H26 G8 R9 AJ7
[37] FB_C_D57 FBC_D57 FBC_WCK01_N FB_C_WCK#01 [37] [38] FB_D_D57 FBD_D57 FBD_WCK01_N FB_D_WCK#01 [38]
F24 G9 P4 AG8
[37] FB_C_D58 FBC_D58 FBC_WCKB01 FB_C_WCKB01 [37] [38] FB_D_D58 FBD_D58 FBD_WCKB01 FB_D_WCKB01 [38]
G26 F9 P5 AG9
[37] FB_C_D59 FBC_D59 FBC_WCKB01_N FB_C_WCKB#01 [37] [38] FB_D_D59 FBD_D59 FBD_WCKB01_N FB_D_WCKB#01 [38]
F26 H12 L7 AD8
[37] FB_C_D60 FBC_D60 FBC_WCK23 FB_C_WCK23 [37] [38] FB_D_D60 FBD_D60 FBD_WCK23 FB_D_WCK23 [38]
D26 G12 L6 AD9
[37] FB_C_D61 FBC_D61 FBC_WCK23_N FB_C_WCK#23 [37] [38] FB_D_D61 FBD_D61 FBD_WCK23_N FB_D_WCK#23 [38]
B26 G14 L4 AC7
[37] FB_C_D62 FBC_D62 FBC_WCKB23 FB_C_WCKB23 [37] [38] FB_D_D62 FBD_D62 FBD_WCKB23 FB_D_WCKB23 [38]
C26 H14 L5 AC8
[37] FB_C_D63 FBC_D63 FBC_WCKB23_N FB_C_WCKB#23 [37] [38] FB_D_D63 FBD_D63 FBD_WCKB23_N FB_D_WCKB#23 [38]
J27 J6
FBC_WCK45 FB_C_WCK45 [37] FBD_WCK45 FB_D_WCK45 [38]
H27 J7
FBC_WCK45_N FB_C_WCK#45 [37] FBD_WCK45_N FB_D_WCK#45 [38]
A5 E29 AJ1 H7
[37] FB_C_DBI0 FBC_DQM0 FBC_WCKB45 FB_C_WCKB45 [37] [38] FB_D_DBI0 FBD_DQM0 FBD_WCKB45 FB_D_WCKB45 [38]
C8 F29 AG1 H6
[37] FB_C_DBI1 FBC_DQM1 FBC_WCKB45_N FB_C_WCKB#45 [37] [38] FB_D_DBI1 FBD_DQM1 FBD_WCKB45_N FB_D_WCKB#45 [38]
J18 G23 AA7 P8
[37] FB_C_DBI2 FBC_DQM2 FBC_WCK67 FB_C_WCK67 [37] [38] FB_D_DBI2 FBD_DQM2 FBD_WCK67 FB_D_WCK67 [38]
F12 H23 AD5 P7
[37] FB_C_DBI3 FBC_DQM3 FBC_WCK67_N FB_C_WCK#67 [37] [38] FB_D_DBI3 FBD_DQM3 FBD_WCK67_N FB_D_WCK#67 [38]
D29 H24 D3 M7
[37] FB_C_DBI4 FBC_DQM4 FBC_WCKB67 FB_C_WCKB67 [37] [38] FB_D_DBI4 FBD_DQM4 FBD_WCKB67 FB_D_WCKB67 [38]
E27 J24 H3 M8
[37] FB_C_DBI5 FBC_DQM5 FBC_WCKB67_N FB_C_WCKB#67 [37] [38] FB_D_DBI5 FBD_DQM5 FBD_WCKB67_N FB_D_WCKB#67 [38]
F20 U5
[37] FB_C_DBI6 FBC_DQM6 [38] FB_D_DBI6 FBD_DQM6
E26 M9
[37] FB_C_DBI7 FBC_DQM7 [38] FB_D_DBI7 FBD_DQM7

D5 AJ3
[37] FB_C_EDC0 FBC_DQS_WP0 [38] FB_D_EDC0 FBD_DQS_WP0
D8 AG2
[37] FB_C_EDC1 FBC_DQS_WP1 +FBX_PLLAVDD [38] FB_D_EDC1 FBD_DQS_WP1 +FBX_PLLAVDD
E17 AA9
3 [37] FB_C_EDC2 FBC_DQS_WP2 [38] FB_D_EDC2 FBD_DQS_WP2 3
E12 AF4
[37] FB_C_EDC3 FBC_DQS_WP3 [38] FB_D_EDC3 FBD_DQS_WP3
E30 E3
[37] FB_C_EDC4 FBC_DQS_WP4 [38] FB_D_EDC4 FBD_DQS_WP4
B29 H2
[37] FB_C_EDC5 FBC_DQS_WP5 [38] FB_D_EDC5 FBD_DQS_WP5
G21 U6
[37] FB_C_EDC6 FBC_DQS_WP6 [38] FB_D_EDC6 FBD_DQS_WP6
E24 L17 M5 V11
[37] FB_C_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD [38] FB_D_EDC7 FBD_DQS_WP7 FBD_PLL_AVDD

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

Y24 1 Y32 1
GND_710 GND_0718

CG570
CG65

Y25 Y33
Y26 GND_711 Y34 GND_0719
Y27 GND_712 Y35 GND_0720
Y28 GND_713 2 Y36 GND_0721 2
Y29 GND_714 Y37 GND_0722
Y30 GND_715 Y38 GND_0723
Y31 GND_716 Y39 GND_0724
GND_717 GND_0725

Under GPU N18E-G3


Under GPU
FBD N/A
N18E-G3-ES-A1_FCBGA2228 +1.35VS_VGA +1.35VS_VGA N18E-G3-ES-A1_FCBGA2228
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
1

1
G3G2@

G3G2@
RG1487

RG1488

RG1491

RG1492

For CKE_A
2

FB_C_CMD10 FB_D_CMD10

4 FB_C_CMD26 FB_D_CMD26 4

FB_C_CMD2 FB_D_CMD2

FB_C_CMD18 FB_D_CMD18
2
2
2

G3G2@
10K_0402_1%
10K_0402_1%
10K_0402_1%

10K_0402_1%

RG1493
RG1494
RG1490

RG1489

G3G2@

For Reset Security Classification Compal Secret Data Compal Electronics, Inc.
1
1
1

Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(9/9) MEM Interface_CD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 32 of 81
A B C D E
5 4 3 2 1

GPU Decoupling - NV Spec Recommendation

FBVDDQ_GPU
+1.35VS_VGA

Place under GPU


1 1 1 1 1 1
D
CG6838 CG6829 CG6828 CG6831 CG6833 CG6834
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
0.47UF_0201 X 48 pcs D

2 2 2 2 2 2

10UF_0603 X 8 pcs
1 1 1 1 1 1
CG6839 CG6830 CG6832 CG6835 CG6836 CG6837
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2

1 1 1 1 1 1
CG6849 CG6841 CG6840 CG6843 CG6845 CG6846
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2

1 1 1 1 1 1
CG6851 CG6842 CG6844 CG6847 CG6848 CG6850
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2

1 1 1 1 1 1
CG6861 CG6854 CG6852 CG6856 CG6858 CG6857
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2
C C

1 1 1 1 1 1
CG6863 CG6853 CG6855 CG6859 CG6860 CG6862
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2

1 1 1 1 1 1
CG6873 CG6866 CG6864 CG6868 CG6870 CG6869
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2

1 1 1 1 1 1
CG6875 CG6865 CG6867 CG6871 CG6872 CG6874
0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K0.47U_0201_6.3V6K
2 2 2 2 2 2
1

1
1

1
1

CG6879 CG6876 CG6877 CG6878 CG6880 CG6884 CG6886 CG6887


10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
2

2
2

2
2

B B
1

1
1

CG6885 CG6881 CG6882 CG6883


10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
Place near GPU
2

2
2

22UF_0603 X 9 pcs
22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
1
1

CG6894
CG6888

CG6890

CG6895

CG6896
CG6889

CG6891

CG6892

CG6893

10UF_0603 X 4 pcs
2

2
2
2

2
2

2
330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330UF_B2 X 2 pcs 330UF_D3 X 1 pcs


330U_D3_2.5VY_R6M

1 1 1
CG7101

+ + +
CG6897

CG6898

@
2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPU Decoupling_1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 33 of 81
5 4 3 2 1
5 4 3 2 1

+3VS

1
D +1V8_AON
2 QG57
[19,34,48] DGPU_PWR_EN
G L2N7002LT1G_SOT23-3 UG52

5
S NL17SZ08DFT2G_SC70-5

3
@

VCC
DGPU_PWR_EN_RC 1 @ 2 DGPU_PWR_EN_R 1
IN B 4 1V8_MAIN_EN_AND
RG1566 5K_0402_1% 2 OUT Y

GND
[25] 1V8_MAIN_EN IN A

2
@2

0.1U_0402_25V6
@ RG1567
10K_0402_5%

3
CG486
D 1 D

1
RG1565 1 2 0_0201_5%

+1V8_AON / +1V8_MAIN
+5VALW +1.8VALW
From PCH DG12
2 +1V8_AON
,34,48] DGPU_PWR_EN
1 UG45
1 @ 2 0_0402_5% 3 1 14
[77] 1.5VS_DGPU_PG VIN1 VOUT1
2 2 13
VIN1 VOUT1

10U_0603_6.3V6M
0.1U_0402_25V6

RG1564 BAV70W_SOT323-3 CG7099


@ 1V8_AON_EN 3 12 1 2 220P_0402_50V8J 1
ON1 CT1

CG7100
CG485

1 +1V8_AON 4 11
VBIAS GND CG7097
PS_1V8_MAIN_EN 5 10 1 2 220P_0402_50V8J +1V8_MAIN 2
ON2 CT2
5

0.1U_0402_10V7K
6 9
VIN2 VOUT2

1
[25] GPU_FGC6_EN
1 VCC 1 1 7 8
B VIN2 VOUT2

CG7096

10U_0603_6.3V6M
Y 4 RG1516 RG1520
1V8_MAIN_EN_AND 2 A 100K_0402_5% 100K_0402_5% 15 1
GPAD

CG7098
G
UG49 @ 2 EM5209VF_DFN14_3X2

2
3

74LVC1G32GW_TSSOP5
2

Change UG45 from SA00006U300 to SA00007PM00


RG1521 1 @ 2 0_0201_5%
C C

+1V8_AON

5
VCC
DGPU_PWR_EN 1 RG641
IN B 4 DG13 2 1 1 2
1V8_MAIN_EN OUT Y NVVDD_EN [73]
2 GND
IN A RB751S-40 SOD-523
1K +-1% 0402 Enable: Vh:1.2V Vl:0.6V
UG51 1 2 RG1522 1 @ 2 0_0201_5%
3

+3VS NL17SZ08DFT2G_SC70-5 RG1523 2


41.2K_0402_1% CV197
UG29 +1V8_AON
MC74VHC1G09DFT2G_SC70-5 0.1U_0402_25V6
5

1
NVVDD_PGOOD 1
G VCC

[73] NVVDD_PGOOD B

5
4
1.5VS_DGPU_PG Y DGPU_PWROK [16] PEX_VDD_EN_D
2 DG15 1 2 Delay 1.33ms 1 VCC
A [25] GPU_OVERT# B
Y 4
GPU_FGC6_EN 1.0VS_DGPU_EN [79]
RB751S-40 SOD-523 2 A
3

G
1 2 UG39 @

3
74LVC1G32GW_TSSOP5
RG1532 1 2 0_0201_5% RG1524 10K_0402_5% 2
@ CV196

0.1U_0402_25V6
GC6 2.1 function 1

+3VS

FOR GC6 2.1


1

B
RG1527 RG1544 1 2 0_0201_5% GPU_GC6_FB_EN_H [19]
1V8_AON 1V8_MAIN NVVDD PEXVDD FBVDD B
1

10K_0402_5%
RG1531
10K_0402_5% DG18
RG1568
GC6 2.1 ON OFF OFF OFF ON
3 2

GC6_FB_EN3V3 2
1 1 2 FBVDD_EN_R [77]
FGC6
6 2

NVVDD_PGOOD
D
5 3
G

S 5K_0402_1%
ON ON OFF ON ON
1

CG487

GPU_GC6_FB_EN 2
D
0.1U_0402_25V6

G QG522A PJT138KA 2N SOT363-6 BAV70W_SOT323-3


[25] GPU_GC6_FB_EN
4

QG522B S RG1528
PJT138KA 2N SOT363-6 68K_0402_5%
1

2
2

+1V8_AON
+1V8_MAIN +1.35VS_VGA
1

+5VS
16_0805_1%

16_0805_1%

16_0805_1%

RG510
+5VS +5VS
RG1561

RG1562

RG1563

51_0402_5% RG512
51_0402_5% @
2
1

2
1

1
PJT138KA_SOT363-6

RG509
PJT138KA_SOT363-6

PJT138KA_SOT363-6

10K_0402_5% RG511 RG1560


10K_0402_5% 10K_0402_5%
3
2

3
QG503B

2
QG520B

QG526B

5
PJT138KA_SOT363-6

A 5 5 A
PJT138KA_SOT363-6

PJT138KA_SOT363-6
4

4
6

6
QG503A

QG526A
QG520A

1V8_AON_EN 2
PS_1V8_MAIN_EN2 FBVDD_EN_R 2
1

1V8_MAIN_EN_R [44] Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sequence control
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
SB00001FN00 change to SB000016K00 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 34 of 81
5 4 3 2 1
A B C D E

VRAM A
www.teknisi-indonesia.com

1 1

UG11 @ UG12 @
GDDR6 CMD Mapping x16 Mode
Lower 0..31 Upper 32..63
DRAM1 DRAM2 C2 B4 C2 B4
[31] FB_A_EDC0 EDC0_A DQ0_A FB_A_D4 [31] [31] FB_A_EDC4 EDC0_A DQ0_A FB_A_D39 [31]
CHA-Byte 0,1 CHA-Byte 4,5 C13 A3 C13 A3
[31] FB_A_EDC1 EDC1_A DQ1_A FB_A_D7 [31] [31] FB_A_EDC5 EDC1_A DQ1_A FB_A_D35 [31]
T2 B3 T2 B3
[31] FB_A_EDC3 EDC0_B DQ2_A FB_A_D1 [31] [31] FB_A_EDC7 EDC0_B DQ2_A FB_A_D32 [31]
CA0_A CMD0 CMD20 T13 B2 T13 B2
[31] FB_A_EDC2 EDC1_B DQ3_A FB_A_D5 [31] [31] FB_A_EDC6 EDC1_B DQ3_A FB_A_D38 [31]
CA1_A CMD9 CMD28 E3 E3
DQ4_A FB_A_D3 [31] DQ4_A FB_A_D34 [31]
CA2_A CMD8 CMD21 E2 E2
DQ5_A FB_A_D6 [31] DQ5_A FB_A_D33 [31]
CA3_A CMD32 CMD29 D2 F2 D2 F2
[31] FB_A_DBI0 DBI0#_A DQ6_A FB_A_D2 [31] [31] FB_A_DBI4 DBI0#_A DQ6_A FB_A_D37 [31]
CA4_A CMD7 CMD23 D13 G2 D13 G2
[31] FB_A_DBI1 DBI1#_A DQ7_A FB_A_D0 [31] [31] FB_A_DBI5 DBI1#_A DQ7_A FB_A_D36 [31]
CA5_A CMD11 CMD27 R2 B11 R2 B11
[31] FB_A_DBI3 DBI0#_B DQ8_A FB_A_D8 [31] [31] FB_A_DBI7 DBI0#_B DQ8_A FB_A_D43 [31]
CA6_A CMD15 CMD30 R13 A12 R13 A12
[31] FB_A_DBI2 DBI1#_B DQ9_A FB_A_D15 [31] [31] FB_A_DBI6 DBI1#_B DQ9_A FB_A_D46 [31]
CA7_A CMD14 CMD31 B12 B12
DQ10_A FB_A_D13 [31] DQ10_A FB_A_D44 [31]
CA8_A CMD3 CMD19 B13 B13
DQ11_A FB_A_D14 [31] DQ11_A FB_A_D42 [31]
CA9_A CMD1 CMD17 J10 E12 J10 E12
[31] FB_A_CLK0 CK_T DQ12_A FB_A_D12 [31] [31] FB_A_CLK1 CK_T DQ12_A FB_A_D45 [31]
CABI_A CMD6 CMD22 K10 E13 K10 E13
[31] FB_A_CLK#0 CK_C DQ13_A FB_A_D10 [31] [31] FB_A_CLK#1 CK_C DQ13_A FB_A_D40 [31]
CKE_A CMD10 CMD26 G10 F13 G10 F13
[31] FB_A_CMD10 CKE#_A DQ14_A FB_A_D11 [31] [31] FB_A_CMD26 CKE#_A DQ14_A FB_A_D41 [31]
M10 G13 M10 G13
CKE#_B DQ15_A FB_A_D9 [31] CKE#_B DQ15_A FB_A_D47 [31]
CHB-Byte 2,3 CHB-Byte 6,7
CA0_B CMD4 CMD16 U4 U4
DQ0_B FB_A_D30 [31] DQ0_B FB_A_D57 [31]
CA1_B CMD12 CMD25 V3 V3
DQ1_B FB_A_D29 [31] DQ1_B FB_A_D56 [31]
CA2_B CMD5 CMD24 U3 U3
DQ2_B FB_A_D28 [31] DQ2_B FB_A_D59 [31]
CA3_B CMD13 CMD33 J5 U2 J5 U2
[31] FB_A_CMD6 CABI#_A DQ3_B FB_A_D31 [31] [31] FB_A_CMD22 CABI#_A DQ3_B FB_A_D58 [31]
CA4_B CMD7 CMD23 K5 P3 K5 P3
CABI#_B DQ4_B FB_A_D25 [31] CABI#_B DQ4_B FB_A_D61 [31]
CA5_B CMD11 CMD27 P2 P2
DQ5_B FB_A_D27 [31] DQ5_B FB_A_D60 [31]
CA6_B CMD15 CMD30 N2 N2
DQ6_B FB_A_D24 [31] DQ6_B FB_A_D63 [31]
CA7_B CMD14 CMD31 M2 M2
DQ7_B FB_A_D26 [31] DQ7_B FB_A_D62 [31]
CA8_B CMD3 CMD19 U11 U11
DQ8_B FB_A_D23 [31] DQ8_B FB_A_D49 [31]
CA9_B CMD1 CMD17 V12 V12
DQ9_B FB_A_D22 [31] DQ9_B FB_A_D50 [31]
CABI_B CMD6 CMD22 RG101 2 1 121_0402_1% J14 U12 RG573 2 1 121_0402_1% J14 U12
ZQ_A DQ10_B FB_A_D20 [31] ZQ_A DQ10_B FB_A_D53 [31]
CKE_B CMD10 CMD26 RG102 2 1 121_0402_1% K14 U13 RG574 2 1 121_0402_1% K14 U13
ZQ_B DQ11_B FB_A_D17 [31] ZQ_B DQ11_B FB_A_D48 [31]
P12 P12
DQ12_B FB_A_D21 [31] DQ12_B FB_A_D52 [31]
RESET* CMD2 CMD18 P13 P13
DQ13_B FB_A_D16 [31] DQ13_B FB_A_D51 [31]
N13 N13
DQ14_B FB_A_D19 [31] DQ14_B FB_A_D54 [31]
M13 M13
DQ15_B FB_A_D18 [31] DQ15_B FB_A_D55 [31]

N5 H3 N5 H3
TCK CA0_A FB_A_CMD0 [31] TCK CA0_A FB_A_CMD20 [31]
F10 G11 F10 G11
TDI CA1_A FB_A_CMD9 [31] TDI CA1_A FB_A_CMD28 [31]
N10 G4 N10 G4
TDO CA2_A FB_A_CMD8 [31] TDO CA2_A FB_A_CMD21 [31]
F5 H12 F5 H12
TMS CA3_A FB_A_CMD32 [31] TMS CA3_A FB_A_CMD29 [31]
H5 H5
2 CA4_A FB_A_CMD7 [31] CA4_A FB_A_CMD23 [31] 2
H10 H10
CA5_A FB_A_CMD11 [31] CA5_A FB_A_CMD27 [31]
J12 J12
CA6_A FB_A_CMD15 [31] CA6_A FB_A_CMD30 [31]
D4 J11 D4 J11
[31] FB_A_WCK01 WCK0_T_A CA7_A FB_A_CMD14 [31] [31] FB_A_WCK45 WCK0_T_A CA7_A FB_A_CMD31 [31]
D5 J4 D5 J4
[31] FB_A_WCK#01 WCK0_C_A CA8_A FB_A_CMD3 [31] [31] FB_A_WCK#45 WCK0_C_A CA8_A FB_A_CMD19 [31]
D11 J3 D11 J3
[31] FB_A_WCKB01 WCK1_T_A CA9_A FB_A_CMD1 [31] [31] FB_A_WCKB45 WCK1_T_A CA9_A FB_A_CMD17 [31]
D10 D10
[31] FB_A_WCKB#01 WCK1_C_A [31] FB_A_WCKB#45 WCK1_C_A
L3 L3
CA0_B FB_A_CMD4 [31] CA0_B FB_A_CMD16 [31]
M11 M11
CA1_B FB_A_CMD12 [31] CA1_B FB_A_CMD25 [31]
R4 M4 R4 M4
[31] FB_A_WCKB23 WCK0_T_B CA2_B FB_A_CMD5 [31] [31] FB_A_WCKB67 WCK0_T_B CA2_B FB_A_CMD24 [31]
R5 L12 R5 L12
[31] FB_A_WCKB#23 WCK0_C_B CA3_B FB_A_CMD7 FB_A_CMD13 [31] [31] FB_A_WCKB#67 WCK0_C_B CA3_B FB_A_CMD23 FB_A_CMD33 [31]
R11 L5 R11 L5
[31] FB_A_WCK23 WCK1_T_B CA4_B FB_A_CMD11 [31] FB_A_WCK67 WCK1_T_B CA4_B FB_A_CMD27
R10 L10 R10 L10
[31] FB_A_WCK#23 WCK1_C_B CA5_B FB_A_CMD15 [31] FB_A_WCK#67 WCK1_C_B CA5_B FB_A_CMD30
K12 K12
+1.35VS_VGA CA6_B K11 FB_A_CMD14 CA6_B K11 FB_A_CMD31
CA7_B K4 FB_A_CMD3 CA7_B K4 FB_A_CMD19
CA8_B K3 FB_A_CMD1 CA8_B K3 FB_A_CMD17
CA9_B CA9_B
1

@ +FBA_VREFC K1 +1.35VS_VGA +FBA_VREFC K1 +1.35VS_VGA


RG110 VREFC VREFC
549_0402_1% C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
[31] FB_A_CMD2 RESET# VDDQ2 [31] FB_A_CMD18 RESET# VDDQ2
H1 H1
W=16mils
2

VDDQ3 L1 VDDQ3 L1
1 2 +FBA_VREFC B1 VDDQ4 P1 B1 VDDQ4 P1
D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
VSS2 VDDQ6 VSS2 VDDQ6
1

820P_0402_25V7

820P_0402_25V7
1K_0402_1%

CG78

CG79
RG112

RG111 @ 1 1 F1 J2 F1 J2
931_0402_1% G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
VSS5 VDDQ9 VSS5 VDDQ9
1

D
@ @ @ N1 F4 N1 F4
2 QG2 2 2 R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
[25,36,37,38] MEM_VREF
2

G MESS138W-G_SOT323-3 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4


S A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
3

V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5


C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
Close to GDDR6 UG11 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14 Close to GDDR6 UG12 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

P4 P14 P4 P14
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
2 2 2 2 VSS24 VDDQ28 2 2 2 2 VSS24 VDDQ28
+1.35VS_VGA +1.35VS_VGA
CG104

CG105

CG106

CG546

CG547
CG550

CG551
CG103

C5 C5
T5 VSS25 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
1 1 1 1 T10 VSS27 VDD1 V1 1 1 1 1 T10 VSS27 VDD1 V1
3 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2 3
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13 22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13
Around GDDR6 UG11 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
Around GDDR6 UG12 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
VSS39 VSS39

CG517
10U_0603_6.3V6M
CG107

CG110

CG112

CG521

CG519

CG520
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CG108

CG109

CG111

CG518

CG516
N12 N12
R12 VSS40 A5 R12 VSS40 A5
2 2 1 1 1 1 1 1 VSS41 VPP1 2 2 1 1 1 1 1 1 VSS41 VPP1

CG548
CG101

CG102

CG549
T12 V5 T12 V5
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
1 1 2 2 2 2 2 2 VSS44 VPP4 1 1 2 2 2 2 2 2 VSS44 VPP4

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
B14 B14
D14 VSS45 D14 VSS45
F14 VSS46 G5 F14 VSS46 G5
G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
M14 VSS48 NC2 M14 VSS48 NC2
N14 VSS49 N14 VSS49
R14 VSS50 R14 VSS50
U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6

4.7UF_0402 X 1 pcs MT61K256M32JE-13-A_FBGA180~D


4.7UF_0402 X 1 pcs
0.47UF_0201 X 36 pcs 0.47UF_0201 X 36 pcs MT61K256M32JE-13-A_FBGA180~D
+1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON +1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON

Close to GDDR6 UG11 Close to +1V8_AON Close to GDDR6 UG12 Close to +1V8_AON
CG512

0.47U_0201_6.3V6K CG6558

0.47U_0201_6.3V6K CG6561

0.47U_0201_6.3V6K CG6562

CG552

CG553
0.47U_0201_6.3V6K CG6522

0.47U_0201_6.3V6K CG6531

0.47U_0201_6.3V6K CG6532

CG513

CG514

0.47U_0201_6.3V6K CG6581

0.47U_0201_6.3V6K CG6560

0.47U_0201_6.3V6K CG6564

0.47U_0201_6.3V6K CG6565

0.47U_0201_6.3V6K CG6576

0.47U_0201_6.3V6K CG6580

0.47U_0201_6.3V6K CG6559

CG554
0.47U_0201_6.3V6K CG6525

0.47U_0201_6.3V6K CG6527

0.47U_0201_6.3V6K CG6528

0.47U_0201_6.3V6K CG6529

0.47U_0201_6.3V6K CG6530

0.47U_0201_6.3V6K CG6533

CG511

CG515

0.47U_0201_6.3V6K CG6563

0.47U_0201_6.3V6K CG6579

CG555

CG556
0.47U_0201_6.3V6K CG6523

0.47U_0201_6.3V6K CG6524

0.47U_0201_6.3V6K CG6526

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

4.7U_0402_6.3V6M
Chage:0.47uF
4.7U_0402_6.3V6M

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1. X5R --> X7R or X6S?

+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA


4 4
0.47U_0201_6.3V6K CG6542

0.47U_0201_6.3V6K CG6543

0.47U_0201_6.3V6K CG6578

0.47U_0201_6.3V6K CG6568

0.47U_0201_6.3V6K CG6593

0.47U_0201_6.3V6K CG6586

0.47U_0201_6.3V6K CG6583

0.47U_0201_6.3V6K CG6590

0.47U_0201_6.3V6K CG6582
0.47U_0201_6.3V6K CG6545

0.47U_0201_6.3V6K CG6537

0.47U_0201_6.3V6K CG6538

0.47U_0201_6.3V6K CG6539

0.47U_0201_6.3V6K CG6540

0.47U_0201_6.3V6K CG6544

0.47U_0201_6.3V6K CG6551

0.47U_0201_6.3V6K CG6550

0.47U_0201_6.3V6K CG6555

0.47U_0201_6.3V6K CG6546

0.47U_0201_6.3V6K CG6575

0.47U_0201_6.3V6K CG6577

0.47U_0201_6.3V6K CG6591
0.47U_0201_6.3V6K CG6534

0.47U_0201_6.3V6K CG6536

0.47U_0201_6.3V6K CG6557

0.47U_0201_6.3V6K CG6547

0.47U_0201_6.3V6K CG6549

0.47U_0201_6.3V6K CG6548

0.47U_0201_6.3V6K CG6553

0.47U_0201_6.3V6K CG6552

0.47U_0201_6.3V6K CG6556

0.47U_0201_6.3V6K CG6567

0.47U_0201_6.3V6K CG6571

0.47U_0201_6.3V6K CG6570

0.47U_0201_6.3V6K CG6573

0.47U_0201_6.3V6K CG6572

0.47U_0201_6.3V6K CG6574

0.47U_0201_6.3V6K CG6566

0.47U_0201_6.3V6K CG6584

0.47U_0201_6.3V6K CG6588

0.47U_0201_6.3V6K CG6587

0.47U_0201_6.3V6K CG6589

0.47U_0201_6.3V6K CG6592
0.47U_0201_6.3V6K CG6569
0.47U_0201_6.3V6K CG6541

0.47U_0201_6.3V6K CG6535

0.47U_0201_6.3V6K CG6554

0.47U_0201_6.3V6K CG6585
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR6_A_CH2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 35 of 81
A B C D E
A B C D E

VRAM B

1 1

UG13 @ UG14 @
GDDR6 CMD Mapping x16 Mode
Lower 0..31 Upper 32..63
DRAM1 DRAM2 C2 B4 C2 B4
[31] FB_B_EDC0 EDC0_A DQ0_A FB_B_D1 [31] [31] FB_B_EDC4 EDC0_A DQ0_A FB_B_D35 [31]
CHA-Byte 0,1 CHA-Byte 4,5 C13 A3 C13 A3
[31] FB_B_EDC1 EDC1_A DQ1_A FB_B_D6 [31] [31] FB_B_EDC5 EDC1_A DQ1_A FB_B_D33 [31]
T2 B3 T2 B3
[31] FB_B_EDC3 EDC0_B DQ2_A FB_B_D2 [31] [31] FB_B_EDC7 EDC0_B DQ2_A FB_B_D32 [31]
CA0_A CMD0 CMD20 T13 B2 T13 B2
[31] FB_B_EDC2 EDC1_B DQ3_A FB_B_D4 [31] [31] FB_B_EDC6 EDC1_B DQ3_A FB_B_D36 [31]
CA1_A CMD9 CMD28 E3 E3
DQ4_A FB_B_D5 [31] DQ4_A FB_B_D39 [31]
CA2_A CMD8 CMD21 E2 E2
DQ5_A FB_B_D3 [31] DQ5_A FB_B_D34 [31]
CA3_A CMD32 CMD29 D2 F2 D2 F2
[31] FB_B_DBI0 DBI0#_A DQ6_A FB_B_D0 [31] [31] FB_B_DBI4 DBI0#_A DQ6_A FB_B_D37 [31]
CA4_A CMD7 CMD23 D13 G2 D13 G2
[31] FB_B_DBI1 DBI1#_A DQ7_A FB_B_D7 [31] [31] FB_B_DBI5 DBI1#_A DQ7_A FB_B_D38 [31]
CA5_A CMD11 CMD27 R2 B11 R2 B11
[31] FB_B_DBI3 DBI0#_B DQ8_A FB_B_D13 [31] [31] FB_B_DBI7 DBI0#_B DQ8_A FB_B_D42 [31]
CA6_A CMD15 CMD30 R13 A12 R13 A12
[31] FB_B_DBI2 DBI1#_B DQ9_A FB_B_D14 [31] [31] FB_B_DBI6 DBI1#_B DQ9_A FB_B_D43 [31]
CA7_A CMD14 CMD31 B12 B12
DQ10_A FB_B_D12 [31] DQ10_A FB_B_D40 [31]
CA8_A CMD3 CMD19 B13 B13
DQ11_A FB_B_D11 [31] DQ11_A FB_B_D45 [31]
CA9_A CMD1 CMD17 J10 E12 J10 E12
[31] FB_B_CLK0 CK_T DQ12_A FB_B_D15 [31] [31] FB_B_CLK1 CK_T DQ12_A FB_B_D41 [31]
CABI_A CMD6 CMD22 K10 E13 K10 E13
[31] FB_B_CLK#0 CK_C DQ13_A FB_B_D8 [31] [31] FB_B_CLK#1 CK_C DQ13_A FB_B_D44 [31]
CKE_A CMD10 CMD26 G10 F13 G10 F13
[31] FB_B_CMD10 CKE#_A DQ14_A FB_B_D9 [31] [31] FB_B_CMD26 CKE#_A DQ14_A FB_B_D46 [31]
M10 G13 M10 G13
CKE#_B DQ15_A FB_B_D10 [31] CKE#_B DQ15_A FB_B_D47 [31]
CHB-Byte 2,3 CHB-Byte 6,7
CA0_B CMD4 CMD16 U4 U4
DQ0_B FB_B_D24 [31] DQ0_B FB_B_D62 [31]
CA1_B CMD12 CMD25 V3 V3
DQ1_B FB_B_D30 [31] DQ1_B FB_B_D59 [31]
CA2_B CMD5 CMD24 U3 U3
DQ2_B FB_B_D29 [31] DQ2_B FB_B_D57 [31]
CA3_B CMD13 CMD33 J5 U2 J5 U2
[31] FB_B_CMD6 CABI#_A DQ3_B FB_B_D31 [31] [31] FB_B_CMD22 CABI#_A DQ3_B FB_B_D63 [31]
CA4_B CMD7 CMD23 K5 P3 K5 P3
CABI#_B DQ4_B FB_B_D25 [31] CABI#_B DQ4_B FB_B_D56 [31]
CA5_B CMD11 CMD27 P2 P2
DQ5_B FB_B_D26 [31] DQ5_B FB_B_D61 [31]
CA6_B CMD15 CMD30 N2 N2
DQ6_B FB_B_D27 [31] DQ6_B FB_B_D60 [31]
CA7_B CMD14 CMD31 M2 M2
DQ7_B FB_B_D28 [31] DQ7_B FB_B_D58 [31]
CA8_B CMD3 CMD19 U11 U11
DQ8_B FB_B_D21 [31] DQ8_B FB_B_D55 [31]
CA9_B CMD1 CMD17 V12 V12
DQ9_B FB_B_D16 [31] DQ9_B FB_B_D48 [31]
CABI_B CMD6 CMD22 RG103 2 1 121_0402_1% J14 U12 RG575 2 1 121_0402_1% J14 U12
ZQ_A DQ10_B FB_B_D20 [31] ZQ_A DQ10_B FB_B_D52 [31]
CKE_B CMD10 CMD26 RG104 2 1 121_0402_1% K14 U13 RG576 2 1 121_0402_1% K14 U13
ZQ_B DQ11_B FB_B_D17 [31] ZQ_B DQ11_B FB_B_D50 [31]
P12 P12
DQ12_B FB_B_D18 [31] DQ12_B FB_B_D49 [31]
RESET* CMD2 CMD18 P13 P13
DQ13_B FB_B_D22 [31] DQ13_B FB_B_D51 [31]
N13 N13
DQ14_B FB_B_D23 [31] DQ14_B FB_B_D53 [31]
M13 M13
DQ15_B FB_B_D19 [31] DQ15_B FB_B_D54 [31]

N5 H3 N5 H3
TCK CA0_A FB_B_CMD0 [31] TCK CA0_A FB_B_CMD20 [31]
F10 G11 F10 G11
TDI CA1_A FB_B_CMD9 [31] TDI CA1_A FB_B_CMD28 [31]
N10 G4 N10 G4
TDO CA2_A FB_B_CMD8 [31] TDO CA2_A FB_B_CMD21 [31]
F5 H12 F5 H12
TMS CA3_A FB_B_CMD32 [31] TMS CA3_A FB_B_CMD29 [31]
H5 H5
2 CA4_A FB_B_CMD7 [31] CA4_A FB_B_CMD23 [31] 2
H10 H10
CA5_A FB_B_CMD11 [31] CA5_A FB_B_CMD27 [31]
J12 J12
CA6_A FB_B_CMD15 [31] CA6_A FB_B_CMD30 [31]
D4 J11 D4 J11
[31] FB_B_WCK01 WCK0_T_A CA7_A FB_B_CMD14 [31] [31] FB_B_WCK45 WCK0_T_A CA7_A FB_B_CMD31 [31]
D5 J4 D5 J4
[31] FB_B_WCK#01 WCK0_C_A CA8_A FB_B_CMD3 [31] [31] FB_B_WCK#45 WCK0_C_A CA8_A FB_B_CMD19 [31]
D11 J3 D11 J3
[31] FB_B_WCKB01 WCK1_T_A CA9_A FB_B_CMD1 [31] [31] FB_B_WCKB45 WCK1_T_A CA9_A FB_B_CMD17 [31]
D10 D10
[31] FB_B_WCKB#01 WCK1_C_A [31] FB_B_WCKB#45 WCK1_C_A
L3 L3
CA0_B FB_B_CMD4 [31] CA0_B FB_B_CMD16 [31]
M11 M11
CA1_B FB_B_CMD12 [31] CA1_B FB_B_CMD25 [31]
R4 M4 R4 M4
[31] FB_B_WCKB23 WCK0_T_B CA2_B FB_B_CMD5 [31] [31] FB_B_WCKB67 WCK0_T_B CA2_B FB_B_CMD24 [31]
R5 L12 R5 L12
[31] FB_B_WCKB#23 WCK0_C_B CA3_B FB_B_CMD7 FB_B_CMD13 [31] [31] FB_B_WCKB#67 WCK0_C_B CA3_B FB_B_CMD23 FB_B_CMD33 [31]
R11 L5 R11 L5
[31] FB_B_WCK23 WCK1_T_B CA4_B FB_B_CMD11 [31] FB_B_WCK67 WCK1_T_B CA4_B FB_B_CMD27
R10 L10 R10 L10
[31] FB_B_WCK#23 WCK1_C_B CA5_B FB_B_CMD15 [31] FB_B_WCK#67 WCK1_C_B CA5_B FB_B_CMD30
K12 K12
+1.35VS_VGA CA6_B K11 FB_B_CMD14 CA6_B K11 FB_B_CMD31
CA7_B K4 FB_B_CMD3 CA7_B K4 FB_B_CMD19
CA8_B K3 FB_B_CMD1 CA8_B K3 FB_B_CMD17
CA9_B CA9_B
1

@ +FBB_VREFC K1 +1.35VS_VGA +FBB_VREFC K1 +1.35VS_VGA


RG121 VREFC VREFC
549_0402_1% C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
[31] FB_B_CMD2 RESET# VDDQ2 [31] FB_B_CMD18 RESET# VDDQ2
H1 H1
2

VDDQ3 L1 VDDQ3 L1
1 2 +FBB_VREFC W=16mils B1
VSS1
VDDQ4
VDDQ5
P1 B1
VSS1
VDDQ4
VDDQ5
P1
D1 T1 D1 T1
VSS2 VDDQ6 VSS2 VDDQ6
1

820P_0402_25V7
1K_0402_1%

820P_0402_25V7

CG572
RG123

CG571

RG122 @ 1 1 F1 J2 F1 J2
931_0402_1% G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
VSS5 VDDQ9 VSS5 VDDQ9
1

D
@ N1 F4 N1 F4
2 QG3 2@ 2@ R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
[25,35,37,38] MEM_VREF
2

G MESS138W-G_SOT323-3 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4


S A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
3

V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5


C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
Close to GDDR6 UG13 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14 Close to GDDR6 UG14 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

P4 P14 P4 P14
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
2 2 2 2 VSS24 VDDQ28 2 2 2 2 VSS24 VDDQ28
+1.35VS_VGA +1.35VS_VGA
CG574
CG573

CG638

CG639

CG640
CG575

CG642
CG577

C5 C5
T5 VSS25 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
1 1 1 1 T10 VSS27 VDD1 V1 1 1 1 1 T10 VSS27 VDD1 V1
3 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2 3
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13 22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13
Around GDDR6 UG13 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
Around GDDR6 UG14 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
VSS39 VSS39
CG582
CG581
CG579

CG580
CG583

CG584

CG648

CG645

CG649

CG646
10U_0603_6.3V6M

CG644

CG647
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
N12 N12
R12 VSS40 A5 R12 VSS40 A5
2 2 1 1 1 1 1 1 VSS41 VPP1 2 2 1 1 1 1 1 1 VSS41 VPP1
CG578

CG576

CG643

CG641
T12 V5 T12 V5
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
1 1 2 2 2 2 2 2 VSS44 VPP4 1 1 2 2 2 2 2 2 VSS44 VPP4
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
B14

22U_0603_6.3V6M

22U_0603_6.3V6M
B14
D14 VSS45 D14 VSS45
F14 VSS46 G5 F14 VSS46 G5
G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
M14 VSS48 NC2 M14 VSS48 NC2
N14 VSS49 N14 VSS49
R14 VSS50 R14 VSS50
U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6

4.7UF_0402 X 1 pcs 4.7UF_0402 X 1 pcs MT61K256M32JE-13-A_FBGA180~D


0.47UF_0201 X 36 pcs MT61K256M32JE-13-A_FBGA180~D 0.47UF_0201 X 36 pcs
+1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON +1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON

Close to GDDR6 UG13 Close to +1V8_AON Close to GDDR6 UG14 Close to +1V8_AON
0.47U_0201_6.3V6K CG6617

0.47U_0201_6.3V6K CG6594

0.47U_0201_6.3V6K CG6596

0.47U_0201_6.3V6K CG6597

0.47U_0201_6.3V6K CG6599

0.47U_0201_6.3V6K CG6600

0.47U_0201_6.3V6K CG6601

0.47U_0201_6.3V6K CG6612

CG625

CG621

CG623

0.47U_0201_6.3V6K CG6633

0.47U_0201_6.3V6K CG6638

0.47U_0201_6.3V6K CG6648

CG674

CG676
0.47U_0201_6.3V6K CG6598

0.47U_0201_6.3V6K CG6615

0.47U_0201_6.3V6K CG6595

CG622

CG624

0.47U_0201_6.3V6K CG6653

0.47U_0201_6.3V6K CG6634

0.47U_0201_6.3V6K CG6636

0.47U_0201_6.3V6K CG6635

0.47U_0201_6.3V6K CG6650

0.47U_0201_6.3V6K CG6652

0.47U_0201_6.3V6K CG6632

CG678

0.47U_0201_6.3V6K CG6803

CG677
0.47U_0201_6.3V6K CG6616

0.47U_0201_6.3V6K CG6630

0.47U_0201_6.3V6K CG6631

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA


4 4
0.47U_0201_6.3V6K CG6610

0.47U_0201_6.3V6K CG6620

0.47U_0201_6.3V6K CG6625

0.47U_0201_6.3V6K CG6624

0.47U_0201_6.3V6K CG6627
0.47U_0201_6.3V6K CG6602

0.47U_0201_6.3V6K CG6629

0.47U_0201_6.3V6K CG6621

0.47U_0201_6.3V6K CG6623

0.47U_0201_6.3V6K CG6622

0.47U_0201_6.3V6K CG6628

0.47U_0201_6.3V6K CG6618

0.47U_0201_6.3V6K CG6651

0.47U_0201_6.3V6K CG6639

0.47U_0201_6.3V6K CG6641

0.47U_0201_6.3V6K CG6640

0.47U_0201_6.3V6K CG6643

0.47U_0201_6.3V6K CG6642

0.47U_0201_6.3V6K CG6647

0.47U_0201_6.3V6K CG6646

0.47U_0201_6.3V6K CG6649

0.47U_0201_6.3V6K CG6656

0.47U_0201_6.3V6K CG6659

0.47U_0201_6.3V6K CG6661
0.47U_0201_6.3V6K CG6614

0.47U_0201_6.3V6K CG6604

0.47U_0201_6.3V6K CG6607

0.47U_0201_6.3V6K CG6609

0.47U_0201_6.3V6K CG6608

0.47U_0201_6.3V6K CG6611

0.47U_0201_6.3V6K CG6613

0.47U_0201_6.3V6K CG6619

0.47U_0201_6.3V6K CG6637

0.47U_0201_6.3V6K CG6665

0.47U_0201_6.3V6K CG6658

0.47U_0201_6.3V6K CG6655

0.47U_0201_6.3V6K CG6657

0.47U_0201_6.3V6K CG6660

0.47U_0201_6.3V6K CG6663

0.47U_0201_6.3V6K CG6664

0.47U_0201_6.3V6K CG6654
0.47U_0201_6.3V6K CG6644

0.47U_0201_6.3V6K CG6662
0.47U_0201_6.3V6K CG6603

0.47U_0201_6.3V6K CG6605

0.47U_0201_6.3V6K CG6606

0.47U_0201_6.3V6K CG6626

0.47U_0201_6.3V6K CG6645

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR6_B_CH2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 36 of 81
A B C D E
A B C D E

VRAM C

1 1

UG15 @ UG16 @
GDDR6 CMD Mapping x16 Mode
Lower 0..31 Upper 32..63
DRAM1 DRAM2 C2 B4 C2 B4
[32] FB_C_EDC0 EDC0_A DQ0_A FB_C_D1 [32] [32] FB_C_EDC4 EDC0_A DQ0_A FB_C_D38 [32]
CHA-Byte 0,1 CHA-Byte 4,5 C13 A3 C13 A3
[32] FB_C_EDC1 EDC1_A DQ1_A FB_C_D7 [32] [32] FB_C_EDC5 EDC1_A DQ1_A FB_C_D34 [32]
T2 B3 T2 B3
[32] FB_C_EDC3 EDC0_B DQ2_A FB_C_D5 [32] [32] FB_C_EDC7 EDC0_B DQ2_A FB_C_D36 [32]
CA0_A CMD0 CMD20 T13 B2 T13 B2
[32] FB_C_EDC2 EDC1_B DQ3_A FB_C_D4 [32] [32] FB_C_EDC6 EDC1_B DQ3_A FB_C_D39 [32]
CA1_A CMD9 CMD28 E3 E3
DQ4_A FB_C_D6 [32] DQ4_A FB_C_D35 [32]
CA2_A CMD8 CMD21 E2 E2
DQ5_A FB_C_D3 [32] DQ5_A FB_C_D32 [32]
CA3_A CMD32 CMD29 D2 F2 D2 F2
[32] FB_C_DBI0 DBI0#_A DQ6_A FB_C_D0 [32] [32] FB_C_DBI4 DBI0#_A DQ6_A FB_C_D33 [32]
CA4_A CMD7 CMD23 D13 G2 D13 G2
[32] FB_C_DBI1 DBI1#_A DQ7_A FB_C_D2 [32] [32] FB_C_DBI5 DBI1#_A DQ7_A FB_C_D37 [32]
CA5_A CMD11 CMD27 R2 B11 R2 B11
[32] FB_C_DBI3 DBI0#_B DQ8_A FB_C_D14 [32] [32] FB_C_DBI7 DBI0#_B DQ8_A FB_C_D40 [32]
CA6_A CMD15 CMD30 R13 A12 R13 A12
[32] FB_C_DBI2 DBI1#_B DQ9_A FB_C_D15 [32] [32] FB_C_DBI6 DBI1#_B DQ9_A FB_C_D43 [32]
CA7_A CMD14 CMD31 B12 B12
DQ10_A FB_C_D8 [32] DQ10_A FB_C_D46 [32]
CA8_A CMD3 CMD19 B13 B13
DQ11_A FB_C_D12 [32] DQ11_A FB_C_D42 [32]
CA9_A CMD1 CMD17 J10 E12 J10 E12
[32] FB_C_CLK0 CK_T DQ12_A FB_C_D13 [32] [32] FB_C_CLK1 CK_T DQ12_A FB_C_D44 [32]
CABI_A CMD6 CMD22 K10 E13 K10 E13
[32] FB_C_CLK#0 CK_C DQ13_A FB_C_D9 [32] [32] FB_C_CLK#1 CK_C DQ13_A FB_C_D45 [32]
CKE_A CMD10 CMD26 G10 F13 G10 F13
[32] FB_C_CMD10 CKE#_A DQ14_A FB_C_D11 [32] [32] FB_C_CMD26 CKE#_A DQ14_A FB_C_D47 [32]
M10 G13 M10 G13
CKE#_B DQ15_A FB_C_D10 [32] CKE#_B DQ15_A FB_C_D41 [32]
CHB-Byte 2,3 CHB-Byte 6,7
CA0_B CMD4 CMD16 U4 U4
DQ0_B FB_C_D25 [32] DQ0_B FB_C_D56 [32]
CA1_B CMD12 CMD25 V3 V3
DQ1_B FB_C_D29 [32] DQ1_B FB_C_D57 [32]
CA2_B CMD5 CMD24 U3 U3
DQ2_B FB_C_D28 [32] DQ2_B FB_C_D58 [32]
CA3_B CMD13 CMD33 J5 U2 J5 U2
[32] FB_C_CMD6 CABI#_A DQ3_B FB_C_D31 [32] [32] FB_C_CMD22 CABI#_A DQ3_B FB_C_D59 [32]
CA4_B CMD7 CMD23 K5 P3 K5 P3
CABI#_B DQ4_B FB_C_D26 [32] CABI#_B DQ4_B FB_C_D60 [32]
CA5_B CMD11 CMD27 P2 P2
DQ5_B FB_C_D24 [32] DQ5_B FB_C_D61 [32]
CA6_B CMD15 CMD30 N2 N2
DQ6_B FB_C_D30 [32] DQ6_B FB_C_D62 [32]
CA7_B CMD14 CMD31 M2 M2
DQ7_B FB_C_D27 [32] DQ7_B FB_C_D63 [32]
CA8_B CMD3 CMD19 U11 U11
DQ8_B FB_C_D23 [32] DQ8_B FB_C_D51 [32]
CA9_B CMD1 CMD17 V12 V12
DQ9_B FB_C_D20 [32] DQ9_B FB_C_D50 [32]
CABI_B CMD6 CMD22 RG105 2 1 121_0402_1% J14 U12 RG577 2 1 121_0402_1% J14 U12
ZQ_A DQ10_B FB_C_D22 [32] ZQ_A DQ10_B FB_C_D48 [32]
CKE_B CMD10 CMD26 RG106 2 1 121_0402_1% K14 U13 RG578 2 1 121_0402_1% K14 U13
ZQ_B DQ11_B FB_C_D21 [32] ZQ_B DQ11_B FB_C_D49 [32]
P12 P12
DQ12_B FB_C_D18 [32] DQ12_B FB_C_D53 [32]
RESET* CMD2 CMD18 P13 P13
DQ13_B FB_C_D19 [32] DQ13_B FB_C_D52 [32]
N13 N13
DQ14_B FB_C_D17 [32] DQ14_B FB_C_D55 [32]
M13 M13
DQ15_B FB_C_D16 [32] DQ15_B FB_C_D54 [32]

N5 H3 N5 H3
TCK CA0_A FB_C_CMD0 [32] TCK CA0_A FB_C_CMD20 [32]
F10 G11 F10 G11
TDI CA1_A FB_C_CMD9 [32] TDI CA1_A FB_C_CMD28 [32]
N10 G4 N10 G4
TDO CA2_A FB_C_CMD8 [32] TDO CA2_A FB_C_CMD21 [32]
F5 H12 F5 H12
TMS CA3_A FB_C_CMD32 [32] TMS CA3_A FB_C_CMD29 [32]
H5 H5
2 CA4_A FB_C_CMD7 [32] CA4_A FB_C_CMD23 [32] 2
H10 H10
CA5_A FB_C_CMD11 [32] CA5_A FB_C_CMD27 [32]
J12 J12
CA6_A FB_C_CMD15 [32] CA6_A FB_C_CMD30 [32]
D4 J11 D4 J11
[32] FB_C_WCK01 WCK0_T_A CA7_A FB_C_CMD14 [32] [32] FB_C_WCK45 WCK0_T_A CA7_A FB_C_CMD31 [32]
D5 J4 D5 J4
[32] FB_C_WCK#01 WCK0_C_A CA8_A FB_C_CMD3 [32] [32] FB_C_WCK#45 WCK0_C_A CA8_A FB_C_CMD19 [32]
D11 J3 D11 J3
[32] FB_C_WCKB01 WCK1_T_A CA9_A FB_C_CMD1 [32] [32] FB_C_WCKB45 WCK1_T_A CA9_A FB_C_CMD17 [32]
D10 D10
[32] FB_C_WCKB#01 WCK1_C_A [32] FB_C_WCKB#45 WCK1_C_A
L3 L3
CA0_B FB_C_CMD4 [32] CA0_B FB_C_CMD16 [32]
M11 M11
CA1_B FB_C_CMD12 [32] CA1_B FB_C_CMD25 [32]
R4 M4 R4 M4
[32] FB_C_WCKB23 WCK0_T_B CA2_B FB_C_CMD5 [32] [32] FB_C_WCKB67 WCK0_T_B CA2_B FB_C_CMD24 [32]
R5 L12 R5 L12
[32] FB_C_WCKB#23 WCK0_C_B CA3_B FB_C_CMD7 FB_C_CMD13 [32] [32] FB_C_WCKB#67 WCK0_C_B CA3_B FB_C_CMD23 FB_C_CMD33 [32]
R11 L5 R11 L5
[32] FB_C_WCK23 WCK1_T_B CA4_B FB_C_CMD11 [32] FB_C_WCK67 WCK1_T_B CA4_B FB_C_CMD27
R10 L10 R10 L10
[32] FB_C_WCK#23 WCK1_C_B CA5_B FB_C_CMD15 [32] FB_C_WCK#67 WCK1_C_B CA5_B FB_C_CMD30
K12 K12
+1.35VS_VGA CA6_B K11 FB_C_CMD14 CA6_B K11 FB_C_CMD31
CA7_B K4 FB_C_CMD3 CA7_B K4 FB_C_CMD19
CA8_B K3 FB_C_CMD1 CA8_B K3 FB_C_CMD17
CA9_B CA9_B
1

@ +FBC_VREFC K1 +1.35VS_VGA +FBC_VREFC K1 +1.35VS_VGA


RG132 VREFC VREFC
549_0402_1% C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
[32] FB_C_CMD2 RESET# VDDQ2 [32] FB_C_CMD18 RESET# VDDQ2
H1 H1
2

VDDQ3 L1 VDDQ3 L1
1 2 +FBC_VREFC W=16mils B1
VSS1
VDDQ4
VDDQ5
P1 B1
VSS1
VDDQ4
VDDQ5
P1
D1 T1 D1 T1
VSS2 VDDQ6 VSS2 VDDQ6
1

1K_0402_1%

820P_0402_25V7

820P_0402_25V7
RG134

CG148

CG149

RG133 1 1 F1 J2 F1 J2
931_0402_1% G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
@ VSS5 VDDQ9 VSS5 VDDQ9
1

D N1 F4
@ N1 F4
2 QG4 2@ 2@ R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
[25,35,36,38] MEM_VREF
2

G MESS138W-G_SOT323-3 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4


A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
S
VSS9 VDDQ13
3

V2 VSS9 VDDQ13 U5 V2 U5
C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
Close to GDDR6 UG15 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14 Close to GDDR6 UG16 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
P4 P14 P4 P14
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
2 2 2 2 VSS24 VDDQ28 2 2 2 2 VSS24 VDDQ28
+1.35VS_VGA +1.35VS_VGA
CG684

CG736
CG739

CG735
CG681

CG686

CG685

CG743
C5 C5
T5 VSS25 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
1 1 1 1 T10 VSS27 VDD1 V1 1 1 1 1 T10 VSS27 VDD1 V1
3 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2 3
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13 22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13
Around GDDR6 UG15 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
Around GDDR6 UG16 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
VSS39 VSS39
CG687

CG740
CG733
CG679

CG741

CG738
CG690

CG683

CG734
10U_0603_6.3V6M

10U_0603_6.3V6M
CG682
10U_0603_6.3V6M

CG680

CG737
N12

10U_0603_6.3V6M
N12
R12 VSS40 A5 R12 VSS40 A5
2 2 1 1 1 1 1 1 VSS41 VPP1 2 2 1 1 1 1 1 1 VSS41 VPP1
CG688

CG742
CG689

CG732
T12 V5 T12 V5
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
1 1 2 2 2 2 2 2 VSS44 VPP4 1 1 2 2 2 2 2 2 VSS44 VPP4
22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

B14
22U_0603_6.3V6M

22U_0603_6.3V6M
B14
D14 VSS45 D14 VSS45
F14 VSS46 G5 F14 VSS46 G5
G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
M14 VSS48 NC2 M14 VSS48 NC2
N14 VSS49 N14 VSS49
R14 VSS50 R14 VSS50
U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6

4.7UF_0402 X 1 pcs 4.7UF_0402 X 1 pcs MT61K256M32JE-13-A_FBGA180~D


0.47UF_0201 X 36 pcs MT61K256M32JE-13-A_FBGA180~D 0.47UF_0201 X 36 pcs
+1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON +1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON

Close to GDDR6 UG15 Close to +1V8_AON Close to GDDR6 UG16 Close to +1V8_AON
0.47U_0201_6.3V6K CG6667

0.47U_0201_6.3V6K CG6671

0.47U_0201_6.3V6K CG6686

0.47U_0201_6.3V6K CG6688

CG726

0.47U_0201_6.3V6K CG6725

0.47U_0201_6.3V6K CG6703

0.47U_0201_6.3V6K CG6720
0.47U_0201_6.3V6K CG6670

0.47U_0201_6.3V6K CG6672

CG727

0.47U_0201_6.3V6K CG6702
CG723

0.47U_0201_6.3V6K CG6706

0.47U_0201_6.3V6K CG6710
0.47U_0201_6.3V6K CG6666

0.47U_0201_6.3V6K CG6684

CG718

0.47U_0201_6.3V6K CG6708

0.47U_0201_6.3V6K CG6724

CG770

CG778

CG781

CG769
0.47U_0201_6.3V6K CG6689

0.47U_0201_6.3V6K CG6669

0.47U_0201_6.3V6K CG6674

0.47U_0201_6.3V6K CG6668

CG722

0.47U_0201_6.3V6K CG6705

0.47U_0201_6.3V6K CG6707

0.47U_0201_6.3V6K CG6721

0.47U_0201_6.3V6K CG6704

CG775
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.7U_0402_6.3V6M

0.47U_0201_6.3V6K

4.7U_0402_6.3V6M
0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA


4 4
0.47U_0201_6.3V6K CG6678

0.47U_0201_6.3V6K CG6681

0.47U_0201_6.3V6K CG6683

0.47U_0201_6.3V6K CG6682

0.47U_0201_6.3V6K CG6693

0.47U_0201_6.3V6K CG6697

0.47U_0201_6.3V6K CG6723

0.47U_0201_6.3V6K CG6722

CG783

CG779
0.47U_0201_6.3V6K CG6694

0.47U_0201_6.3V6K CG6696

0.47U_0201_6.3V6K CG6699

0.47U_0201_6.3V6K CG6690

CG780

CG771
0.47U_0201_6.3V6K CG6701

0.47U_0201_6.3V6K CG6695

0.47U_0201_6.3V6K CG6713

0.47U_0201_6.3V6K CG6714

0.47U_0201_6.3V6K CG6717

0.47U_0201_6.3V6K CG6716

0.47U_0201_6.3V6K CG6719

CG772

CG777
0.47U_0201_6.3V6K CG6677

0.47U_0201_6.3V6K CG6676

0.47U_0201_6.3V6K CG6679

0.47U_0201_6.3V6K CG6680

0.47U_0201_6.3V6K CG6685

0.47U_0201_6.3V6K CG6692

0.47U_0201_6.3V6K CG6698

0.47U_0201_6.3V6K CG6700

0.47U_0201_6.3V6K CG6715

0.47U_0201_6.3V6K CG6709

CG784

CG776
0.47U_0201_6.3V6K CG6712

CG774
0.47U_0201_6.3V6K CG6687

0.47U_0201_6.3V6K CG6675

0.47U_0201_6.3V6K CG6673

0.47U_0201_6.3V6K CG6691

0.47U_0201_6.3V6K CG6711

0.47U_0201_6.3V6K CG6718

CG768

CG782

CG773
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR6_C_CH2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 37 of 81
A B C D E
A B C D E

VRAM D (N18G1,N18G0 No Need)

1 1

UG17 @ UG18 @
GDDR6 CMD Mapping x16 Mode
Lower 0..31 Upper 32..63
DRAM1 DRAM2 C2 B4 C2 B4
[32] FB_D_EDC0 EDC0_A DQ0_A FB_D_D5 [32] [32] FB_D_EDC4 EDC0_A DQ0_A FB_D_D35 [32]
CHA-Byte 0,1 CHA-Byte 4,5 C13 A3 C13 A3
[32] FB_D_EDC1 EDC1_A DQ1_A FB_D_D1 [32] [32] FB_D_EDC5 EDC1_A DQ1_A FB_D_D33 [32]
T2 B3 T2 B3
[32] FB_D_EDC3 EDC0_B DQ2_A FB_D_D0 [32] [32] FB_D_EDC7 EDC0_B DQ2_A FB_D_D32 [32]
CA0_A CMD0 CMD20 T13 B2 T13 B2
[32] FB_D_EDC2 EDC1_B DQ3_A FB_D_D3 [32] [32] FB_D_EDC6 EDC1_B DQ3_A FB_D_D37 [32]
CA1_A CMD9 CMD28 E3 E3
DQ4_A FB_D_D6 [32] DQ4_A FB_D_D34 [32]
CA2_A CMD8 CMD21 E2 E2
DQ5_A FB_D_D7 [32] DQ5_A FB_D_D39 [32]
CA3_A CMD32 CMD29 D2 F2 D2 F2
[32] FB_D_DBI0 DBI0#_A DQ6_A FB_D_D2 [32] [32] FB_D_DBI4 DBI0#_A DQ6_A FB_D_D36 [32]
CA4_A CMD7 CMD23 D13 G2 D13 G2
[32] FB_D_DBI1 DBI1#_A DQ7_A FB_D_D4 [32] [32] FB_D_DBI5 DBI1#_A DQ7_A FB_D_D38 [32]
CA5_A CMD11 CMD27 R2 B11 R2 B11
[32] FB_D_DBI3 DBI0#_B DQ8_A FB_D_D13 [32] [32] FB_D_DBI7 DBI0#_B DQ8_A FB_D_D43 [32]
CA6_A CMD15 CMD30 R13 A12 R13 A12
[32] FB_D_DBI2 DBI1#_B DQ9_A FB_D_D14 [32] [32] FB_D_DBI6 DBI1#_B DQ9_A FB_D_D41 [32]
CA7_A CMD14 CMD31 B12 B12
DQ10_A FB_D_D8 [32] DQ10_A FB_D_D42 [32]
CA8_A CMD3 CMD19 B13 B13
DQ11_A FB_D_D12 [32] DQ11_A FB_D_D40 [32]
CA9_A CMD1 CMD17 J10 E12 J10 E12
[32] FB_D_CLK0 CK_T DQ12_A FB_D_D10 [32] [32] FB_D_CLK1 CK_T DQ12_A FB_D_D46 [32]
CABI_A CMD6 CMD22 K10 E13 K10 E13
[32] FB_D_CLK#0 CK_C DQ13_A FB_D_D15 [32] [32] FB_D_CLK#1 CK_C DQ13_A FB_D_D44 [32]
CKE_A CMD10 CMD26 G10 F13 G10 F13
[32] FB_D_CMD10 CKE#_A DQ14_A FB_D_D9 [32] [32] FB_D_CMD26 CKE#_A DQ14_A FB_D_D47 [32]
M10 G13 M10 G13
CKE#_B DQ15_A FB_D_D11 [32] CKE#_B DQ15_A FB_D_D45 [32]
CHB-Byte 2,3 CHB-Byte 6,7
CA0_B CMD4 CMD16 U4 U4
DQ0_B FB_D_D30 [32] DQ0_B FB_D_D56 [32]
CA1_B CMD12 CMD25 V3 V3
DQ1_B FB_D_D28 [32] DQ1_B FB_D_D59 [32]
CA2_B CMD5 CMD24 U3 U3
DQ2_B FB_D_D26 [32] DQ2_B FB_D_D58 [32]
CA3_B CMD13 CMD33 J5 U2 J5 U2
[32] FB_D_CMD6 CABI#_A DQ3_B FB_D_D31 [32] [32] FB_D_CMD22 CABI#_A DQ3_B FB_D_D60 [32]
CA4_B CMD7 CMD23 K5 P3 K5 P3
CABI#_B DQ4_B FB_D_D25 [32] CABI#_B DQ4_B FB_D_D57 [32]
CA5_B CMD11 CMD27 P2 P2
DQ5_B FB_D_D27 [32] DQ5_B FB_D_D62 [32]
CA6_B CMD15 CMD30 N2 N2
DQ6_B FB_D_D29 [32] DQ6_B FB_D_D61 [32]
CA7_B CMD14 CMD31 M2 M2
DQ7_B FB_D_D24 [32] DQ7_B FB_D_D63 [32]
CA8_B CMD3 CMD19 U11 U11
DQ8_B FB_D_D23 [32] DQ8_B FB_D_D49 [32]
CA9_B CMD1 CMD17 G3G2@ V12 G3G2@ V12
DQ9_B FB_D_D21 [32] DQ9_B FB_D_D48 [32]
CABI_B CMD6 CMD22 RG107 2 1 121_0402_1% J14 U12 RG579 2 1 121_0402_1% J14 U12
ZQ_A DQ10_B FB_D_D22 [32] ZQ_A DQ10_B FB_D_D52 [32]
CKE_B CMD10 CMD26 RG108 2 1 121_0402_1% K14 U13 RG580 2 1 121_0402_1% K14 U13
ZQ_B DQ11_B FB_D_D20 [32] ZQ_B DQ11_B FB_D_D50 [32]
P12 G3G2@ P12
DQ12_B FB_D_D17 [32] DQ12_B FB_D_D55 [32]
RESET* CMD2 CMD18 G3G2@ P13 P13
DQ13_B FB_D_D19 [32] DQ13_B FB_D_D53 [32]
N13 N13
DQ14_B FB_D_D16 [32] DQ14_B FB_D_D51 [32]
M13 M13
DQ15_B FB_D_D18 [32] DQ15_B FB_D_D54 [32]

N5 H3 N5 H3
TCK CA0_A FB_D_CMD0 [32] TCK CA0_A FB_D_CMD20 [32]
F10 G11 F10 G11
TDI CA1_A FB_D_CMD9 [32] TDI CA1_A FB_D_CMD28 [32]
N10 G4 N10 G4
TDO CA2_A FB_D_CMD8 [32] TDO CA2_A FB_D_CMD21 [32]
F5 H12 F5 H12
TMS CA3_A FB_D_CMD32 [32] TMS CA3_A FB_D_CMD29 [32]
H5 H5
2 CA4_A FB_D_CMD7 [32] CA4_A FB_D_CMD23 [32] 2
H10 H10
CA5_A FB_D_CMD11 [32] CA5_A FB_D_CMD27 [32]
J12 J12
CA6_A FB_D_CMD15 [32] CA6_A FB_D_CMD30 [32]
D4 J11 D4 J11
[32] FB_D_WCK01 WCK0_T_A CA7_A FB_D_CMD14 [32] [32] FB_D_WCK45 WCK0_T_A CA7_A FB_D_CMD31 [32]
D5 J4 D5 J4
[32] FB_D_WCK#01 WCK0_C_A CA8_A FB_D_CMD3 [32] [32] FB_D_WCK#45 WCK0_C_A CA8_A FB_D_CMD19 [32]
D11 J3 D11 J3
[32] FB_D_WCKB01 WCK1_T_A CA9_A FB_D_CMD1 [32] [32] FB_D_WCKB45 WCK1_T_A CA9_A FB_D_CMD17 [32]
D10 D10
[32] FB_D_WCKB#01 WCK1_C_A [32] FB_D_WCKB#45 WCK1_C_A
L3 L3
CA0_B FB_D_CMD4 [32] CA0_B FB_D_CMD16 [32]
M11 M11
CA1_B FB_D_CMD12 [32] CA1_B FB_D_CMD25 [32]
R4 M4 R4 M4
[32] FB_D_WCKB23 WCK0_T_B CA2_B FB_D_CMD5 [32] [32] FB_D_WCKB67 WCK0_T_B CA2_B FB_D_CMD24 [32]
R5 L12 R5 L12
[32] FB_D_WCKB#23 WCK0_C_B CA3_B FB_D_CMD7 FB_D_CMD13 [32] [32] FB_D_WCKB#67 WCK0_C_B CA3_B FB_D_CMD23 FB_D_CMD33 [32]
R11 L5 R11 L5
[32] FB_D_WCK23 WCK1_T_B CA4_B FB_D_CMD11 [32] FB_D_WCK67 WCK1_T_B CA4_B FB_D_CMD27
R10 L10 R10 L10
[32] FB_D_WCK#23 WCK1_C_B CA5_B FB_D_CMD15 [32] FB_D_WCK#67 WCK1_C_B CA5_B FB_D_CMD30
K12 K12
+1.35VS_VGA CA6_B K11 FB_D_CMD14 CA6_B K11 FB_D_CMD31
CA7_B K4 FB_D_CMD3 CA7_B K4 FB_D_CMD19
CA8_B K3 FB_D_CMD1 CA8_B K3 FB_D_CMD17
CA9_B CA9_B
1

@ +FBD_VREFC K1 +1.35VS_VGA +FBD_VREFC K1 +1.35VS_VGA


RG155 VREFC VREFC
549_0402_1% C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
[32] FB_D_CMD2 RESET# VDDQ2 [32] FB_D_CMD18 RESET# VDDQ2
H1 H1
VDDQ3
2

VDDQ3 L1 L1
1 2 +FBD_VREFC W=16mils B1
VSS1
VDDQ4
VDDQ5
P1 B1
VSS1
VDDQ4
VDDQ5
P1
D1 T1 D1 T1
VSS2 VDDQ6 VSS2 VDDQ6
1

1K_0402_1%

820P_0402_25V7

820P_0402_25V7
G3G2@ RG154

CG256

CG265

RG156 @ 1 1 F1 J2 F1 J2
931_0402_1% G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
VSS5 VDDQ9 VSS5 VDDQ9
1

D
@ N1 F4 N1 F4
2 QG8 2@ 2@ R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
[25,35,36,37] MEM_VREF
2

G MESS138W-G_SOT323-3 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4


S A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
3

V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5


C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
10UF_0603 X 4 pcs +1.35VS_VGA E4 VSS19 VDDQ23 E14
Close to GDDR6 UG17 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14 Close to GDDR6 UG18 H4
L4
VSS20
VSS21
VSS22
VDDQ24
VDDQ25
VDDQ26
H14
L14
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
P4 P14
10U_0603_6.3V6M

P4 P14
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
2 2 2 2 VSS24 VDDQ28 2 2 2 2 VSS24 VDDQ28
+1.35VS_VGA +1.35VS_VGA
G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@
CG789

CG844
G3G2@

CG848
CG785

CG795

CG845

CG840
CG794

C5 C5
T5 VSS25 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
1 1 1 1 T10 VSS27 VDD1 V1 1 1 1 1 T10 VSS27 VDD1 V1
3 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2 3
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
10UF_0603 X 2 pcs C12 VSS34 VDD8 H13
22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13 22UF_0603 X 6 pcs +1.35VS_VGA D12 VSS35 VDD9 L13
Around GDDR6 UG17 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
Around GDDR6 UG18 F12
G12
M12
VSS36
VSS37
VSS38
VDD10
VDD11
VDD12
A14
V14
+1V8_AON
VSS39 VSS39
10U_0603_6.3V6M

CG790

CG787

CG788

CG791

CG849

CG839

CG847
CG796

CG838

CG841
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M
CG792

CG842
N12 N12
R12 VSS40 A5 R12 VSS40 A5
2 2 1 1 1 1 1 1 VSS41 VPP1 2 2 1 1 1 1 1 1 VSS41 VPP1
CG793
CG786

CG843
CG846
T12 V5 T12 V5
A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
1 1 2 2 2 2 2 2 VSS44 VPP4 1 1 2 2 2 2 2 2 VSS44 VPP4
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
B14
22U_0603_6.3V6M

22U_0603_6.3V6M
B14
D14 VSS45 D14 VSS45
VSS46 VSS46
G3G2@
G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@
G3G2@
F14 G5 F14 G5
VSS47 NC1 VSS47 NC1
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@
G3G2@

G14 M5 G14 M5
M14 VSS48 NC2 M14 VSS48 NC2
N14 VSS49 N14 VSS49
R14 VSS50 R14 VSS50
U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6

4.7UF_0402 X 1 pcs 4.7UF_0402 X 1 pcs MT61K256M32JE-13-A_FBGA180~D


0.47UF_0201 X 36 pcs MT61K256M32JE-13-A_FBGA180~D 0.47UF_0201 X 36 pcs
+1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON +1.35VS_VGA 0.47UF_0201 X 4 pcs +1V8_AON

Close to GDDR6 UG17 Close to +1V8_AON Close to GDDR6 UG18 Close to +1V8_AON
0.47U_0201_6.3V6K CG6730

0.47U_0201_6.3V6K CG6745

0.47U_0201_6.3V6K CG6728

0.47U_0201_6.3V6K CG6766

CG878
0.47U_0201_6.3V6K CG6729

CG827

CG823

CG826

0.47U_0201_6.3V6K CG6764

0.47U_0201_6.3V6K CG6765

0.47U_0201_6.3V6K CG6767

0.47U_0201_6.3V6K CG6782

0.47U_0201_6.3V6K CG6784

0.47U_0201_6.3V6K CG6763

CG888
0.47U_0201_6.3V6K CG6748

CG837

0.47U_0201_6.3V6K CG6785

0.47U_0201_6.3V6K CG6762

0.47U_0201_6.3V6K CG6780

CG882

CG889
0.47U_0201_6.3V6K CG6727

0.47U_0201_6.3V6K CG6734

0.47U_0201_6.3V6K CG6768

0.47U_0201_6.3V6K CG6769
0.47U_0201_6.3V6K CG6749

0.47U_0201_6.3V6K CG6726

0.47U_0201_6.3V6K CG6732

0.47U_0201_6.3V6K CG6731

0.47U_0201_6.3V6K CG6744

CG835

CG887
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
0.47U_0201_6.3V6K

0.47U_0201_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
G3G2@

G3G2@

G3G2@
G3G2@

G3G2@
G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@
G3G2@

G3G2@
+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA
4 4
0.47U_0201_6.3V6K CG6755

0.47U_0201_6.3V6K CG6760

0.47U_0201_6.3V6K CG6773
0.47U_0201_6.3V6K CG6737

0.47U_0201_6.3V6K CG6739

0.47U_0201_6.3V6K CG6738

0.47U_0201_6.3V6K CG6740

0.47U_0201_6.3V6K CG6743

0.47U_0201_6.3V6K CG6751

0.47U_0201_6.3V6K CG6753

0.47U_0201_6.3V6K CG6754

0.47U_0201_6.3V6K CG6759

0.47U_0201_6.3V6K CG6758

0.47U_0201_6.3V6K CG6772

0.47U_0201_6.3V6K CG6777

0.47U_0201_6.3V6K CG6779

0.47U_0201_6.3V6K CG6778

0.47U_0201_6.3V6K CG6781

0.47U_0201_6.3V6K CG6789

0.47U_0201_6.3V6K CG6795

0.47U_0201_6.3V6K CG6794
0.47U_0201_6.3V6K CG6736

0.47U_0201_6.3V6K CG6741

0.47U_0201_6.3V6K CG6752

0.47U_0201_6.3V6K CG6771

0.47U_0201_6.3V6K CG6775

0.47U_0201_6.3V6K CG6770

0.47U_0201_6.3V6K CG6787

0.47U_0201_6.3V6K CG6793

0.47U_0201_6.3V6K CG6792
0.47U_0201_6.3V6K CG6747

0.47U_0201_6.3V6K CG6735

0.47U_0201_6.3V6K CG6733

0.47U_0201_6.3V6K CG6786
0.47U_0201_6.3V6K CG6742

0.47U_0201_6.3V6K CG6746

0.47U_0201_6.3V6K CG6761

0.47U_0201_6.3V6K CG6757

0.47U_0201_6.3V6K CG6756

0.47U_0201_6.3V6K CG6750

0.47U_0201_6.3V6K CG6783

0.47U_0201_6.3V6K CG6774

0.47U_0201_6.3V6K CG6776

0.47U_0201_6.3V6K CG6797

0.47U_0201_6.3V6K CG6788

0.47U_0201_6.3V6K CG6791

0.47U_0201_6.3V6K CG6790

0.47U_0201_6.3V6K CG6796
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Chage:0.47uF 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1. 0401 --> 0201
G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@
G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@

G3G2@
2. X5R --> X7R or X6S

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR6_D_CH2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 38 of 81
A B C D E
A B C D E

RG1569 1 @ 2 0_0402_5%
+3VL +3V_OVRM
RG1570 1 @ 2 0_0402_5%
+3VS +3V_OVRM
Power Monitor(OVR-M) +3V_OVRM

1
CG343

1U_0402_6.3V6K
2

UG19 @ +3V_OVRM
1 CSSP_B+ BS_IN1 1
RG259 1 2 75K_0402_1% 3 27
CSSP_NVVDD RG227 1 2 75K_0402_1% BS_IN2 6 BS_IN1 VCC
BS_IN2

1000P_0402_50V7K

1000P_0402_50V7K
RG1533 1 @ 2 0_0402_5% BS_IN3 11 2 SH_IN_P1 RG238 1 2 100_0402_1% CSSP_B+
BS_IN4 BS_IN3 SH_IN_P1 SH_IN_N1 CSSN_B+ CSSP_B+ [74]
RG1534 1 @ 2 0_0402_5% 14 1 RG239 1 @ 2 0_0402_5%
BS_IN4 SH_IN_N1 CSSN_B+ [74]

1
5 SH_IN_P2 RG240 1 2 100_0402_1% CSSP_NVVDD
SH_IN_P2 SH_IN_N2 CSSN_NVVDD CSSP_NVVDD [74]
CG341 CG342 RG225 1 @ 2 649_0402_1% 4 RG241 1 @ 2 0_0402_5%
SH_IN_N2 SH_IN_P3 CSSN_NVVDD [74]
RG226 1 @ 2 649_0402_1% 9 12 RG1551 1 2 10K_0201_5%

2
GND_FET SH_IN_P3 13 SH_IN_N3 RG1552 1 2 10K_0201_5%
RG235 1 @ 2 0_0402_5% SH_IN_N3 15 SH_IN_P4 RG1553 1 2 10K_0201_5% @
32 SH_IN_P4 16 SH_IN_N4 RG1554 1 2 10K_0201_5% CG344 1 2 47P_0402_50V8J
SH_O1 SH_IN_N4 +3V_OVRM
7
10 SH_O2 20
+3V_OVRM SH_O3 DIFF_OUT_P ADC_IN_P [25]

0.015U_0402_25V7K
@ 17 19
SH_O4 DIFF_OUT_N ADC_IN_N [25]

1
1
BS_OK

0.015U_0402_25V7K
1 1 30 RG1549 1 @ 2 10K_0402_1% +3V_OVRM
BS_OK

2 RG1535 1

2 RG1536 1
1

0_0402_5%

0_0402_5%
287_0402_1% RG228

CG350
287_0402_1% RG222
RG251 @
@ RG236 1 2 0_0402_5% 29 8
[25] ADC_MUX_SEL MUX_SEL NC

2
2
1K_0402_5%
18
2 2 NC

CG351
21 RG242 RG243 @ @

2
2
OVRM_EN# 28 NC 31 @ 243K_0402_1% 365K_0402_1%

2
ENABLE NC

47P_0402_50V8J
47P_0402_50V8J
23

1
1
BG_REF_OUT

1
1

CG346
CG345
25 24
SKIP BS_REF 22
CM_REF_IN @ @

2
2
26 33 2 2 2
MODE_SEL GND

2
2
1000p_0402_50V7K

1000p_0402_50V7K

1000p_0402_50V7K
CG347

CG348

CG349
RG244
Change CG350 & CG351 SE00000TM00 to SE075153K80 NCP45491XMNTWG_QFN32_4X4 RG245 681K_0402_1%

1
RG1548 1 1 1 10K_0402_5%

10K_0402_5%

1
1
@ @
RG644 1 2 0_0201_5%
[46,48,55,61] S5_PWR_EN#

2
1
RG232

10K_0201_5%
2 2

2
OVR-M(OnSemi)
RG225 ON@ RG226 ON@ UG19 ON@

ON ON ON

649_0402_1% 649_0402_1% NCP45491

RG222 ON@ RG228 ON@ RG644 ON@

ON ON ON

287_0402_1% 287_0402_1% 0_0201_5%


3 3
RG242 ON@ RG1569 ON@

ON ON

243K_0402_1% 0_0402_5%

OVR-M(UPI)
RG225 UPI@ RG226 UPI@ UG19 UPI@

UPI UPI UPI

487_0402_1% 487_0402_1% US5650QQKI


RG222 RG228
UPI@ UPI@

UPI UPI

215_0402_1% 215_0402_1%

4 RG242 UPI@ RG1570 UPI@ 4

UPI UPI

324K_0402_1% 0_0402_5%

Reference ORB R997 ,R923 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OVR-M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 39 of 81
A B C D E
A B C D E

L Y 1

O N
O
2 2

O V
3

EN www.teknisi-indonesia.com
3

L
O R
F
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 40 of 81
A B C D E
5 4 3 2 1

+3VS

2
RV21
4.7K_0402_1%
@
D D
I2C Control EnableI Internal pull down at I150KI, �3.3V I/O.

1
I2C_CTL_EN L: Pin Control is selected. (default)
H: I2C control is selected with default address 0x66/67

1
+3VS M: I2C control is selected with alternat i ve addr ess 0x D8/ D9
RV22
4.7K_0402_1%

2
RV19
100K_0402_5%

2
+3VS
MUX_EDP_AUXN [42]
MUX_EDP_AUXP [42]

Automat i c E Q di sabl eI I nt er nal pull do wn at I150KI, 3. 3V I / O.
L: Automat i c E Q enabl e ( def aul t)

1
+3VS
H: Automat i c E Q di sabl e 1 1 RV20
100K_0402_5%

2
CV437 CV436 UV21
0.1U_0201_10V6K 0.1U_0201_10V6K 21 RV623

2
2 2 26 VDD33 4.7K_0402_1%
35 VDD33 @
VDD33
49 32 Auto test enableI Internal pull down at I150KI, �3.3V I/O.

1
60 VDD33 OUT_AUXp_SCL 31
VDD33 OUT_AUXn_SDA PI0 L: Auto test disable & input of fs et cancell at i on enabl e ( def ault)
[18,25,46,48,51] EC_SMB_CK2
RV632 1 @ 2 0_0402_5% IN2_PEQ# 51
IN2_PEQ/SCL_CTL
H: Auto test enable & input of fs et cancell at i on enable

1
RV633 1 @ 2 0_0402_5% IN1_PEQ# 52 53 I2C_CTL_EN M: Auto test disable & input of fs et cancell at i on di s able
[18,25,46,48,51] EC_SMB_DA2 IN1_PEQ/SDA_CTL I2C_CTL_EN
RV634 1 2 4.7K_0402_1% 59 RV622
RV635 1 2 4.7K_0402_1% 58 IN1_AEQ# 4.7K_0402_1%
+3VS IN2_AEQ# 56 PI0 @
PI0 38 PC0

2
0.1U_0201_6.3V6K 2 1 CV416 GPU_TX0P_C 1 PC0 55 PC1
[27] GPU_EDP_TXP0 GPU_TX0N_C IN1_D0p PC1
0.1U_0201_6.3V6K 2 1 CV417 2
[27] GPU_EDP_TXN0 GPU_TX1P_C IN1_D0n
0.1U_0201_6.3V6K 2 1 CV418 4 RV23
[27] GPU_EDP_TXP1 GPU_TX1N_C IN1_D1p
0.1U_0201_6.3V6K 2 1 CV419 5 1M_0402_5%
[27] GPU_EDP_TXN1 IN1_D1n

GPU
0.1U_0201_6.3V6K 2 1 CV420 GPU_TX2P_C 6 48 2 1
[27] GPU_EDP_TXP2 GPU_TX2N_C IN1_D2p CA_DET
C 0.1U_0201_6.3V6K 2 1 CV421 7 C
[27] GPU_EDP_TXN2 GPU_TX3P_C IN1_D2n
0.1U_0201_6.3V6K 2 1 CV422 9
[27] GPU_EDP_TXP3 GPU_TX3N_C IN1_D3p
0.1U_0201_6.3V6K 2 1 CV423 10 46
[27] GPU_EDP_TXN3 IN1_D3n OUT_D0p MUX_EDP_A0P [42]
45
OUT_D0n MUX_EDP_A0N [42]

To eDP connector
0.1U_0201_6.3V6K 2 1 CV424 GPU_AUXP/DDC_C 28 43
[27] GPU_EDP_AUXP GPU_AUXN/DDC_C IN1_AUXp OUT_D1p MUX_EDP_A1P [42]
0.1U_0201_6.3V6K 2 1 CV425 27 42
[27] GPU_EDP_AUXN IN1_AUXn OUT_D1n MUX_EDP_A1N [42]
23 40
IN1_SCL OUT2_D2p MUX_EDP_A2P [42]
22 39
IN1_SDA OUT2_D2n MUX_EDP_A2N [42]
37
OUT_D3p MUX_EDP_A3P [42]
36
CPU_EDP_P0_C OUT_D3n MUX_EDP_A3N [42]
0.1U_0201_6.3V6K 2 1 CV426 11
[6] EDP_TXP0 CPU_EDP_N0_C IN2_D0p
0.1U_0201_6.3V6K 2 1 CV427 12
[6] EDP_TXN0 CPU_EDP_P1_C IN2_D0n EDP_SW
0.1U_0201_6.3V6K 2 1 CV428 14 54 Port switching control conf i gur at i onI Inter nal pul l d ow
n
[6] EDP_TXP1 CPU_EDP_N1_C IN2_D1p SW
0.1U_0201_6.3V6K 2 1 CV429 15
[6] EDP_TXN1 IN2_D1n at I150KI,� 3.3V I/O.

CPU
0.1U_0201_6.3V6K 2 1 CV430 CPU_EDP_P2_C 16 44
[6] EDP_TXP2 IN2_D2p OUT_HPD EDP_HPD [42]
[6] EDP_TXN2
0.1U_0201_6.3V6K 2 1 CV431 CPU_EDP_N2_C 17
IN2_D2n
L: Input Port1 is selected (default)
0.1U_0201_6.3V6K 2 1 CV432 CPU_EDP_P3_C 19 H: Input Port2 is selected
[6] EDP_TXP3 CPU_EDP_N3_C IN2_D3p
0.1U_0201_6.3V6K 2 1 CV433 20
[6] EDP_TXN3 IN2_D3n 34
0.1U_0201_6.3V6K 2 1 CV434 CPU_EDP_AUX_C 30 REXT 47
[6] EDP_AUXP CPU_EDP_AUX#_C IN2_AUXp CEXT
0.1U_0201_6.3V6K 2 1 CV435 29
[6] EDP_AUXN IN2_AUXn
+3VS 25
IN2_SCL

1
24 8 1
IN2_SDA GND 18 CV438 RV24
GND
2

33 2.2U_0402_6.3V6M 4.99K_0402_1%
RV629 3 GND 41
[25] EDP_HPD_GPU IN1_HPD GND 2
4.7K_0402_1% 13 57
[16] EDP_HPD_CPU

2
IN2_HPD GND 61
Epad 50
1

PD
IN1_PEQ# PS8331BQFN60GTR-A2 QFN
SA000060U10
+3VS
1

RV628

2
4.7K_0402_1%
RV625
4.7K_0402_1%
2


Programmable input ePualiPat i on l evel sI I nt er nal pull do wn at I150KI, 3. 3V I / O. @
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2 AUX intercept i on di sabl e f or Port y ( y A 1, 2). I nt er nal pull do wn at I150K �I, 3. 3V I / OI

1
B B

H: HEQ, compensate channel loss up to 14.5dB @ HBR2 PC0 L: AUX intercept i on enabl e, dri ver c onf i gur at i on i s set by l i nk tr ai ni ng (defaut)l
+3VS M: LLEQ, compensate channel loss up to 8.5dB @ HBR2 H: AUX intercept i on di sabl e, dri ver out put wit h f i xed 80 0mV and 0d B

1
M: AUX intercept i on di sabl e, dri ver out put wit h f i xed 40 0mV and 0d B
RV624
2

4.7K_0402_1%
RV631 @
4.7K_0402_1%

2
1

IN2_PEQ# +5VS
1

1
RV630
4.7K_0402_1% CV484 +3VS
0.1U_0201_10V6K UV23
2 16
2

Vcc
2

4 +3VS
1A INV_PWM [42]
2 7 RV659
[25] GPU_BKL_PWM 1B1 2A INV_ENVDD [42]
3 9 10K_0402_5%
[17] PCH_BKL_PWM 1B2 3A INV_ENBKL [48]

2
5 12
[25] DGPU_ENVDD 2B1 4A
6 RV627
[17] PCH_ENVDD
1

11 2B2 15 4.7K_0402_1%
[25] GPU_ENBKL 3B1 OE EDP_SW
10 1 @
[17] ENBKL 3B2 S EDP_SW [19,48]
14 �3.3V I/OI
Output swing adjustment for Port y (y A 1, 2). Internal pull down at I150KI,

1
13 4B1 8
4B2 GND L: default
2

17 PC1
T-PAD RV701 H: +20%

1
CBT3257ABQ_DHVQFN16_2P5X3P5 @ 10K_0402_5% M: -16.7%
RV626
4.7K_0402_1%
1

2
S1 OE output function
A A

L L A=B1 DGPU
H L A=B2 IGPU
X H

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP MUX PS8331B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 41 of 81
5 4 3 2 1
5 4 3 2 1

LCD Power Circuit


W=60mils
+3VS +LCDVDD_CONN
D
UV20
Camera D
W=60mils 5 1 +LCDVDD RV345 1 @ 2 0_0805_5%
IN OUT +3VS

CV275
2 1@ 1@ 1@

4.7U_0402_6.3V6K
GND 1 1

CV308

CV310

CV311
CV309
1 W=20mils

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M
INV_ENVDD 4 3
CV274 EN OC
2 2 2 2 2 1
1U_0201_6.3V6M G5016KD1U SOT23
2 CV276
10U_0402_6.3V6M
2

[41] INV_ENVDD

1
RV346
100K_0402_5%
Close JEDP1 pin 33

2
RV347 1 @ 2 0_0805_5% +LEDVDD
W=100mils
+19VB

10U_0603_25V6M
1
@
eDP CONN.

2
C485
JEDP1
1
2 1
3 2
4 3
C C
GSYNC# 5 4
[25] GSYNC# 5
INV_PWM 6
INV_PWM DISPOFF# 7 6
[41] INV_PWM EDP_HPD 7
[41] EDP_HPD 8
8
1

+LCDVDD_CONN 9
10 9
RV693
W=80mils 11 10
100K_0402_5% 12 11
13 12
2

MUX_EDP_AUXN CV277 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 14 13


eDP [41] MUX_EDP_AUXN MUX_EDP_AUXP CV278 1 2 0.1U_0201_10V K X5R EDP_AUXP_C 15 14
[41] MUX_EDP_AUXP MUX_EDP_A0P EDP_TXP0_C 15
CV279 1 2 0.1U_0201_10V K X5R 16
[41] MUX_EDP_A0P MUX_EDP_A0N EDP_TXN0_C 16
CV280 1 2 0.1U_0201_10V K X5R 17
[41] MUX_EDP_A0N MUX_EDP_A1P EDP_TXP1_C 17
CV281 1 2 0.1U_0201_10V K X5R 18
[41] MUX_EDP_A1P MUX_EDP_A1N EDP_TXN1_C 18
CV282 1 2 0.1U_0201_10V K X5R 19
[41] MUX_EDP_A1N MUX_EDP_A2P EDP_TXP2_C 19
CV283 1 2 0.1U_0201_10V K X5R 20
[41] MUX_EDP_A2P MUX_EDP_A2N EDP_TXN2_C 20
CV284 1 2 0.1U_0201_10V K X5R 21
[41] MUX_EDP_A2N MUX_EDP_A3P EDP_TXP3_C 21
@ CV285 1 2 0.1U_0201_10V K X5R 22
[41] MUX_EDP_A3P MUX_EDP_A3N EDP_TXN3_C 22
From EC RV349 1 2 0_0402_5% DISPOFF# CV286 1 2 0.1U_0201_10V K X5R 23
[48] BKOFF# [41] MUX_EDP_A3N 23
24
25 24
25
1

26
RV351 27 26
100K_0402_5% 28 27
29 28
30 29
2

31 30
[14] USB20_P7 31
32
[14] USB20_N7 32
Camera W=20mils 33
34 33
+3VS 34
DMIC_CLK 35
[45] DMIC_CLK DMIC_DAT 35
DMIC 36
[45] DMIC_DAT 36
+5VALW 37
R613 1 2 22_0402_5% 38 37
[62] LOGO_R 38
A-Logo R614 1 2 22_0402_5% 39
[62] LOGO_G 39
R615 1 2 22_0402_5% 40
[62] LOGO_B 40
B B
41
42 GND
43 GND

EMI For S3 EC control 44 GND


GND

1
DMIC_CLK
DMIC_DAT STARC_300E40-1010RA-G3
R635 @ ME@
510_0402_1%
DMIC_CLK

2
3

10P_0402_50V8J
3

1
D

@EMI@
1

CV287
DV18 2
[48,62] S3_LED#
L03ESDL5V0CG3-2_SOT-523-3 G
@ESD@ @ S

3
2 Q55
1

L2N7002WT1G_SC-70-3
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 42 of 81
5 4 3 2 1
5 4 3 2 1

RV292 1 EMI@ 2 2.2_0201_1%

+3VS
2 1 TMDS_C_TXCN TMDS_R_TXCN
[27] TMDS_TXCN
CV238 0.1U_0201_6.3V6K

2 1 TMDS_C_TXCP TMDS_R_TXCP
[27] TMDS_TXCP
CV239 0.1U_0201_6.3V6K QV100

1
C LMBT3904WT1G_SC70-3
D HDMI_HPD_CONN D
1 EMI@ 2 2 1 2
RV295 2.2_0201_1% +1V8_AON B
E RV336

3
150K_0402_5% 1
RV297 1 EMI@ 2 2.2_0201_1%
CV300 @
[19] HDMI_HPD_PCH

1
0.1U_0402_16V7K
2 1 TMDS_C_TX0N TMDS_R_TX0N RV322 2
[27] TMDS_TX0N

1
CV242 0.1U_0201_6.3V6K 10K_0402_5%
RV320
2 1 TMDS_C_TX0P TMDS_R_TX0P 10K_0402_5%
[27] TMDS_TX0P

2
CV243 0.1U_0201_6.3V6K
[25] HDMI_HPD_GPU#

2
6
1 EMI@ 2
RV300 2.2_0201_1% QV97A
DMN53D0LDW-7 2N SOT363-6
2
RV301 1 EMI@ 2 2.2_0201_1%

1
2 1 TMDS_C_TX1N TMDS_R_TX1N
[27] TMDS_TX1N
CV244 0.1U_0201_6.3V6K

2 1 TMDS_C_TX1P TMDS_R_TX1P
[27] TMDS_TX1P
CV245 0.1U_0201_6.3V6K

1 EMI@ 2
RV303 2.2_0201_1%

RV304 1 EMI@ 2 2.2_0201_1% +HDMI_5V_OUT


+5VS UV14

2 1 TMDS_C_TX2N TMDS_R_TX2N 3
W=40mils
[27] TMDS_TX2N OUT
CV246 0.1U_0201_6.3V6K

10U_0402_6.3V6M

0.1U_0201_6.3V6K
1
2 1 TMDS_C_TX2P TMDS_R_TX2P IN
C 1 1 C
[27] TMDS_TX2P

CV240

CV241
CV247 0.1U_0201_6.3V6K 2
GND @
1 EMI@ 2
RV306 2.2_0201_1% AP2330W-7_SC59-3 2 2
SA00004ZA00

teknisi-indonesia.com
+3VS

1
W=60 mils RV299
@ 10K_0402_5%
+HDMI_5V_OUT TMDS_C_TX0N RV307 1 2 499_0201_1%
+1V8_AON TMDS_C_TX0P RV308 1 2 499_0201_1% JHDMI1

2
TMDS_C_TXCN RV309 1 2 499_0201_1% HDMI_HPD_CONN 19
TMDS_C_TXCP RV310 1 2 499_0201_1% 18 HP_DET
17 +5V
TMDS_CTRLDAT_R 16 DDC/CEC_GND
DB2J31400L_SOD323-2

DB2J31400L_SOD323-2

TMDS_CTRLCLK_R 15 SDA
SCL
2

TMDS_C_TX1N RV311 1 2 499_0201_1% 14


+1V8_AON TMDS_C_TX1P RV312 1 2 499_0201_1% 13 Reserved
CEC
DV12

DV13

TMDS_C_TX2N RV313 1 2 499_0201_1% TMDS_R_TXCN 12 20


TMDS_C_TX2P RV314 1 2 499_0201_1% 11 CK- GND 21
TMDS_R_TXCP 10 CK_shield GND 22
TMDS_R_TX0N 9 CK+ GND 23
8 D0- GND
1

TMDS_R_TX0P D0_shield
5.1K_0402_5%

5.1K_0402_5%

7
D0+
1

+3VS HDMI_Down TMDS_R_TX1N 6


D1-
2

2
2K_0402_5%

2K_0402_5%
RV317

5
D1_shield

1
D
RV318

RV319
RV316

TMDS_R_TX1P 4
2 QV99 TMDS_R_TX2N 3 D1+
G 2 D2-
L2N7002WT1G_SC-70-3
2

D2_shield

1
@ S TMDS_R_TX2P 1
1

3
RV315 D2+
5

B B
100K_0402_5% ACON_HMRB4-AK1L0C
G

ME@
HDMI_CTRLCLK 4 3 TMDS_SCLF 2 1 TMDS_CTRLCLK_R
[27] HDMI_CTRLCLK

2
S

PJT138KA 2N SOT363-6 RV321


To GPU
2

QV96A 33_0402_1%
G

HDMI_CTRLDAT 1 6 TMDS_SDAF 2 1 TMDS_CTRLDAT_R


[27] HDMI_CTRLDAT
S

PJT138KA 2N SOT363-6 RV323


QV96B 33_0402_1%

TMDS_CTRLCLK_R
TMDS_CTRLDAT_R
10P_0402_50V8J
10P_0402_50V8J

1 1
RF@ RF@
CV304 CV305
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 43 of 81
5 4 3 2 1
5 4 3 2 1

+3VS

QV102

1
C LMBT3904WT1G_SC70-3
D mDP_HPD D
2 1 2
B
E RV338

3
+1V8_AON 150K_0402_5% 1
CV301 @
[19] DP_HPD_PCH 0.1U_0402_16V7K

1
2

1
RV698
10K_0402_5% RV337
10K_0402_5%

2
[25] DP_HPD_GPU#

2
3
QV97B
DMN53D0LDW-7 2N SOT363-6
5
+5VS +3VS

4
1

100K_0201_5%
2.2K_0201_5%
2.2K_0201_5%
CV251

1
2
0.1U_0201_6.3V6K

RV326

RV327
RV325
2

UV13

2
1
16
Vcc 4 DISP_CLK_AUXP_CONN
GPU_DPC_AUX 0.1U_0201_6.3V6K 2 1 CV256 DP_AUXP_C 2 1A 7 DISP_DAT_AUXN_CONN
mDP_AUX_SCL 3 1B1 2A 9
GPU_DPC_AUX# 0.1U_0201_6.3V6K 2 1 CV258 DP_AUXN_C 5 1B2 3A 12
mDP_AUX#_SDA 6 2B1 4A
11 2B2 15
3B1 OE DP_CBL_DET 1V8_MAIN_EN_R [34]
10 1
14 3B2 S
C C
4B1

2
13 8
4B2 GND 17 RV329 RV328
T-PAD 1M_0201_1% 100K_0201_5%
CBT3257ABQ_DHVQFN16_2P5X3P5
2

1
JDP1
1
mDP_HPD 2 GND
CV250 1 2 0.1U_0201_6.3V6K mDP_LANE_P0_C 3 HP_DET
[27] GPU_mDP_P0 DP_CBL_DET LAN0+
4
CV252 1 2 0.1U_0201_6.3V6K mDP_LANE_N0_C 5 CONFIG1
[27] GPU_mDP_N0 DISP_CEC LAN0-
RV18 1 2 5.1M_0402_5% 6
7 CONFIG2
8 GND 24
CV253 1 2 0.1U_0201_6.3V6K mDP_LANE_P1_C 9 GND GND 23
[27] GPU_mDP_P1 mDP_LANE_P3_C LAN1+ GND
CV254 1 2 0.1U_0201_6.3V6K 10 22
[27] GPU_mDP_P3 mDP_LANE_N1_C LAN3+ GND
CV255 1 2 0.1U_0201_6.3V6K 11 21
[27] GPU_mDP_N1 mDP_LANE_N3_C LAN1- GND
CV257 1 2 0.1U_0201_6.3V6K 12
[27] GPU_mDP_N3 LAN3-
13
14 GND
CV259 1 2 0.1U_0201_6.3V6K mDP_LANE_P2_C 15 GND
mDP_AUX_SCL [27] GPU_mDP_P2 DISP_CLK_AUXP_CONN LAN2+
16
CV260 1 2 0.1U_0201_6.3V6K mDP_LANE_N2_C 17 AUX_CH+
[27] GPU_mDP_N2 DISP_DAT_AUXN_CONN LAN2-
18
mDP_AUX#_SDA 19 AUX_CH-
20 GND
+3VS_DP DP_PWR
+3VS UV18
RV332 1 @ 2 0_0402_5% GPU_DPC_AUX FOX_3V112M1-RA4A2-7H
[27] mDP_AUX_SCL
3 ME@
OUT

10U_0402_6.3V6M

0.1U_0201_6.3V6K
1
IN
1 1

CV261

CV262
RV333 1 @ 2 0_0402_5% GPU_DPC_AUX# 2
[27] mDP_AUX#_SDA GND @

AP2330W-7_SC59-3 2 2
B B
SA00004ZA00
1

RV334 RV335
100K_0402_5% 100K_0402_5%
2

DV33 DV22 DV44


DISP_CEC 9 10 1 1 DISP_CEC DISP_DAT_AUXN_CONN 9 10 1 1 DISP_DAT_AUXN_CONN mDP_LANE_P1_C 1 1 10 9 mDP_LANE_P1_C

DP_CBL_DET 8 9 2 2 DP_CBL_DET DISP_CLK_AUXP_CONN 8 9 2 2 DISP_CLK_AUXP_CONN mDP_LANE_N1_C 2 2 9 8 mDP_LANE_N1_C

mDP_LANE_P0_C 7 7 4 4 mDP_LANE_P0_C mDP_LANE_N3_C 7 7 4 4 mDP_LANE_N3_C mDP_LANE_N2_C 4 4 7 7 mDP_LANE_N2_C

mDP_LANE_N0_C 6 6 5 5 mDP_LANE_N0_C mDP_LANE_P3_C 6 6 5 5 mDP_LANE_P3_C mDP_LANE_P2_C 5 5 6 6 mDP_LANE_P2_C

3 3 3 3 3 3

8 8 8

YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9


A @ESD@ @ESD@ @ESD@ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
miniDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 44 of 81

5 4 3 2 1
A B C D E

+1.8VS +5VS
ALC3268 +3VS +3VS
+5VDDA_CODEC
+5VS_PVDD1 RA35 1 @ 2 0_0805_5%

0.1U_0201_10V K X5R
2
0_0402_5%

4.7U_0402_6.3V6M
Input

RA31
+1.8VS_CODEC

+5VS_PVDD1

+5VS_PVDD2

4.7U_0402_6.3V6M

0.1U_0201_10V K X5R
2 1 place close audio codec

CA44

CA10
1 1
@ +3VS
EMI

1
1 2

C216

CA52
Combo Jack

2
22P_0402_50V8J @EMI@ CA12 33_0402_5% 2 @EMI@ 1 RA10 2 2

57

19

46

51

45

24
(Normal Open)

7
UA1 RA55
RA14 2.2K_0402_5% 100K_0402_1%

T-PAD

DVDD

DVDD-IO

PVDD1

PVDD2

AVDD1

CPVDD/AVDD2
23 AGND PC_BEEP +MIC1-VREFO_R 1 2

1
1 @ 2 AUDIO_SMDAT0_R 11 PCBEEP CA45 2.2U_0402_6.3V6M +5VS PLUG_IN_R RA36 1 2 200K_0402_1% PLUG_IN
1 [61] AUDIO_SMDAT0 I2C-DATA 1
RA171 0_0402_5% 25 1 2 +MIC1-VREFO_L 1 2
1 @ 2 AUDIO_SMCLK0_R 12 CBN2 +5VS_PVDD2 RA58 1 @ 2 0_0805_5%
[61] AUDIO_SMCLK0 I2C-CLK
RA172 0_0402_5% 26 RA15 2.2K_0402_5%
13 CBP2

4.7U_0402_6.3V6M
CA54 2.2U_0402_6.3V6M SM010016720

0.1U_0201_10V K X5R
[18] HDA_BIT_CLK_R AUDIOLINK:BCLK/BCLK
CBP1
27 1 2
2 1
SM010016720 EMI

CA18

CA9
14 MIC1_SLEEVE EMI@ RA56 2 1 FBMA-L11-160808-121LMT 0603 HGNDB
[18] HDA_SYNC_R AUDIOLINK:SYNC/LRCK 28
W=40mils MIC1_RING2 EMI@ RA21 2 1 FBMA-L11-160808-121LMT 0603 HGNDA
15 CBN1 1 2 W=40mils HP_OUTL EMI@ RA24 1 2 47_0402_5% HPOUT_L
[18] HDA_RST#_R AUDIOLINK:RESETO/MCLK 39 +MIC1-VREFO_R HP_OUTR EMI@ RA37 1 2 47_0402_5% HPOUT_R
2 1 HDA_SDIN0_AUDIO 16 Mic1-VrefO-R/AGPO-1 SD028470A80
[18] HDA_SDIN0 AUDIOLINK:SDATA-IN/DOUT
RA25 33_0402_5% 38 +MIC1-VREFO_L SD028470A80
17 Mic1-VrefO-L/AGPO-0
[18] HDA_SDOUT_R AUDIOLINK:SDATA-OUT/DIN

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
470P_0402_50V7K
SM01000M700 37 MIC1_SLEEVE
RA170 1 EMI@ 2 220_0402_5% DMIC_CLK_R 53 Mic1-R/Sleeve
[42] DMIC_CLK DMIC-CLK1 1 1

2
EMI@ CA42

EMI@ CA49

EMI@ CA41
EMI@ CA51
36 MIC1_RING2
RA169 1 @ 2 0_0402_5% DMIC_DAT_R 54 Mic1-L/Ring2 17@
[42] DMIC_DAT DMIC-DATA1 35 LINE1-L CA76 1 2 1U_0402_6.3V6K SWF_INPR
SWF_INPR [47]

1
Line1-L 2 2
I2S_LRCK_SA 1 34 LINE1-R CA77 1 2 1U_0402_6.3V6K
[46] I2S_LRCK_SA GPIO_9/I2S_LRCK Line1-R
2
I2S_DOUT_SA 3 GPIO_1/DMIC_CLK2/SPDIF_O/I2S_In-JD 33 HP_OUTR 17@ AGND AGND AGND AGND
[46] I2S_DOUT_SA GPIO_6/I2S_Out HP_Out-R
SWF_SDZ# 4
[47] SWF_SDZ# GPIO_2/DMIC-DATA2/I2S_Out-JD
I2S_DIN_SA 5 32 HP_OUTL
[46] I2S_DIN_SA GPIO_5/I2S_In HP_Out-L
8 JHP1 ME@
55 I2S_Out-JD/Mic-JD 40 HGNDB 3
GPIO_8/I2S-MCLK/SPDIF_IN LINE1-VREFO

AGND AGND
I2S_BCLK_SA 56 HPOUT_L 1
[46] I2S_BCLK_SA GPIO_7/I2S-BCLK 41 MIC1_CAP C210 1 2 4.7U_0402_6.3V6M
RA18 2 @ 1 0_0402_5% 52 MIC1-CAP
[47,48] EC_MUTE# EAPD+PD#/GPIO_11 44 LDO1 C208 1 2 4.7U_0402_6.3V6M PLUG_IN 5
1 2 SPK_L2+ RA60 2 17@ 1 0_0201_5% 47 LDO1-CAP

0.1U_0201_10V K X5R
SPK-OUT-LP

4.7U_0402_6.3V6M
@
10K_0402_5%RA17 SPK_L1- RA61 2 17@ 1 0_0201_5% 48 21 6
SPK-OUT-LN VREF1 HPOUT_R 2
1 2

AGND
SPK_R1- RA62 1 17@ 2 0_0603_5% 49 22 LDO2 C209 1 2 4.7U_0402_6.3V6M
SPK-OUT-RN LDO2-CAP

CA23

CA24
HGNDA 4
SPK_R2+ RA63 1 17@ 2 0_0603_5% 50 43 7
SPK-OUT-RP VREF 2 1
2 PLUG_IN_R 9 29 CA55 1 2 1 2 2SJ3095-141111F 2
HP-JD/LINE1-JD CPVPP

4.7U_0402_6.3V6M
DC23000GL00

0.1U_0201_10V K X5R
CA61

CA62
4.7U_0402_6.3V6M 2 1 C199 LDO3 18 30 2.2U_0402_6.3V6M
LDO3_CAP CPVREF AGND
10 31 CA60 1 2 2 1
+3VALW VD33STB CPVEE

+3VS 2 RA57 1 6 42 2.2U_0402_6.3V6M


HD-I2S_SEL/IRQOUT/GPIO0 AVSS1 DA7 DA8
AGND HPOUT_L
100K_0402_1% 20 HGNDB 2 2
AVSS2 AGND 1 1
HGNDA 3 HPOUT_R 3
AGND
PESD5V0U2BT_SOT23-3 S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23 ESD
ESD@ @ESD@
ALC3268-CG_QFN56_7X7 ESD for Audio
SA00009YP00

Change SCA00002900 to SCA00000T00


+5VS for +5VDDA_CODEC
+5VS +5VDDA_CODEC EMI15@
LA9
EMI15@
LA5
RA9 1 @ 2 0_0603_5% place close audio codec
0.1U_0201_10V K X5R

RA48 1 2 47K_0402_5% BEEP_N CA57 2 1 1U_0201_6.3V6M PC_BEEP


4.7U_0402_6.3V6M

2 1 EC Beep [48] BEEP#


CA50

BLM15BD121SN1D_0402
CA75

RA49 1 2 47K_0402_5% BLM15BD121SN1D_0402


APU Beep [18,19] SPKR SM010009U00
1 2 SM010009U00
100P_0402_50V8J
CA56 @ESD@
1 EMI15@ EMI15@
1 LA6 LA12
RA53
27K_0402_5%
2
3 3
2

AGND
Place near Pin45 BLM15BD121SN1D_0402 BLM15BD121SN1D_0402
SM010009U00 SM010009U00
AGND
LA11
LA10
1
1
17@
17@
2
2
1_0402_5%
1_0402_5%

SPEAK 4 ohmG40MIL
LA9 1 17@ 2 1_0402_5% �
SPEAK 8 ohmG20MIL JSPK1
+3VS for +IOVDD_CODEC +3VS for +3VDD_CODEC [46] SPK_L1-
SPK_L1- LA6 1 17@ 2 1_0402_5% SPK_L1-_CONN
SPK_L2+_CONN
1
2 1
2
SPK_L2+ LA5 1 17@ 2 1_0402_5% 3
+3VS +3VS [46] SPK_L2+ G1

1000P_0402_50V7K

1000P_0402_50V7K
LA12 1 17@ 2 1_0402_5% 4
LA13 1 17@ 2 1_0402_5% G2
LA14 1 17@ 2 1_0402_5% 1 1 CVILU_CI4202M2HR0-NH

@EMI@ CA28

@EMI@ CA29
ME@
0.1U_0201_10V K X5R

2 2
1U_0201_6.3V6M
0.1U_0201_10V K X5R

1 1
CA59

1
CA53
CA46

2 2
2

Place near Pin8 Place near Pin1 EMI@


SPK_R1- LA8 1 2 HCB1608KF-121T30_0603
[46] SPK_R1- SPK_R1-_CONN [55]
SPK_R2+ LA7 1 2 S SUPPRE_ KC FBMA-L11-160808-121LMT 0603
[46] SPK_R2+ SPK_R2+_CONN [55]
EMI@

1000P_0402_50V7K

1000P_0402_50V7K
CA78 1 2 0.1U_0402_10V7K

EMI ESD 1 1

@EMI@ CA30

@EMI@ CA31
CA79 1 2 0.1U_0402_10V7K
4 4
RA46 1 @ 2 0_0402_5% SM01000BW00 to SM010016720
SPK_L2+_CONN 2 2

RA51 1 @ 2 0_0402_5% SPK_L1-_CONN

GND AGND
2

RA50 1 @ 2 0_0402_5%
DA3
PESD5V0U2BT_SOT23-3
RA47 1 @ 2 0_0402_5%
@ESD@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
1

GND AGND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3268
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 45 of 81
A B C D E
5 4 3 2 1

TAS5766 Smart Amp for 15" only

+3V_AMP
+3VALW
@
D D
RSA28 1 2 0_0402_5%

QSA1 15@
W=20mils W=20mils

S
3 1

D
PJ2301_SOT23-3 +3V_AMP

G
2
1 15@ 2
[39,48,55,61] S5_PWR_EN#
RSA29 FAULT# 2 15@ 1 10K_0402_5%
150K_0402_5% 1 15@ RSA27
CSA37
0.1U_0201_10V6K
2 +3V_AMP
+3V_AMP
+19VB

The XSMT pin rise time and fall time


need less than 20ns.

46

11

12

13

26

33
1

2
USA1

DVDD

CPVDD

AVCC

PVCC

PVCC

AVDD
XSMP/UVT

FAULTZ
16
RSA14 1 @ 2 0_0402_5% EC_SMB_DA2_SA 35 OUTPL 15@
[18,25,41,48,51] EC_SMB_DA2 SDA 17 DSP_BSPL 1 2
BSPL SPK_L2+ [45]
RSA15 1 @ 2 0_0402_5% EC_SMB_CK2_SA 36 CSA4 0.22U_0603_25V7K
[18,25,41,48,51] EC_SMB_CK2 SCL 18
37 OUTNL 15@
PAD~D TW7 @ GPIO1 DSP_BSNL
19 1 2 SPK_L1- [45]
38 BSNL CSA22 0.22U_0603_25V7K
PAD~D TW6 @ GPIO2 DSP_BSNR
20 1 2 colay with ALC3268's SPK OUT signal
I2S_DIN_SA 40 BSNR CSA23 0.22U_0603_25V7K
[45] I2S_DIN_SA GPIO3
C 21 15@ SPK_R1- [45] C
OUTNR
22 DSP_BSPR 1 2
41 BSPR CSA24 0.22U_0603_25V7K
SCLK 23 15@
From ALC3268 [45] I2S_BCLK_SA
I2S_BCLK_SA 42
BLCK
OUTPR

GVDD
27 GVDD
SPK_R2+ [45]
1 2
I2S_DOUT_SA 43 CSA31 1U_0402_10V6K
[45] I2S_DOUT_SA DIN SA_GAIN
28 1 @ 2 15@
I2S_LRCK_SA 44 GAIN/FSW 15@ RSA2 51K_0402_1%
[45] I2S_LRCK_SA LRCLK 30 INNR 1 2
INNR 15@ CSA32 1U_0201_6.3V6M 1 15@ 2
31 INPR 1 2 RSA1 100K_0402_5%
15@ INPR CSA33 1U_0201_6.3V6M
1 2 CAPM 5 32 DACR
CSA17 1U_0402_25V6K CAPM DACR 15@
CAPP 3 6 VNEG 1 2
CAPP VNEG 15@ CSA35 1U_0201_6.3V6M
Address=0x9C 7 DACL 1 2
DACL CSA34 1U_0201_6.3V6M
ADR2 39 8 INPL
ADR2 INPL 15@
+1.8V_LDO

THERMAL PAD
ADR1 45 9 INNL 1 2
ADR1 INNL CSA36 1U_0201_6.3V6M
47
LDOO
1 Place close to USA1 Pin30, 6, 9

GND

GND

GND

GND

GND

GND

GND

GND

GND
CSA1
1U_0201_6.3V6M
15@ TAS5766MRMTR_VQFN48_7X5

10

14

15

24

25

29

34

48

49
2 15@

www.teknisi-indonesia.com
+3V_AMP +3V_AMP
B B
1

RSA3 RSA18
10K_0402_5% 10K_0402_5%
@ 15@ +3V_AMP +19VB CSA20 & CSA19 close to USA1 Pin26
2

ADR1 ADR2
1 1 1 1 1
1
1

CSA18 CSA21 CSA3 CSA2 CSA7 CSA8


RSA17 RSA19 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0603_25V6M 1U_0402_25V6K 10U_0603_25V6M 10U_0603_25V6M
10K_0402_5% 10K_0402_5% 15@ 15@ @ 15@ 15@ 15@
2

15@ @ 2 2 2 2 2
2

CSA18 close to USA1 Pin1 CSA3 & CSA2 close to USA1 Pin12, 13
CSA21 close to USA1 Pin33

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Smart Amp TAS5766
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 46 of 81
5 4 3 2 1
5 4 3 2 1

+GVDD +GVDD
ALC1304 Subwoofer Amp for 17" only

1
17@
RSWF5 RSWF4 @
Gain/SLV Setting
D 10K_0402_5% 10K_0402_5% D

1U_0201_6.3V6M
2
Gain RSWF4 RSWF8

2
CSWF13
PLIMIT SWF_GAIN
20dB NC 0
+5VS

1
+5VS 1 17@
Master 26dB 75K 15K @ 17@ RSWF8
Mode RSWF9 0_0402_5%
32dB 65K 25K 10K_0402_5%

1000P_0402_50V7K

CSWF7

0.1U_0201_10V K X5R
1 1
15dB 55K 35K

2
0.1U_0402_25V6
1000P_0402_50V7K

10U_0402_6.3V6M

1000P_0402_50V7K

0.1U_0402_25V6

10U_0402_6.3V6M

CSWF8
1 1 1 1 1 1
CSWF4

CSWF2
CSWF3

CSWF5

CSWF1

CSWF6
2 17@ 2
2 2 2@ 2 2 2 17@ 17@ USWF1
17@ @ 17@ 17@
+5VS 12 1 PLIMIT +3VS

SDZ Control
AVCC PLIMIT

13
PVCC GAIN/SLV
3 SWF_GAIN Low Power down 17@
14 SWF_SDZ# RSWF11 2 1 10K_0402_5%
High Normal
27 PVCC
Close Pin13/Pin14 Close Pin27/Pin28 28 PVCC 11
PVCC SYNC
C C

CSWF18 2 @ 1 1U_0201_6.3V6M 6 29 SWF_SDZ#


INPL SDZ SWF_SDZ# [45]
AGND CSWF19 2 @ 1 1U_0201_6.3V6M 5
INNL
30 R632 1 @ 2 0_0402_5%
FAULTZ EC_MUTE# [45,48]
RSWF15 1 17@ 2 2.94K_0402_1% 17@ CSWF9 2 1 1U_0201_6.3V6M 31
[45] SWF_INPR INPR
RSWF12 1 2 1.24K_0402_1% 17@ CSWF10 2 1 1U_0201_6.3V6M 32 JSWF1
INNR
1

AGND 17@ 25 SWF_OUTPR LSWF1 1 @ 2 0_0603_5% SWF_OUTPR_CONN 1


RSWF13 +GVDD OUTPR 23 SWF_OUTNR LSWF2 1 @ 2 0_0603_5% SWF_OUTNR_CONN 2 1
1K_0402_5% 2 OUTNR 2 3
17@ GVDD 16 SWF_OUTPL G1 4
OUTPL 18 SWF_OUTNL G2
2

SWF_OUTPL 17@ CSWF11 1 2 0.22U_0402_6.3V6K 15 OUTNL CVILU_CI4202M2HR0-NH


SWF_OUTNL 17@ CSWF12 1 2 0.22U_0402_6.3V6K 19 BSPL
BSNL ME@
7
Mute Control
AGND MUTE
SWF_OUTPR 17@ CSWF14 1 2 0.22U_0402_6.3V6K 26
Low Normal
SWF_OUTNR 17@ CSWF15 1 2 0.22U_0402_6.3V6K 22 BSPR 4
BSNR GND 1 1
17 CSWF16 CSWF17
High Mute
GND 20 680P_0402_50V7K 680P_0402_50V7K
+GVDD +GVDD AM0 10 GND 21
AM0 GND 2 2

@EMI@

@EMI@
AM1 9 24
8 AM1 GND
PBTL/BTL 33
B B
PGND
1

ALC1304-CG_QFN32_5X5
RSWF2 @ RSWF3 @ 17@
RSWF14 1 @ 2 0_0402_5% 10K_0402_5% 10K_0402_5%
2

AM0 AM1
AGND
AM Avoidance Setting
1

RSWF6 17@ RSWF7 17@ PWM Fsw AM0 AM1


10K_0402_5% 10K_0402_5%
400KHz L L
2

500KHz H L
600KHz L H
1000KHz H H

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Subwoofer ALC1304
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 47 of 81
5 4 3 2 1
+1.05V_VCCST
+3VL
+3VL

2
L20 1@ @
BLM15AX601SN1D_2P R189 1 @ 2 0_0603_5% C179 R588
1 2 100P_0402_50V8J 0_0402_5%
+3VALW_EC +EC_VCCA +3VALW_EC
SM01000KL00 1 1

1
C184 C185 @ 2
1 1 1 1

0.1U_0201_10V K X5R
C180

0.1U_0201_10V K X5R
C181

1000P_0402_50V7K
C182

1000P_0402_50V7K
C183
0.1U_0201_10V K X5R +5VALW
SM01000KL00 1000P_0402_50V7K
1 2 2 ECAGND 2
BLM15AX601SN1D_2P 2 2 @ 2 @ 2 +EC_VCCA +V18R R560 1 @ 2 0_0402_5% USB_EN# R554 1 2 10K_0402_5%
+3VALW_EC
L21 1

C192
4.7U_0402_6.3V6K
ECAGND
VCIN1_BATT_TEMP 1 2

111

117

124
2 C189 100P_0402_50V8J

22
33
96

67
U11

9
VCIN1_AC_IN 1 2
C190 100P_0402_50V8J

VCC_LPC
VCC
VCC
VCC

AVCC
PECI_VTT
VCC0

VCC_IO2
LPC/eSPI & MISC
1 21
[59] PD_IRQ# GA20/GPIO00 PWM0/GPIO0F DCIN_LED_W# [53]
2 23 TBT@
[49] WLAN_PWR_EN# KBRST#/GPIO01 PWM1/GPIO10 DCIN_LED_O# [53] PD_RESET
3 PWM Output 26 R624 2 1 10K_0402_5%
[17] SERIRQ SERIRQ FANPWM0/GPIO12 EC_FAN_PWM2 EC_FAN_PWM1 [53]
4 27
[17] LPC_FRAME# LFRAME#/ESPI_CS# FANPWM1/GPIO13 EC_FAN_PWM2 [53]
5
EMI
@EMI@ @EMI@
[17] LPC_AD3
[17] LPC_AD2
[17] LPC_AD1
7
8
10
LAD3/ESPI_IO3
LAD2/ESPI_IO2
LAD1/ESPI_IO1 AD0/GPIO38
63
64
VCIN1_BATT_TEMP [64,65]
[17] LPC_AD0 LAD0/ESPI_IO0 AD1/GPIO39 DCHG_I [65]
2 1 R190 2 1 10_0402_1% 65
AD2/GPIO3A ADP_I [65]
C186 22P_0402_50V8J 12 AD Input 66
[17] CLK_LPC_EC PCICLK/ESPICLK AD3/GPIO3B CUST_TEMP3 [51] +3VALW_AG
13 75
[16,24,49,50,57] PCI_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 ADP_ID [64]
1 2 37 76
+3VALW_EC R192 @ 47K_0402_5% EC_SCI# 20 ECRST# AD5/GPIO43 CUST_TEMP2 [51]
[19] EC_SCI# PM_CLKRUN#_R SCI#/GPIO0E EC_SMB_CK4 R207 1
1 @ 2 38 2 2.2K_0402_5%
2 [18] PM_CLKRUN#
[55] USB_CHG_CTL1
RC219 0_0402_5% 14 CLKRUN#/GPIO1D
GPIO07/ESPI_RST#
Pin 70 SWTRAP EC_SMB_DA4 R208 1
C187 68 2 2.2K_0402_5%
0.1U_0201_10V K X5R
1 1 DA Output
DA0/GPIO3C
DA1/GPIO3D
70 SWTRAP
NOVO# [55] SWTRAP = Pull-Up: eSPI
ESD@ EC_DBG_KSI0 55 71
C188
[52] EC_DBG_KSI0
56 KSI0/GPIO30
KSI1/GPIO31
DA2/GPIO3E
DA3/GPIO3F
72
DGPU_PWR_EN
USB_EN# [56]
[19,34] SWTRAP = Pull-Down: LPC

1
0.1U_0402_25V6 57
2 58 KSI2/GPIO32 83 R209
KSO[0..15] KSI3/GPIO33 SCL2/GPIO4A INT_AG_EC [61] +3VL
EC_DBG_KSI4 59 84 6.8K_0402_5%
KSO[0..15] [52,61] [52] EC_DBG_KSI4 EC_DBG_KSI5 KSI4/GPIO34 SDA2/GPIO4B EDP_SW [19,41]
60 85
KSI[0..7] [52] EC_DBG_KSI5 EC_DBG_KSI6 KSI5/GPIO35 SCL3/GPIO4C EC_SMB_CK4 [61]
61 86
KSI[0..7] [52,61] [52] EC_DBG_KSI6 EC_SMB_DA4 [61]

2
EC_DBG_KSI7 62 KSI6/GPIO36 SDA3/GPIO4D 87
[52] EC_DBG_KSI7 EC_DBG_KSO0 KSI7/GPIO37 PSCLK3/GPIO4E USB_CHG_ILIM_SEL [55]
39 PS2 Interface 88 NOVO# R625 1 2 100K_0402_5%
[52] EC_DBG_KSO0 EC_DBG_KSO1 KSO0/GPIO20 PSDAT3/GPIO4F CNV_DET# [49]
+3VL 40
[52] EC_DBG_KSO1 EC_DBG_KSO2 KSO1/GPIO21
41
[52] EC_DBG_KSO2 EC_DBG_KSO3 KSO2/GPIO22
R556 42 97
EC_SMB_CK1 [52] EC_DBG_KSO3 KSO3/GPIO23 SHICS#/GPIO60 INV_ENBKL [41]
1 2 43 98
KSO4/GPIO24 SHICLK/GPIO61 SYS_PWROK [18]
2.2K_0402_5% 44 Int. K/B GPIO 99
KSO5/GPIO25 SHIDO/GPIO62 ME_EN [19]
R557 45 Matrix 109 +3VALW
EC_SMB_DA1 KSO6/GPIO26 VCIN0/GPIO78 VCIN0_PH1 [64]
1 2 46
2.2K_0402_5% 47 KSO7/GPIO27
EC_SMB_CK1 EC_SMB_DA1 48 KSO8/GPIO28 119
KSO9/GPIO29 MISO_SHR_ROM/GPIO5B EC_SPI_MISO [16]
1000P_0402_50V7K

49 120
KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C EC_SPI_MOSI [16]
1000P_0402_50V7K

50 SPI ROM 126 LID_SW# R626 1 2 100K_0402_5%


KSO11/GPIO2B SPICLK_SHR_ROM/GPIO58 EC_SPI_CLK [16]
1

51 128
KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A EC_SPI_CS0# [16]
1

C126 @ 52 EC_MUTE# R555 1 2 10K_0402_5%


C127 @ 53 KSO13/GPIO2D
2

54 KSO14/GPIO2E 73
CUST_TEMP1 [51]
2

KB_MUTLI_KEY 81 KSO15/GPIO2F AD6/GPIO40 74 VCCST_PWRGD


[52,61] KB_MUTLI_KEY
[25,65] GPU_PROHOT
GPU_PROHOT 82 KSO16/GPIO48
KSO17/GPIO49
AD7/GPIO41
LOCK#/GPIO50
89
EC_MUTE# [45,47]
VCCST_PWRGD [10]
ESD

100P_0402_50V8J
C124 @ESD@
90 1
GPIO52 S5_PWR_EN# [39,46,55,61]
91
EC_SMB_CK1 CAPSLED#/GPIO53 S3_LED# EN_5VALW [66]
77 GPIO 92 SYSON
[59,64,65] EC_SMB_CK1 EC_SMB_DA1 SCL0/GPIO44 WDT_LED/GPIO54 S3_LED# [42,62]
78 93
[59,64,65] EC_SMB_DA1 SDA0/GPIO45 SCROLED#/GPIO55 LAN_PWR_EN [50] 2

C193
EC_SMB_CK2

0.1U_0201_10V K X5R
+3VALW_AG 79 95 SYSON
[18,25,41,46,51] EC_SMB_CK2 EC_SMB_DA2 SCL1_BT/GPIO46 GPIO56 SYSON [63,67]
80 121 ESD@
[18,25,41,46,51] EC_SMB_DA2 SDA1_BT/GPIO47 GPIO57/XCLK32K VR_ON [70]
15 SMBUS 127 1
[18] EC_CLEAR_CMOS# SCL4/GPIO08 GPIO59/DPWROK AC_PRESENT [18]
17@ 19
KB_MUTLI_KEY [55] USB_CHG_STATUS# SDA4/GPIO0D
R210 1 2 20K_0402_1% 17
[55] USB_CHG_EN SCL5/GPIO0B
18 100
[55] USB_CHG_CTL2 SDA5/GPIO0C FANFB2/RSMRST# EC_RSMRST# [18] 2
101
FANFB3/GPIO64 PG_3V/5VALW [55,63,66,69]
+3VALW 102
VCIN1/GPIO65 103
GPIO VCOUT1/GPIO66 VCOUT1_PROCHOT# [65]
104 1
VCOUT0/GPIO67 VCOUT0_MAIN_PWR_ON [66]
6 105 BKOFF# C2174
PBTN_OUT# [18,68] PM_SLP_S3# GPIO04 GPIO68 BKOFF# [42]
R395 1 @ 2 10K_0402_5% 16 106 100P_0402_50V8J
[55] USB_CHG_CTL3 KBL_ICON_PWM OWM/GPIO0A GPIO69 PD_RESET [59]
25 107 ESD@
[52] KBL_ICON_PWM PWM2/GPIO11 GPIO6A EC_PCIE_WAKE# TP_DISABLE# [52] 2
28 108
[53] EC_FAN_SPEED1
29 FANFB0/GPIO14 GWG/GPIO6B EC_PCIE_WAKE# [50,57] Near U11 R391
[53] EC_FAN_SPEED2 EC_TX FANFB1/GPIO15
30 GPIO SUSP# 1 @ 2
[49] EC_TX EC_RX TXD/GPIO16 VCIN1_AC_IN
31 110
[49] EC_RX PCH_PWROK RXD/GPIO17 AC_IN/GPIO79 EC_ON VCIN1_AC_IN [65]
32 112 100K_0402_5%
[18] PCH_PWROK POWER_FAIL1/GPIO18 GPIO7A/ALW_PWR_EN EC_ON [66]
GPIO19 34 114 ON/OFF# [53]
PWM3/GPIO19 GPIO7B/ON/OFFBTN#
100P_0402_50V8J
C125 @ESD@

1 36 GPIO 115
[70] VR_PWRGD NUMLED#/GPIO1A GPIO7C/LID_IN LID_SW# [52]
116 SUSP#
GPIO7D SUSP# [57,63,67,68]
C123 ESD@
100P_0402_50V8J

1
118 PECI 1 2
2 PBTN_OUT# PECI H_PECI [10,17]
122 R559 43_0402_1%
[18] PBTN_OUT# PM_SLP_S4# XCLKI/GPIO5D +3VALW_EC
123
2 [18,65,67] PM_SLP_S4# GPIO5E
+3VALW
125 GPIO7E R589 1 9022@ 2 0_0402_5%
GPIO7E
AGND
GND
GND
GND
GND
GND

VCOUT1_PROCHOT# R561 1 @ 2 0_0402_5%


11
24
35
94

69
113

R563 KB9542Q-B_LQFP128_14X14 R562 1 @ 2 0_0402_5% H_PROCHOT# [10]


EC_PCIE_WAKE# [70] VR_HOT#
1 2
ECAGND

1K_0402_5%
ESD 1
ESD@
1
@ESD@ C191
C197 47P_0402_50V8J
0.1U_0201_10V K X5R 2
2

R642 1 @ 2 0_0201_5% GPIO19


[25] THERM_ALERT#_EC_R

R643 1 @ 2 0_0201_5%
[45] BEEP#

+3VS

R389 1 2 GPU_PROHOT
10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB9542Q
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 48 of 81
A B C D E

NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi] Jefferson Peak:1360mA@peak current


Close to KEY E pin2,4
+3V_WLAN

Thunder_Peak_2:1100mA@peak current
For Power consumption Measurement 1
CW1 @
1
CW2 @
1
CW3 @

+3VALW 422.18mA
KEY E 422.18mA
+3V_WLAN 2
4.7U_0402_6.3V6K
2
0.1U_0201_10V6K
2
0.01U_0402_16V7K

+3V_WLAN JWLAN1
1 2
GND 3.3VAUX RW4 CNVI@
@ USB2 P14 3 4 1 2
0_0603_5% [14] USB20_P14 USB_D+ / RSVD 3.3VAUX
RW40 1 2 5 6 @ TW1 PAD~D 75K_0402_1%
(For Bluetooth) [14] USB20_N14 USB_D- / RSVD LED1#
7 8
QW10 CNVI@ CNV_PRX_DTX_N1 9 GND PCM_CLK / RSVD 10 CNV_RF_RESET#_R RW6 1 @ 2 0_0201_5%
[15] CNV_PRX_DTX_N1 SIDO_CLK / WGR_D1N PCM_SYNC / LCP_RSTN CNV_RF_RESET# [18]
CNV_PRX_DTX_P1 11 12
W=20mils W=20mils [15] CNV_PRX_DTX_P1
CNV_DET# SDIO_CMD / WGRD1P PCM_IN / RSVD CLKREQ_CNV#_R
1.8V

S
3 1 13 14 RW8 1 @ 2 0_0201_5%

D
[48] CNV_DET# SDO_DAT0 / RSVD PCM_OUT / CLKREQ0 CLKREQ_CNV# [18]
CNV_PRX_DTX_N0 15 16
[15] CNV_PRX_DTX_N0 SDO_DAT1 / WGR_D0N LED2# @ TW2 PAD~D
CNVi Rx CNV_PRX_DTX_P0 17 18
[15] CNV_PRX_DTX_P0 SDO_DAT2 / WGR_D0P GND
PJ2301_SOT23-3 19 20 RW12 1 CNVI@ 2 0_0402_5%

G
1 1 CNV_BRI_PRX_DTX [15]

2
CLK_CNV_PRX_DTX_N 21 SDO_DAT3 / RSVD UART_WAKE# / RSVD 22 CNV_BRI_PRX_R_DTX
[15] CLK_CNV_PRX_DTX_N SDIO_WAKE# / WGR_CLKN UART_RX / BRI_RSP 1.8V
CW10 @ CW11 @ CLK_CNV_PRX_DTX_P 23 RW35 1 2 0_0402_5%
1 CNVI@ [15] CLK_CNV_PRX_DTX_P SDIO_RESET# / WGR_CLKP UART_2_PRXD_DTXD [19] 1
1 2 0.1U_0201_10V6K 10U_0402_6.3V6M DBG@
[48] WLAN_PWR_EN# 2 2 RW36 1 DBG@ 2 0_0402_5%
RW41 UART_2_PTXD_DRXD [19]
150K_0402_5% 1
CW9 32 CNV_RGI_PTX_R_DRX RW16 1 CNVI@ 2 0_0402_5% 1.8V
UART_TX / RGI_DT CNV_RGI_PRX_R_DTX CNV_RGI_PTX_DRX [15]
0.1U_0201_10V6K 33 34 RW17 1 @ 2 0_0201_5%
PCIE_PTX_C_DRX_P14 GND UART_CTS / RGI_RSP CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX [15]
CNVI@ CW4 1 2 0.1U_0402_10V7K 35 36 RW19 1 @ 2 0_0201_5% CNV_BRI_PTX_DRX [15]
2 [17] PCIE_PTX_DRX_P14 PCIE_PTX_C_DRX_N14 PETP0 / RSVD UART_RTS / BRI_DT
CW5 1 2 0.1U_0402_10V7K 37 38 RW20 1 @ 2 0_0402_5% EC_TX EC_TX [48]
[17] PCIE_PTX_DRX_N14 PETN0 / RSVD RSVD
PCIe X1 39 40 RW22 1 @ 2 0_0402_5% EC_RX EC_RX [48]
PCIE_PRX_DTX_P14 41 GND RSVD 42
[17] PCIE_PRX_DTX_P14 PERP0 / RSVD RSVD
(link to PICe Port 14) PCIE_PRX_DTX_N14 43 44
[17] PCIE_PRX_DTX_N14 PERN0 / RSVD COEX3 / RSVD @ TW3 PAD~D
The connectivity module power supply pin shall be 45 46
GND COEX2 / RSVD @ TW4 PAD~D
connected directly to thr rail DSW. 47 48
[15] CLK_PCIE_P3 REFCLKP0 / RSVD COEX1 / RSVD @ TW5 PAD~D
From PCIe CLK 49 50 RW25 1 @ 2 0_0402_5% SUSCLK
[15] CLK_PCIE_N3 REFCLKN0 / RSVD SUSCLK WL_RST#_R SUSCLK [18]
567240_Intel_Wireless_AC_9560_Jefferson_Peak_EPS_Rev1.1 51 52 RW26 1 @ 2 0_0402_5% PCI_RST# [16,24,48,50,57]
(From PCH CLKOUT3) 53 GND PERST0# / RSVD 54 BT_ON_R RW37 1 @ 2 0_0402_5%
+3VALW [15] WLAN_CLKREQ3# CLKEQ0# / RSVD W_DISABLE2# BT_ON [19]
EC_WL_WAKE# 55 56 EC_WL_OFF#_R RW38 1 @ 2 0_0402_5%
PEWAKE0# / RSVD W_DISABLE1# EC_WL_OFF# [19]
57 58
CNV_PTX_DRX_N1 59 GND I2C_DATA 60
[15] CNV_PTX_DRX_N1 RSVD / WT_D1N I2C_CLK
10K_0402_5% 2 1 RW42 CNV_DET# CNV_PTX_DRX_P1 61 62
[15] CNV_PTX_DRX_P1 RSVD / WT_D1P ALERT / I2C_IRQ# REFCLK_CNV_R
63 64 RW29 1 @ 2 0_0201_5% REFCLK_CNV [15]
CNV_PTX_DRX_N0 65 GND RSVD / REFCLK0 66
+3V_WLAN [15] CNV_PTX_DRX_N0
CNVi Tx CNV_PTX_DRX_P0 67 RSVD / WT_D0N RSVD 68 422.18mA For CNVi Feature
[15] CNV_PTX_DRX_P0 RSVD / WT_D0P RSVD
69 70 +3V_WLAN
CLK_CNV_PTX_DRX_N 71 GND RSVD 72
[15] CLK_CNV_PTX_DRX_N RSVD / WT_CLKN 3.3VAUX
10K_0402_5% 2 @ 1 RW18 EC_WL_OFF#_R CLK_CNV_PTX_DRX_P 73 74 +3V_WLAN
[15] CLK_CNV_PTX_DRX_P RSVD / WT_CLKP 3.3VAUX
75
10K_0402_5% 2 @ 1 RW21 BT_ON_R GND

10K_0402_5% 2 1 RW23 EC_WL_WAKE# +3VALW 77 76


MTG77 MTG76 1 1 1
Need to stuff for CNVi power sequence control Imax : 2.0 A +3V_WLAN CW6 CW7 CW8
71.5K_0402_1%2 @ 1 RW39 CLKREQ_CNV# 4.7U_0402_6.3V6K 0.1U_0201_10V6K 0.01U_0402_16V7K
Imax : 2.0 A LOTES_APCI0128-P005A
2 2 2
ME@

1U_0201_6.3V6M
100K_0402_5% 2 1 RW24 EC_TX 1
+3VS_WLAN
1

CW3861 @
CW3863
@ 0.1U_0201_10V6K Close to KEY E pin72,74
UC13
2

1 2
5 VOUT
VIN
Follow 566468_CNL_UY_PDG_Rev0p73.pdf
@ 2
WLAN_PWR_EN# 1 2 WLAN_PWR_EN#_R 4 GND
RW3937 0_0402_5% EN
1U_0201_6.3V6M

3 RW3943 1 @ 2 10K_0402_5%
/OC
1

CW3864 @

EM5203AJ-20 SOT23-5
@
2

I (Max) : 2.0 A(+3VS_WLAN)


2 RDS(Typ) : 70 mohm 2
V drop : 0.14 V
+3VS_SSD
Note : footprint not update, Please use low active load swtich
footprint(SA00009XD00)
KEY M for 15" only SSD +3VS_SSD
1 CS2 1 1 CS3
JSSD1 CS4

4.7U_0402_6.3V6K

0.01U_0402_16V7K
1 2 15@ 15@ 15@

0.1U_0201_10V6K
3 GND 3P3VAUX 4 +3VS_SSD
5 GND 3P3VAUX 6 2 2 2
[14] PCIE_PRX_DTX_N24 PERn3 NC
7 8
[14] PCIE_PRX_DTX_P24 PERp3 NC
9 10 TP@ TS1
PCIE_PTX_DRX_N24 CS5 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_N24 11 GND DAS/DSS# 12
[14] PCIE_PTX_DRX_N24 PCIE_PTX_DRX_P24 PETn3 3P3VAUX
CS6 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_P24 13 14
[14] PCIE_PTX_DRX_P24 PETp3 3P3VAUX
15 16
17 GND 3P3VAUX 18
[14] PCIE_PRX_DTX_N23 PERn2 3P3VAUX Close to JSSD1 KEY M pin2,4
19 20
[14] PCIE_PRX_DTX_P23 PERp2 NC
21 22
PCIE_PTX_DRX_N23 CS7 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_N23 23 GND NC 24
NGFF SSD1 (KEY M) PCIE X4
[14] PCIE_PTX_DRX_N23
[14] PCIE_PTX_DRX_P23
PCIE_PTX_DRX_P23 CS8 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_P23 25
27
PETn2
PETp2
NC
NC
26
28
29 GND NC 30
(link to PICE Port 17~20) [14] PCIE_PRX_DTX_N22
31 PERn1 NC 32
[14] PCIE_PRX_DTX_P22 PERp1 NC
33 34
PCIE_PTX_DRX_N22 CS9 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_N22 35 GND NC 36
+3VS +3VS_SSD [14] PCIE_PTX_DRX_N22 PCIE_PTX_DRX_P22 PETn1 NC
CS10 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_P22 37 38 DEVSLP4_SSD RS8 1 @ 2 0_0402_5%
[14] PCIE_PTX_DRX_P22 PETp1 DEVSLP DEVSLP4 [17]
39 40
41 GND NC 42
[14] PCIE_PRX_DTX_P21 PERn0/SATA-B+ NC
RS2 1 @ 2 0_0603_5% 43 44
[14] PCIE_PRX_DTX_N21 PERp0/SATA-B- NC
45 46
PCIE_PTX_DRX_N21 CS11 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_N21 47 GND NC 48
[14] PCIE_PTX_DRX_N21 PETn0/SATA-A- NC
For Power consumption [14] PCIE_PTX_DRX_P21
PCIE_PTX_DRX_P21 CS12 15@ 1 2 0.22U_0201_6.3V PCIE_PTX_C_DRX_P21 49
PETp0/SATA-A+ PERST#
50 PCI_RST#
Measurement 51 52 SSD_CLKREQ1# [15]
53 GND CLKREQ# 54
[15] CLK_PCIE_N1 REFCLKN PEWake# TP@ TS2
PCIE CLK [15] CLK_PCIE_P1
55
REFCLKP NC
56
(From PCH CLKOUT1) 57 58
GND NC
+3VS
+3VS_SSD

67 68 SUSCLK
NC SUSCLK(32kHz)
1

SATAPCIE_4 69 70
RS12 71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 72
10K_0402_5% @ 73 GND 3P3VAUX 74
75 GND 3P3VAUX
3 GND 76
3
2

GND1 77
GND2
[17] SATAPCIE_4 LOTES_APCI0079-P005A

PEDET Module Type 1129 symbol changed

0 SATA
1 PCIE
for 17" SSD +3VS_SSD
+3VS_SSD

JSSD2
1 2
3 GND 3P3VAUX 4 +3VS_SSD
PCIE_PRX_DTX_N24 RHD19 2 17@ 1 0_0201_5% PCIE_PRX_DTX_N24_R 5 GND 3P3VAUX 6
PCIE_PRX_DTX_P24 RHD20 2 17@ 1 0_0201_5% PCIE_PRX_DTX_P24_R 7 PERn3 NC 8
9 PERp3 NC 10 CS23 CS22 CS211
GND DAS/DSS# TP@ TS3 1 1
PCIE_PTX_DRX_N2417@ CS13 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_N24 11 12
PCIE_PTX_DRX_P2417@ CS14 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_P24 13 PETn3 3P3VAUX 14 17@ 17@ 17@
PETp3 3P3VAUX

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
15 16
PCIE_PRX_DTX_N23 RHD23 2 17@ 1 0_0201_5% PCIE_PRX_DTX_N23_R 17 GND 3P3VAUX 18 2 2 2
PCIE_PRX_DTX_P23 RHD24 2 17@ 1 0_0201_5% PCIE_PRX_DTX_P23_R 19 PERn2 3P3VAUX 20
21 PERp2 NC 22
PCIE_PTX_DRX_N2317@ CS15 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_N23 23 GND NC 24
PCIE_PTX_DRX_P2317@ CS16 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_P23 25 PETn2 NC 26
27 PETp2 NC 28
PCIE_PRX_DTX_N22 RHD27 2 17@ 1 0_0201_5% PCIE_PRX_DTX_N22_R 29 GND NC 30
PCIE_PRX_DTX_P22 RHD28 2 17@ 1 0_0201_5% PCIE_PRX_DTX_P22_R 31 PERn1 NC 32
33 PERp1 NC 34
PCIE_PTX_DRX_N2217@ CS17 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_N22 35 GND NC 36
PCIE_PTX_DRX_P2217@ CS18 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_P22 37 PETn1 NC 38 DEVSLP4_SSD
39 PETp1 DEVSLP 40
PCIE_PRX_DTX_P21 RHD31 2 17@ 1 0_0201_5% PCIE_PRX_DTX_P21_R 41 GND NC 42 Close to JSSD2 KEY M pin2,4
PCIE_PRX_DTX_N21 RHD32 2 17@ 1 0_0201_5% PCIE_PRX_DTX_N21_R 43 PERn0/SATA-B+ NC 44
45 PERp0/SATA-B- NC 46
PCIE_PTX_DRX_N2117@ CS19 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_N21 47 GND NC 48
PCIE_PTX_DRX_P2117@ CS20 1 2 0.22U_0201_6.3V PCIE_PTX_17C_DRX_P21 49 PETn0/SATA-A- NC 50 PCI_RST#
4 51 PETp0/SATA-A+ PERST# 52 SSD_CLKREQ1# 4
CLK_PCIE_N1 RHD35 2 17@ 1 0_0201_5% CLK_PCIE_N1_R 53 GND CLKREQ# 54
REFCLKN PEWake# TP@ TS4
CLK_PCIE_P1 RHD36 2 17@ 1 0_0201_5% CLK_PCIE_P1_R 55 56
57 REFCLKP NC 58
GND NC

+3VS_SSD

67 68 SUSCLK
SATAPCIE_4 69 NC SUSCLK(32kHz) 70
71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 72
73 GND 3P3VAUX 74
75 GND 3P3VAUX
GND 76
GND1 77
GND2
LOTES_APCI0079-P005A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN(KEY E)/SSD(KEY M)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 49 of 81
A B C D E
5 4 3 2 1

RJ-45 CONN.
RL11 1 @ 2 0_0603_5% JLAN1
RJ45_TX3- 8
PR4- 10
+LAN_VDD RJ45_TX3+ 7 GND 9
LL1 PR4+ GND
+LAN_SROUT1.05 RJ45_RX1-

0.1U_0201_10V7K
1 2 6
2.2UH +-5% NLC252018T-2R2J-N PR2-
RJ45_TX2-

0.1U_0201_10V7K
8111H_SW@ 5

4.7U_0402_6.3V6K
1 PR3-
1 1
CL15 CL16 CL17 RJ45_TX2+ 4
+3VALW +3V_LAN 8111H_LDO@ PR3+
D 2 D

8111H_SW@

8111H_SW@
RJ45_RX1+ 3
2 2 PR2+ LANGAN1 LANGAN
W=40mils RL18 1 @ 2 0_0603_5%
W=40mils RJ45_TX0- 2
PR1-
1U_0201_6.3V6M

2 RJ45_TX0+ 1
+3V_LAN rising time (10%~90%) need >0.5mS and <100mS PR1+
CL1

SANTA_130452-S
1 LL1, CL16, and CL17 close to Pin24 ME@
( Should be place within 200 mils )

+LAN_VDD +3VS

0.1U_0201_10V7K
0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K

1
1U_0201_6.3V6M
1 1 1 1 1 RL8
1K_0402_5%
CL4 CL5 CL6 CL7 CL8

2
2 2 2 2 2 ISOLATE#

RL10
15K_0402_5%
Pin3 Pin8 Pin22 Pin30 Pin22

+LAN_VDD

C C
UL1
For surge CL23, CL22 close to UL1 Pin17,18
+3V_LAN LAN_MDIP0 1 17 PCIE_PRX_C_DTX_P13 .1U_0402_16V7K 2 1 CL23
LAN_MDIN0 MDIP0 HSOP PCIE_PRX_C_DTX_N13 PCIE_PRX_DTX_P13 [17]
2 18 .1U_0402_16V7K 2 1 CL22
MDIN0 HSON PCIE_PRX_DTX_N13 [17]
3 19 PCI_RST# [16,24,48,49,57]
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE#
4.7U_0402_6.3V6K

4.7U_0402_6.3V6K

LAN_MDIN1 MDIP1 ISOLATEB


0.1U_0201_10V7K
0.1U_0201_10V7K

1 1 1 1 5 21
@ @ LAN_MDIP2 6 MDIN1 LANWAKEB 22 EC_PCIE_WAKE# [48,57]
CL2 CL3 CL20 CL21 LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG +3V_LAN
8 MDIN2 VDDREG 24 +LAN_SROUT1.05
2 2 2 2 +3V_LAN LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 @
LAN_MDIN3 10 MDIP3 LED2 26 TPL2 RL17 1 2 10K_0402_5%
11 MDIN3 LED1/GPO 27 LED0
12 AVDD33 LED0 28 XTLO TPL1
[15] LAN_CLKREQ2#
13 CLKREQB CKXTAL1 29 XTLI +3V_LAN Reserved GPIO pin
[17] PCIE_PTX_C_DRX_P13 14 HSIP CKXTAL2 30 RL40 1 @ 2
[17] PCIE_PTX_C_DRX_N13 HSIN AVDD10 LAN_PWR_EN [48]
15 31 1 RL9 2 0_0402_5%
[15] CLK_PCIE_P2 16 REFCLK_P RSET 32 2.49K_0402_1%
[15] CLK_PCIE_N2 REFCLK_N AVDD33 33
GND
CL2 close to Pin 11
CL3 close to Pin 32
RTL8111H-CG_QFN32_4X4

RTL8111H SA000080P00 LDO regulator XTLO RL20 1 @ 2 0_0402_5%

+3V_LAN
1 @ 2+LAN_VDDREG
EMI RTL8111HS SA000082V00 Switching regulator YL1
25MHZ_20PF_XRCGB25M000F2P18R0 SJ10000TO00
0.1U_0201_10V7K

RL1 0_0603_5% RL4 1 @ 2 0_0402_5%


4.7U_0402_6.3V6K

1 1 XTLI 3 1
CL9 CL10 RL5 1 @ 2 0_0402_5% 3 1
TXC SJ10000TO00 NC NC
2 2
8111H_SW@

2 2 Murata SJ10000UH00 CL14 4 2 CL13


LANGAN 27P_0402_50V8J 27P_0402_50V8J
1 1

B B
RL6 1 @ 2 0_0402_5%

Close to Pin23 RL7 1 @ 2 0_0402_5%

LANGAN1

+V_DAC 1
TL1
24
RL19
75_0402_5%
1 2
EMI CL19
1 2
TCT1 MCT1 EMI@
EMI LAN_MDIP3

LAN_MDIN3
2

3
TD1+ MX1+
23

22
RJ45_TX3+

RJ45_TX3- RL21
10P_0603_50V
EMI@

CL18 TD1- MX1- 75_0402_5% LANGAN


1 2 +V_DAC 4 21 1 2
TCT2 MCT2 EMI@
0.01U_0402_16V7K LAN_MDIP2 5 20 RJ45_TX2+
EMI@ TD2 MX2+
SC300003V00
LAN_MDIN2 6 19 RJ45_TX2- RL22
L30ESDL5V0C6-4_SOT23-6 TD2- MX2-
DL2 @ESD@ 75_0402_5%
LAN_MDIN0 4 3 LAN_MDIP1 LAN_MDIN2 6 1 LAN_MDIP3 +V_DAC 7 18 1 2
4 3 6 1 TCT3 MCT3 EMI@
LAN_MDIP1 8 17 RJ45_RX1+
TD3+ MX3+
LAN_MDIN1 9 16 RJ45_RX1- RL23
TD3- MX3- 75_0402_5%
+V_DAC 10 15 1 2
TCT4 MCT4 EMI@
LAN_MDIP0 11 14 RJ45_TX0+
5 2 5 2 TD4+ MX4+
Vbus GND Vbus GND LAN_MDIN0 12 13 RJ45_TX0-
TD4- MX4-

350UH_IH-160

A A

LAN_MDIP0 6 1 LAN_MDIN1 LAN_MDIP2 4 3 LAN_MDIN3


6 1 4 3
DL1 @ESD@
L30ESDL5V0C6-4_SOT23-6
SC300003V00

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8111H/RTL8107E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 50 of 81
5 4 3 2 1
1 2 3 4 5

THERMAL SENSOR For Smart Performance

A +3VS_THM A
+3VS +3VS_THM

RTH3 1 @ 2 0_0402_5% 1
CTH1
0.1U_0201_10V6K
2 TOP DDR
BOTTOM VCORE REMOTE1+ Close UTH1 UTH1
+3VS_THM

LMBT3904WT1G_SC70-3 1

1
QTH1 C CTH3 1 10 EC_SMB_CK2
VCC SCL EC_SMB_CK2 [18,25,41,46,48]
2 2200P_0402_25V7K CTH4
RTH2
B @ 2200P_0402_25V7K REMOTE1+ 2 9 EC_SMB_DA2 @
EC_SMB_DA2 [18,25,41,46,48] 10K_0402_5%

2
E 2 DP1 SDA

3
3 8

2
REMOTE1- REMOTE1- DN1 ALERT#
4 7 THM_ALERT#
BOTTOM GPU REMOTE2+ REMOTE2+ DP2 THERM#
5 6
LMBT3904WT1G_SC70-3 DN2 GND
1

QTH2 C 1 REMOTE2-
B B

1
2 CTH5 F75303M_MSOP10
B 2200P_0402_25V7K CT114
E @ 2200P_0402_25V7K SA000046C00
3

2
2
REMOTE2- Address 1001_101xb

REMOTE1,2 (+/-) : teknisi-indonesia.com


Trace width/space:10/10 mil
Trace length:<8"
GPU Fan CPU Fan SSD
+EC_VCCA +EC_VCCA +EC_VCCA
1

1
C RTS336 RTS334 RTS341 C
16.5K_0402_1% 16.5K_0402_1% 16.5K_0402_1%
2

2
[48] CUST_TEMP1 [48] CUST_TEMP2 [48] CUST_TEMP3

1
1

1
RTS338 RTS335 RTS339

100K_0402_1%_NTCG104EF104FT1X 100K_0402_1%_NTCG104EF104FT1X 100K_0402_1%_NTCG104EF104FT1X

2
2

D D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
Thermal Sensor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 51 of 81
1 2 3 4 5
1 2 3 4 5

Lid Switch Touch Pad JKB1


Keyboard KSO7 1
1
KSO0 2
KSI1 3 2
KSI[0..7] KSI7 4 3
PU @ Module side [61] KSI[0..7] 4
KSO9 5
KSO[0..15] KSI6 6 5
+3VS +3VS +3VS +3VS [61] KSO[0..15] 6
KSI5 7
KSO3 8 7
+3VALW KSI4 9 8
KSI2 10 9
10

1
1 KSO1 11
@ R505 KSI3 12 11
15@ C438 @ R211 @ R212 KSI0 13 12
U1 4.7K_0402_5% 13
0.1U_0402_10V6K 10K_0402_5% 10K_0402_5% KSO13 14
D APX8132AI-TRG_SOT23-3 2 14 D
C362 KSO5 15

2
JTP1 KSO2 16 15
2
0.47U_0402_6.3V6K

2 3 14 12 KSO4 17 16

GND
VDD VOUT LID_SW# [48] GND 12 17
15@ 13 11 I2C_1_SCL [19] KSO8 18
GND 11 10 KSO6 19 18
1 1 10 I2C_1_SDA [19] To PCH 19
C363 9 KSO11 20
1

10P_0402_50V8J 9 8 TP_L KSO10 21 20


@ 8 7 TP_R KSO12 22 21
2 7 6 TP_INT# KSO14 23 22
6 TP_INT# [16] 23
5 TP_DISABLE# +3VS KSO15 24
5 TP_L TP_DISABLE# [48] 24
4 R487 1 @ 2 0_0402_5% 25
4 3 TP_R R631 1 2 100_0402_5% 26 25
3 [61] KB_ESC_LED# 26
2 R627 1 17@ 2 100_0402_5% 27 33
2 [61] KB_F1_LED# 27 GND

220P_0402_50V7K

220P_0402_50V7K
1 R628 1 17@ 2 100_0402_5% 28 34
1 [61] KB_F4_LED# 28 GND
+3VALW R629 1 17@ 2 100_0402_5% 29
[61] KB_CAP_LED# 29

2
@ C439

@ C440
ACES_51522-01201-001 R630 1 17@ 2 100_0402_5% 30
[61] KB_NUM_LED# 30
ME@ 31
[48,61] KB_MUTLI_KEY 31
32
I2C_1_SDA TP_INT#

1
17@ 32
U123 I2C_1_SCL TP_DISABLE#
C279 APX8132AI-TRG_SOT23-3 JXT_FP257H-032S10M
2 ME@
0.47U_0402_6.3V6K

2
3

2
2 3 LID_SW#
GND

17@ VDD VOUT D29 D37

2
1 AZC199-02SPR7G_SOT23-3 PESD5V0U2BT_SOT23-3
1 C278 @ESD@
1

1
10P_0402_50V8J ESD@
@

1
1
2

C C

Bom Structure Icon LED


VRAM 8G 15" KB LED
+5VALW_ICON +5VALW_ICON
ZZZ M8G@ ZZZ S8G@ ZZZ H8G@ LED1 LED4
R6 1 2 2 1 R568 1 2 2 1
220_0402_5% miniDP 100_0402_5% LAN
VRAM VRAM VRAM 19-113-T1D-CP2Q2HY-3T_WHITE 19-113-T1D-CP2Q2HY-3T_WHITE

LED2 LED5
MT61K256M32JE-14:A K4Z80325BC-HC14 H56C8H24MJR-S2C R566 1 2 2 1 R569 1 2 2 1
100_0402_5% HDMMI 100_0402_5% USB2
19-113-T1D-CP2Q2HY-3T_WHITE 19-113-T1D-CP2Q2HY-3T_WHITE
X7678038L51 X7678038L52 X7678038L53
LED3
R567 1 2 2 1
100_0402_5% USB1
19-113-T1D-CP2Q2HY-3T_WHITE
ZZZ M6G@ ZZZ S6G@ ZZZ H6G@

VRAM VRAM VRAM

MT61K256M32JE-14:A K4Z80325BC-HC14 H56C8H24MJR-S2C +5VALW +5VALW_ICON

QKBL1
X7678038L56 X7678038L57 X7678038L58 +VL PJ2301_SOT23-3

S
3 1

D
1

B Coffee Lake-H CPU SKU Refresh RKBL2 B

G
2

0.1U_0201_10V K X5R
10K_0402_5%

10U_0402_6.3V6M
CPU1@ CPU5@ CPU3@ 1 2
17" KB LED
2

CKBL2

CKBL3
UC1 UC1 UC1 RKBL1
[48] KBL_ICON_PWM 1 2

49.9K_0402_1% 2@ 1@
MP-R1 MP-R3 ES-8+2 1
CKBL1
CFL-H_i5-8300H CFL-H_i5-8300H CFL-R 8C 2.1G ES 0.01U_0402_16V7K
2
SA0000BPJ20 SA0000BPJ60 SA0000CDU00

CPU4@
UC1
CPU2@ CPU6@
UC1 UC1
ME@
ES-6+2
MP-R1 MP-R3 JDBG1
12
11 GND2
CFL-R 6C 2.4G ES GND1
CFL-H_i7-8750H CFL-H_i7-8750H SA0000CDV00
SA0000BPZ20 SA0000BPZ60 Nvidia GPU SKU [48] EC_DBG_KSI0
EC_DBG_KSI0
EC_DBG_KSI4
10
9 10
[48] EC_DBG_KSI4 EC_DBG_KSI5 9
8
[48] EC_DBG_KSI5 EC_DBG_KSI6 8
UV1 GPU1@ UV1 GPU2@ UV1 GPU3@ UV1 GPU4@ UV1 GPU5@ UV1 GPU6@ 7
[48] EC_DBG_KSI6 EC_DBG_KSI7 7
6
[48] EC_DBG_KSI7 EC_DBG_KSO0 6
5
[48] EC_DBG_KSO0 EC_DBG_KSO1 5
4
Cannn Lake PCH HM370 2060-G1-R1 2070-G2-R1 2080-G3-R1 2060-G1-MP 2070-G2-MP 2080-G3-MP [48] EC_DBG_KSO1 EC_DBG_KSO2 3 4
Refresh [48]
[48]
EC_DBG_KSO2
EC_DBG_KSO3
EC_DBG_KSO3 2 3
2
N18E-G1-A1 N18E-G2-A1 N18E-G3-A1 N18E-G1-A1 N18E-G2-A1 N18E-G3-A1 1
UH1 PCH1@ UH1 PCH3@ UH1 PCH4@ 1
SA0000CFC00 SA0000CCX00 SA0000CD500 SA0000CFC40 SA0000CCX40 SA0000CD550 JXT_FP225H-010G1AM

MP-R1 MP-R3 ES
A A
UV1 GPU7@ UV1 GPU8@
HM370 SR40B HM370 SR40B 962361/QP21 ES
SA0000BVP00 SA0000BVP30 SA0000B4I20
2050-G0-R1 2050-G0-MP

N18E-G0-A1 N18E-G0-A1
SA0000CK400 SA0000CK420 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/LID/BOM S.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 52 of 81
1 2 3 4 5
A B C D E

Power BTN
DCIN LED
+3VL

1
LED8
R7 2 1 R601 1 2 100_0402_5%
DCIN_LED_W# [48]
100K_0402_5%
19-113-T1D-CP2Q2HY-3T_WHITE
1 SW1 SW2 1
+VL

2
EVQPLHA15_4P EVQPLHA15_4P
1 3 ON/OFF# 1 3 LED10
ON/OFF# [48]
2 4 2 4 2 1 R602 1 2 100_0402_5%
DCIN_LED_O# [48]

1
A
CLRP1
5
6

5
6
15@ SHORT PADS 17@ LTST-C191KFKT-2CA_ORANGE

2
SC500005930
D24
PESD5V0U2BT_SOT23-3
ESD ESD@

1
For 15" For 17"

Change SCA00002900 to SCA00000T00

2 CPU Fan Control Circuit GPU Fan Control Circuit 2

Right Side +3VS


Left Side +3VS +5VS
+5VS
2

2
R200 2 R202
10K_0402_5% 1 10K_0402_5% 1 2
@ @ @
@
C138 C136 DIS@ C140
C137
10U_0402_6.3V6M 1 0.1U_0402_10V6K 10U_0402_6.3V6M
1

1
2 JFAN1 2 1 0.1U_0402_10V6K JFAN2
[48] EC_FAN_SPEED1 1 [48] EC_FAN_SPEED2 1
EC_FAN_SPEED1 2 1 EC_FAN_SPEED2 2 1
1 EC_FAN_PWM1 3 2 1 EC_FAN_PWM2 3 2
C139 [48] EC_FAN_PWM1 3 C141 [48] EC_FAN_PWM2 3
4 4
1000P_0402_50V7K 4 1000P_0402_50V7K 4
5 5
@ G1 @ G1
2 6 2 6
G2 G2
CVILU_CI4404M1HRT-NH CVILU_CI4404M1HRT-NH
ME@ ME@
place as close as EC place as close as EC

3 3

PCB Screw Hole CPU/GPU Thermal Standoff Fiducial Mark DDR Shielding Clip
H2 H3 H4 H5
ZZZ HOLEA HOLEA HOLEA HOLEA
H6
HOLEA
H7
HOLEA
H8
HOLEA
FD1 FD2 Larger
CLIP1 @ CLIP2 @ CLIP3 @ CLIP4 @ CLIP10@
1
1
1
1

@ @ HOLEA_35A2M HOLEA_35A2M HOLEA_35A2M HOLEA_35A2M HOLEA_35A2M

1
1 1 1 1 1
1

LA-G132P H12 FIDUCIAL_C40M80 FIDUCIAL_C40M80


H_2P5 H_2P5 H_2P5 H_2P5 HOLEA
DAB00032000
H_3P3 H_3P3 H_3P3
H13
HOLEA
H14
HOLEA
H15
HOLEA
H16
HOLEA
H17
HOLEA
H18
HOLEA FD3 FD4
Smaller
1

H9 H10 H11 CLIP11@ CLIP5 @ CLIP6 @ CLIP7 @ CLIP8 @


HOLEA HOLEA HOLEA HOLEA_12A2M HOLEA_12A2M HOLEA_12A2M HOLEA_12A2M HOLEA_12A2M
H_3P2 @ @ 1 1 1 1 1
1

1
1

1
1

H_4P6X6P6N H_4P6X6P6N H_2P5X3P5N H_2P5X3P5N


WLAN FIDUCIAL_C40M80 FIDUCIAL_C40M80
1

1
1

H_3P3 H_3P4
CLIP9 @ CLIP12@ CLIP13@ CLIP14@
H_3P3 H_3P3 H_3P3 FD5 HOLEA_12A2M HOLEA_12A2M HOLEA_12A2M HOLEA_12A2M
H19 H20 1 1 1 1
HOLEA HOLEA
4 @ 4
1

FIDUCIAL_C40M80
1

H_2P5N H_1P5N

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
FAN/LED/PBTN/PCB PN/SCREWS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 53 of 81
A B C D E
1 2 3 4 5

SATA HDD

D D

For Power consumption Measurement


+5VS 580mA +5VS_HDD

RHD3 1 @ 2 0_0603_5%
SATA HDD Conn.

10U_0402_6.3V6M

0.1U_0201_10V6K
1 1

CHD3

CHD5
+3VS

2 2 +5VS_HDD

0.1U_0201_10V6K
64mA
1

CHD7
JHDD1
UHD1 1
10 2 2 1
VDD 20 3 2
VDD 4 3
SATA_PTX_DRX_P0 CHD8 1 2 0.01U_0402_16V7K SATA_PTX_C_RD_DRX_P0 1 15 SATA_PTX_RD_DRX_P0 CHD10 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 SATA_PRX_C_DTX_P0 5 4
[17] SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_RD_DRX_N0 A_INP A_OUTP SATA_PTX_RD_DRX_N0 CHD11 1 SATA_PTX_C_DRX_N0 SATA_PRX_C_DTX_N0 5
CHD9 1 2 0.01U_0402_16V7K 2 14 2 0.01U_0402_16V7K 6
[17] SATA_PTX_DRX_N0 A_INN A_OUTN 6
7
from PCH SATA_PRX_DTX_P0 CHD121 2 0.01U_0402_16V7K SATA_PRX_C_RD_DTX_P0 5 11 SATA_PRX_RD_DTX_P0 CHD14 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 SATA_PTX_C_DRX_N0 8 7
[17] SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 SATA_PRX_C_RD_DTX_N0 B_OUTP B_INP SATA_PRX_RD_DTX_N0 CHD15 1 SATA_PRX_C_DTX_N0 SATA_PTX_C_DRX_P0 8
CHD131 2 0.01U_0402_16V7K 4 12 2 0.01U_0402_16V7K 9
[17] SATA_PRX_DTX_N0 B_OUTN B_INN 9
10
PS8527_A_EQ1 17 9 PS8527_A_DE 10
PS8527_A_EQ2 18 A_EQ1 A_DE 11
A_EQ2 8 PS8527_B_DE 12 GND1
PS8527_B_EQ1 19 B_DE GND2
PS8527_B_EQ2 13 B_EQ1 16 PS8527_DEW JXT_FP225H-010G1AM
B_EQ2 DEW

teknisi-indonesia.com
C
ME@ C
PS8527_EN 7 21
PS8527_REXT 6 EN EPAD 3
REXT GND
PS8527CTQFN20GTR2A2_TQFN20_4X4

PN:SA00007JU10

+3VS

RHD1 1 2 4.7K_0402_5% PS8527_A_DE RHD12 1 2 4.7K_0402_5% PS8527_A_DE

RHD4 1 2 4.7K_0402_5% PS8527_B_DE RHD13 1 2 4.7K_0402_5% PS8527_B_DE

RHD6 1 2 4.7K_0402_5% PS8527_A_EQ1 RHD14 1 2 4.7K_0402_5% PS8527_A_EQ1

RHD37 1 @ 2 4.7K_0402_5% PS8527_A_EQ2 RHD38 1 2 4.7K_0402_5% PS8527_A_EQ2

RHD9 1 2 4.7K_0402_5% PS8527_B_EQ1 RHD15 1 2 4.7K_0402_5% PS8527_B_EQ1


B B

RHD39 1 @ 2 4.7K_0402_5% PS8527_B_EQ2 RHD40 1 2 4.7K_0402_5% PS8527_B_EQ2

RHD10 1 2 4.7K_0402_5% PS8527_DEW RHD16 1 2 4.7K_0402_5% PS8527_DEW

RHD18 1 @ 2 10K_0402_5% PS8527_EN RHD11 1 2 4.99K_0402_1% PS8527_REXT

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 54 of 81
1 2 3 4 5
1 2 3 4 5

+3V_U3
+3VALW
@
A A
R636 1 2 0_0402_5%

Q56
W=20mils W=20mils

S
3 1

D
PJ2301_SOT23-3

G
2
1 2
[39,46,48,61] S5_PWR_EN#
R637
150K_0402_5% 1
C456
0.1U_0201_10V6K

USB Charger from YOGA730 15 2

+3VL +5VALW_USBCH +5V_CHGUSB

10K_0402_5%
10K_0402_5%

10K_0402_5%

R639 1
R638 1

R640 1

IO CONN +5V_CHGUSB
80mil
2
2

U12 W=100mils JIO1


1 12 1
USB_CHG_STATUS# 9 IN OUT 10 CHR_USB20_P3 2 1
[48] USB_CHG_STATUS# STATUS# DP_IN 2
13 11 CHR_USB20_N3 3
4 FAULT# DM_IN 2 4 3
[48] USB_CHG_ILIM_SEL ILIM_SEL DM_OUT USB20_N3 [14] 4
[48] USB_CHG_EN
USB_CHG_EN 5
EN DP_OUT
3
USB20_P3 [14]
USB3.0 With USB2.0 For Charge [17] USB3_PTX_DRX_N3 5
5
USB_CHG_CTL1 6 15 R183 1 2 2.7M_0402_1% 6
[48] USB_CHG_CTL1
USB_CHG_CTL2 7 CTL1 ILIM_LO 16 R197 1 2 24.9K_0402_1%
Right Spotlight LED [17] USB3_PTX_DRX_P3
7 6
B [48] USB_CHG_CTL2
USB_CHG_CTL3 8 CTL2 ILIM_HI 14
USB3 with Charger [17] USB3_PRX_DTX_N3
8 7 B
[48] USB_CHG_CTL3 CTL3 GND [17] USB3_PRX_DTX_P3 8
17 CHR_USB20_N3 9
T-PAD Right Speaker CHR_USB20_P3 10 9
USB2 10
22U_0603_6.3V6M

22U_0603_6.3V6M
TPS2546RTER QFN 16P PWR SW 11
SA000064O00 12 11
1 12
1

13
C194 13
C457

C458

14
0.1U_0201_10V K X5R 15 14
2

2 16 15
@ +5VALW_USBCH +5VALW
U3 Redriver [48] NOVO#
17 16
+3V_U3 17
NOVO +5V_CHGUSB 18
+VL +5VS 19 18
20 19
[62] SPL_R_CONN 20
R644 1 2 0_0603_5% Right Spotlight LED [62] SPL_G_CONN 21
22 21
[62] SPL_B_CONN 22
[45] SPK_R1-_CONN 23
24 23
Down USB charger Iout ripple L59
Right Speaker 25 24
[45] SPK_R2+_CONN 25
must under 20mA on DC S5

D
R553 1 @ 2 0_0603_5% 2 1 3 1 26
BLM15PX331SN1D_2P Q28 26
1 1

ME2301DC-G_SOT23-3
C454 L60 C453 27
4.7U_0402_6.3V6K 2 1 4.7U_0402_6.3V6K 28 GND1

G
+5VALW

2
BLM15PX331SN1D_2P GND2
2 2
10U_0402_6.3V6M

10U_0402_6.3V6M

CVILU_CF5026FD0RK-05-NH
1 1 ME@
+VL
C224

C225

@ @ R130
2 2 1 2

100K_0402_5%

1
D
R396 1 @ 2 0_0402_5% 3V/5VALW_PG_R 2 Q29
[48,63,66,69] PG_3V/5VALW
C G L2N7002WT1G_SC-70-3 C
S

3
2
1 @
C486 C90
0.1U_0201_10V K X5R 0.1U_0201_10V K X5R
1 @
2

D D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3 Port 3 CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 55 of 81
1 2 3 4 5
A B C D E

MB_USB3.1 Conn. (Port 1)


RIGHT SIDE
900mA
+5VALW_USB2

6.8P_0402_50V_NPO
JUSB1 1

C2175

RF@
1 1 1
USB20_N1_R 2 VBUS
USB20_P1_R 3 D-
4 D+ 2
USB3_PRX_DTX_N1 5 GND
[17] USB3_PRX_DTX_N1 SSRX-
USB3_PRX_DTX_P1 6 10
[17] USB3_PRX_DTX_P1 SSRX+ GND
7 11
C434 1 2 0.1U_0201_6.3V6K USB3_PTX_C_DRX_N1 8 GND GND 12
[17] USB3_PTX_DRX_N1 SSTX- GND
[17] USB3_PTX_DRX_P1 C433 1 2 0.1U_0201_6.3V6K USB3_PTX_C_DRX_P1 9 13
SSTX+ GND
ACON_TARAQ-9R1U91

D36 ESD@ D35 ESD@


USB20_P1_R 3 6 +5VALW_USB2 USB3_PRX_DTX_N1 1 1 10 9 USB3_PRX_DTX_N1
I/O2 I/O4
USB3_PRX_DTX_P1 2 2 9 8 USB3_PRX_DTX_P1

2 5 USB3_PTX_C_DRX_N1 4 4 7 7 USB3_PTX_C_DRX_N1
2
GND VDD 2
USB3_PTX_C_DRX_P1 5 5 6 6 USB3_PTX_C_DRX_P1
L43 EMI@
1 2 USB20_P1_R 1 4 USB20_N1_R 3 3
[14] USB20_P1 1 2 I/O1 I/O3
L30ESDL5V0C6-4 SOT23 8
4 3 USB20_N1_R
[14] USB20_N1 4 3 AZ1023-04F.R7G_DFN2510P10E
DLM0NSN900HY2D_4P SC300004W00 change to SC300006000

MB_USB3.1 Conn. (Port 2)

900mA LEFT SIDE +5VALW_USB2 I (Max) : 0.9 A(+5VALW_USBB)


RDS(Typ) : 70 mohm
+5VALW_USB2 V drop : 0.063 V
EN: Active Low +5VALW_USB2
1 +5VALW

220U_6.3V_M
C483
JUSB2 + U46
1 5 1 80mil
VBUS IN OUT

1U_0201_6.3V6M

6.8P_0402_50V_NPO
USB20_N2_R 2
3 USB20_P2_R 3 D- 2 2 3
D+ 1 GND
4 1
GND

C431

RF@
C177
USB3_PRX_DTX_N2 5 4 3
[17] USB3_PRX_DTX_N2 SSRX- EN(EN#) OC#
USB3_PRX_DTX_P2 6 10 @
[17] USB3_PRX_DTX_P2 SSRX+ GND 2
7 11 G524B2T11U_SOT23-5
C428 1 2 0.1U_0201_6.3V6K USB3_PTX_C_DRX_N2 8 GND GND 12 2
[17] USB3_PTX_DRX_N2 SSTX- GND
[17] USB3_PTX_DRX_P2 C429 1 2 0.1U_0201_6.3V6K USB3_PTX_C_DRX_P2 9 13
SSTX+ GND
[48] USB_EN#
ACON_TARAQ-9R1U91

D31 ESD@
USB3_PRX_DTX_N2 1 1 10 9 USB3_PRX_DTX_N2
D32 ESD@
USB20_P2_R 3 6 +5VALW_USB2 USB3_PRX_DTX_P2 2 2 9 8 USB3_PRX_DTX_P2
I/O2 I/O4
USB3_PTX_C_DRX_N2 4 4 7 7 USB3_PTX_C_DRX_N2

2 5 USB3_PTX_C_DRX_P2 5 5 6 6 USB3_PTX_C_DRX_P2
GND VDD
3 3

L38 EMI@ 1 4 USB20_N2_R 8


4 I/O1 I/O3 4
1 2 USB20_P2_R
[14] USB20_P2 1 2 L30ESDL5V0C6-4 SOT23 AZ1023-04F.R7G_DFN2510P10E

[14] USB20_N2
4
4 3
3 USB20_N2_R SC300004W00 change to SC300006000
DLM0NSN900HY2D_4P
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title
USB3 Port1/2 Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 56 of 81
A B C D E
5 4 3 2 1

Titan Ridge SP - High Speed (CIO, USB and PCIe) Parts


UT1A
Polarity Reversal is allowed on CIO/USB/DP domains.
Need to be configured on NVM. Y23 V23 PCIE_PRX_C_TTX_P17 CT2 2 1 0.22U_0201_6.3V TBT@
[17] PCIE_PTX_TRX_P17 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_C_TTX_N17 CT3 PCIE_PRX_TTX_P17 [17]
Y22 V22 2 1 0.22U_0201_6.3V TBT@
[17] PCIE_PTX_TRX_N17 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_TTX_N17 [17]
In case of unused high speed interface,
T23 P23 PCIE_PRX_C_TTX_P18 CT4 2 1 0.22U_0201_6.3V TBT@
please leave pins open. No need for termination. [17] PCIE_PTX_TRX_P18
T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_C_TTX_N18 CT5 2 1 0.22U_0201_6.3V TBT@
PCIE_PRX_TTX_P18 [17]

PCIe GEN3
[17] PCIE_PTX_TRX_N18 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_TTX_N18 [17]
From PCH PCIe TX To SoC PCIe RX
TR DP Configuration: [17] PCIE_PTX_TRX_P19
M23
PCIE_RX2_P PCIE_TX2_P
K23 PCIE_PRX_C_TTX_P19 CT6 2 1 0.22U_0201_6.3V TBT@
PCIE_PRX_TTX_P19 [17]
CIO x2 ports may be used M22 K22 PCIE_PRX_C_TTX_N19 CT7 2 1 0.22U_0201_6.3V TBT@
[17] PCIE_PTX_TRX_N19 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_TTX_N19 [17]
PCIe x4 lanes may be used H23 F23 PCIE_PRX_C_TTX_P20 CT8 2 1 0.22U_0201_6.3V TBT@ +3VALW
[17] PCIE_PTX_TRX_P20 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_TTX_P20 [17]
D DPSNK x8 lanes may be used [17] PCIE_PTX_TRX_N20
H22
PCIE_RX3_N PCIE_TX3_N
F22 PCIE_PRX_C_TTX_N20 CT9 2 1 0.22U_0201_6.3V TBT@
PCIE_PRX_TTX_N20 [17]
D

USB 3.1 may be used (for debug only)


T4
DPSRC may be used CLK_PCIE_P0 V19 PERST# PCI_RST# [16,24,48,49,50]
[15] CLK_PCIE_P0 CLK_PCIE_N0 REFCLK_100_IN_P AN_PCIE_RBIAS TBT_I2C_SDA
T19 N16 RT3 1 TBT@ 2 3.01K_0201_1% PCIE RBIAS RT4 1 TBT@ 2 2.2K_0201_1%
[15] CLK_PCIE_N0 REFCLK_100_IN_N PCIE_RBIAS TBT_PEWAKE# TBT_I2C_SCL
Y6 Y2 RT5 1 TBT@ 2 2.2K_0201_1%
[15] TBT_CLKREQ0# PCIE_CLKREQ# PEWAKE# Place as close as possible to pins
TBT@ CT1 2 1 0.22U_0201_6.3V GPU_DPA_N0_C AB7 AB21 RT216 2 @ 1 0_0201_5%
[26] GPU_DPA_N0 DPSNK1_ML0_N DPSRC_ML0_P TBT_WAKE# [18]
TBT@ CT10 2 1 0.22U_0201_6.3V GPU_DPA_P0_C AC7 AC21 RT217 2 @ 1 0_0201_5%
[26] GPU_DPA_P0 DPSNK1_ML0_P DPSRC_ML0_N EC_PCIE_WAKE# [48,50]
GPU_DPA_AUXP RV361 1 TBT@ 2 100K_0402_5% TBT@ CT11 2 1 0.22U_0201_6.3V GPU_DPA_P1_C AB9 AC19 TBT_CLKREQ0# RT8 1 @ 2 10K_0201_1%
[26] GPU_DPA_P1 DPSNK1_ML1_P DPSRC_ML1_P
GPU_DPA_AUXN RV363 1 TBT@ 2 100K_0402_5% TBT@ CT12 2 1 0.22U_0201_6.3V GPU_DPA_N1_C AC9 AB19 TBT_WAKE# RT9 1 TBT@ 2 10K_0201_1%

SOURCE PORT 0
GPU_DPB_AUXP [26] GPU_DPA_N1 DPSNK1_ML1_N DPSRC_ML1_N TBT_RST#
RV362 1 TBT@ 2 100K_0402_5% RT10 1 @ 2 10K_0201_1%

SINK PORT 1
GPU_DPB_AUXN RV364 1 TBT@ 2 100K_0402_5% TBT@ CT13 2 1 0.22U_0201_6.3V GPU_DPA_P2_C AC11 AB17 PM_BATLOW# RT11 1 TBT@ 2 10K_0201_1%
[26] GPU_DPA_P2 GPU_DPA_N2_C DPSNK1_ML2_P DPSRC_ML2_P RTD3_USB_PWR_ENRT12
TBT@ CT14 2 1 0.22U_0201_6.3V AB11 AC17 1 TBT@ 2 10K_0201_1% TBT_GPIO_8
[26] GPU_DPA_N2 DPSNK1_ML2_N DPSRC_ML2_N
TBT@ CT15 2 1 0.22U_0201_6.3V GPU_DPA_P3_C AB13 AC15 TBT_TR_PA_I2C_INTRT13 1 TBT@ 2 10K_0201_1% '0' - Unsecure mode
[26] GPU_DPA_P3 DPSNK1_ML3_P DPSRC_ML3_P '1' - Secure mode
TBT@ CT16 2 1 0.22U_0201_6.3V GPU_DPA_N3_C AC13 AB15
[26] GPU_DPA_N3 DPSNK1_ML3_N DPSRC_ML3_N
TBT@ CT17 2 1 0.22U_0201_6.3V GPU_DPA_AUXP_C N1 N4 DG_GPIO8 RT15 1 TBT@ 2 10K_0201_1%
[26] GPU_DPA_AUXP GPU_DPA_AUXN_C DPSNK1_AUX_P DPSRC_AUX_P
TBT@ CT18 2 1 0.22U_0201_6.3V N2 N5
[26] GPU_DPA_AUXN DPSNK1_AUX_N DPSRC_AUX_N
From GPU DDI RT16 1 @ 2 100K_0201_1%
DPA_HPD AA2
DPSNK1_HPD R5 TBT_DPSRC_HPD
DPSRC_HPD
TBT@ CT285 2 1 0.22U_0201_6.3V GPU_DPB_P0_C A5 +3VS
[26] GPU_DPB_P0 GPU_DPB_N0_C DPSNK2_ML0_P
TBT@ CT282 2 1 0.22U_0201_6.3V B5
[26] GPU_DPB_N0 DPSNK2_ML0_N
+3VS TBT@ CT279 2 1 0.22U_0201_6.3V GPU_DPB_P1_C B3 W1 TBT_GPIO0 SUSP# RT17 1 TBT@ 2 10K_0201_1%

LC GPIO
[26] GPU_DPB_P1 GPU_DPB_N1_C DPSNK2_ML1_P GPIO_0 DG_GPIO1 TBT_CIO_PLUG_EVENT#
TBT@ CT280 2 1 0.22U_0201_6.3V A3 W2 RT18 1 TBT@ 2 10K_0201_1%

SINK PORT 2
[26] GPU_DPB_N1 DPSNK2_ML1_N GPIO_1 TBT_GPIO3
Y1
RT212 1 TBT@ 2 100K_0201_5% GPU_DPA_AUXP_C TBT@ CT284 2 1 0.22U_0201_6.3V GPU_DPB_P2_C C2 TMU_CLKOUT AA1 TBT_CIO_PLUG_EVENT# TBT_FORCE_PWR RT19 1 @ 2 10K_0201_1%
GPU_DPA_AUXN_C [26] GPU_DPB_P2 GPU_DPB_N2_C DPSNK2_ML2_P CIO_PLUG_EVENT# DG_GPIO8 TBT_CIO_PLUG_EVENT# [16]
RT213 1 TBT@ 2 100K_0201_5% TBT@ CT286 2 1 0.22U_0201_6.3V C1 W6
GPU_DPB_AUXP_C [26] GPU_DPB_N2 DPSNK2_ML2_N TMU_CLKIN
RT214 1 TBT@ 2 100K_0201_5% RT20 1 TBT@ 2 100K_0201_1%
RT215 1 TBT@ 2 100K_0201_5% GPU_DPB_AUXN_C TBT@ CT281 2 1 0.22U_0201_6.3V GPU_DPB_P3_C E2
[26] GPU_DPB_P3 GPU_DPB_N3_C DPSNK2_ML3_P TBT_I2C_SDA
TBT@ CT283 2 1 0.22U_0201_6.3V E1 V1
[26] GPU_DPB_N3 DPSNK2_ML3_N I2C_SDA TBT_I2C_SCL TBT_I2C_SDA [59]
V2

POC GPIO
GPU_DPB_AUXP_C I2C_SCL TBT_I2C_SCL [59]
TBT@ CT277 2 1 0.22U_0201_6.3V P1 V5
[26] GPU_DPB_AUXP GPU_DPB_AUXN_C DPSNK2_AUX_P USB_FORCE_PWR TBT_USB_FORCE_PWR [16]
TBT@ CT278 2 1 0.22U_0201_6.3V P2 V4
[26] GPU_DPB_AUXN DPSNK2_AUX_N FORCE_PWR PM_BATLOW# TBT_FORCE_PWR [16] TBT_DPSRC_HPD
U2 DG_FORCE_PWR: RT23 1 TBT@ 2 100K_0201_1%
DPB_HPD BATLOW# PM_BATLOW# [18]
Y4 U1 SUSP#
DPSNK2_HPD SLP_S3# T5 RTD3_USB_PWR_EN SUSP# [48,63,67,68] '0' - Regular Mode, Force Power is disabled (Default) TBT_PA_DPSRC_HPD RT24 1 TBT@ 2 100K_0201_1%
C RTD3_PWR_EN C
'1' - Force Power Mode is enabled TBT_PB_DPSRC_HPD RT25 1 TBT@ 2 100K_0201_1%
Follow TR_DP_TI_PD_HOST_REF_DESIGN_R0V95 AC3 E5
U0_SSRXp1 RESET# TBT_RST# [59] TBT_PA_USB2_MXCTL
AB3 RT26 1 TBT@ 2 100K_0201_1%

Misc
PE isn't POR - U0_SSRXn1

USB
D22 TBT_XTAL_25_IN TBT_PB_USB2_MXCTL RT27 1 TBT@ 2 100K_0201_1%
Please don't use AB5 XTAL_25_IN D23 TBT_XTAL_25_OUT
AC5 U0_SSTXn1 XTAL_25_OUT
U0_SSTXp1
TBT_JTAG_TDI W20 TBT_GPIO0 RT29 1 TBT@ 2 100K_0201_1%
TBT_JTAG_TMS Y20 TDI Y18 DG_GPIO1 RT30 1 TBT@ 2 100K_0201_1%
TBT_JTAG_TCK TMS EE_DI TBT_EE_DI [59] TBT_GPIO3
W19 W16 RT31 1 TBT@ 2 100K_0201_1%
TBT_JTAG_TDO TCK EE_DO TBT_EE_DO [59] TBT_TEST_PWR_GOOD
Y19 MISC W18 RT32 1 TBT@ 2 100_0201_1%
TDO EE_CS# TBT_EE_CS# [59] TBT_USB_FORCE_PWR
RT34 TBT@ Y16 RT33 1 TBT@ 2 100K_0201_1%
AN_RBIAS EE_CLK TBT_EE_WP# TBT_EE_CLK [59]
Place as close as 1 2 J6 W4
4.75K_0402_0.5% AN_RSENSE J5 RBIAS EE_WP#
possible to pins RSENSE
DG_USB_FORCE_PWR:
TBT_A_TRX_R_DTX_P1 TBT@ CT287 1 2 0.33U_0201_6.3V6M TBT_A_TRX_DTX_P1 B21 A13 Might be use for seperatly force USB domain - connect to EC/PCH
[60] TBT_A_TRX_R_DTX_P1 ASSRXp1 BSSRXp1
[60] TBT_A_TRX_R_DTX_N1
TBT_A_TRX_R_DTX_N1 TBT@ CT288 1 2 0.33U_0201_6.3V6M TBT_A_TRX_DTX_N1 A21 B13 '0' - by default
ASSRXn1 BSSRXn1
TBT_A_TTX_C_DRX_P1 TBT@ CT29 2 1 0.22U_0201_6.3V TBT_A_TTX_DRX_P1 A19 A11
[60] TBT_A_TTX_C_DRX_P1 TBT_A_TTX_C_DRX_N1 TBT@ CT31 2 1 0.22U_0201_6.3V TBT_A_TTX_DRX_N1 B19 ASSTXp1 BSSTXp1 B11
DG_FORCE_PWR:
[60] TBT_A_TTX_C_DRX_N1 ASSTXn1 BSSTXn1 Connect to EC/PCH for FW update
[60] TBT_A_TRX_R_DTX_P2
TBT_A_TRX_R_DTX_P2 TBT@ CT289 1 2 0.33U_0201_6.3V6M TBT_A_TRX_DTX_P2 A15
ASSRXp2 BSSRXp2
B7 '0' - by default
TBT_A_TRX_R_DTX_N2 TBT@ CT290 1 2 0.33U_0201_6.3V6M TBT_A_TRX_DTX_N2 B15 A7 '1' - for debug only

TBT PORTS
[60] TBT_A_TRX_R_DTX_N2 ASSRXn2 BSSRXn2
TBT_A_TTX_C_DRX_P2 TBT@ CT33 2 1 0.22U_0201_6.3V TBT_A_TTX_DRX_P2 A17 A9

Port A

PORT B
[60] TBT_A_TTX_C_DRX_P2 TBT_A_TTX_C_DRX_N2 TBT_A_TTX_DRX_N2 ASSTXp2 BSSTXp2 DG_CIO_PLUG_EVENT# should be conncted to PCH SCI GPIO
TBT@ CT35 2 1 0.22U_0201_6.3V B17 B9
[60] TBT_A_TTX_C_DRX_N2 ASSTXn2 BSSTXn2
H4 L4
[60] TBT_A_SBU1 ASBU1 BSBU1
J4 L5 +3VS
[60] TBT_A_SBU2 ASBU2 BSBU2
E20 E19
D20 PA_USB2_D_P PB_USB2_D_P D19
PA_USB2_D_N PB_USB2_D_N TBT@
TBT_PA_DPSRC_HPD T2 T1 TBT_PB_DPSRC_HPD QV103
[59] TBT_PA_DPSRC_HPD PA_HPD PB_HPD

1
TBT_TR_PA_I2C_INT M4 M5 C LMBT3904WT1G_SC70-3
+3V_TBT_LC [59] TBT_TR_PA_I2C_INT TBT_PA_USB2_MXCTL R2 PA_I2C_INT PB_I2C_INT TBT_PB_USB2_MXCTL DPA_HPD
R1 2 1 2
JTAG RT43 1 TBT@ 2 200_0201_1% AN_PA_USB2_RBIAS H19 PA_USB2_MXCTL
PA_USB2_RBIAS
PB_USB2_MXCTL
PB_USB2_RBIAS
F19
E
B RT21 150K_0402_5%
USB2 Rbias Place as close as possible to TBT@

3
+1V8_AON
pins 1
2

2
2

2
10K_0201_1%

10K_0201_1%
10K_0201_1%

10K_0201_1%

TP@ T1 AN_THERMDA V8 W5 TBT_TEST_PWR_GOOD @


THERMDA TEST_PWR_GOOD
RT46

RT49
RT47

RT48

B R4 RT45 1 @ 2 0_0201_5% CV302 B


D4 TEST_EN B23
TEST_EDM USB2_ATEST T2 TP@ [19] TBTA_HPD_PCH 0.1U_0402_16V7K

1
L8 AB23 TBT@ 2
FUSE_VQPS_64 PCIE_ATEST T3 TP@

1
TBT@ TBT@ TBT@ TBT@ DEBUG J9 T4 TP@ RV340 TBT@
1

1
1

A23 ATEST_P J11 10K_0402_5% RV339


PA_MONDC ATEST_N T5 TP@
A1 H5 T6 TP@ 10K_0402_5%
TBT_JTAG_TDI AC23 PB_MONDC VGA_RES

2
TBT_JTAG_TMS AC1 PC_MONDC
[25] TBTA_HPD_GPU#

2
TBT_JTAG_TCK D5 USB_MONDC
MONDC_SVR

6
TBT_JTAG_TDO TBT@
QV104A
DMN53D0LDW-7 2N SOT363-6
THUNDERBOLT_BGA337 2
TBT@

1
RT205 +3VS
TBT_XTAL_25_IN 1 2 TBT_XTAL_25_IN_R

+3V_TBT_LC 33_0201_5%
EMI@ TBT@
QV105
2

1
+3.3V_FLASH C LMBT3904WT1G_SC70-3
R2 2 1 2 DPB_HPD
0_0402_1% @ B RT22 150K_0402_5%
E TBT@

3
+1V8_AON
SPI ROM 1
1

R1 1 @ 2 0_0402_5% @
1 CV303
CT37 0.1U_0402_16V7K
[19] TBTB_HPD_PCH

1
1U_0201_6.3VM YT1 TBT@ TBT@ 2

1
TBT@ 25MHZ 20PF +-20PPM 7R25000001 TXC SJ10000TO00 RV355 TBT@
2 RT206 10K_0402_5% RV356
TBT_XTAL_25_OUT 1 2 TBT_XTAL_25_OUT_R 3 1 Murata SJ10000UH00 10K_0402_5%
3 1

2
UT2 TBT@ 33_0201_5% 1 NC NC
1 [25] TBTB_HPD_GPU#

2
TBT_EE_CS# 1 8 EMI@ TBT@ TBT@
CS# VCC CT273

3
TBT_EE_DO 2 7 TBT_EE_HOLD# 4 2 CT274 TBT@
A TBT_EE_WP# 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK 27P_0402_50V8J 27P_0402_50V8J QV104B A
WP#(IO2) CLK 2 2
4 5 TBT_EE_DI DMN53D0LDW-7 2N SOT363-6
GND DI(IO0) 5
W25Q80DVSSIG_SO8

4
+3.3V_FLASH
25M XTAL
Must use Metal shielded crystal for
TBT_EE_DO RT1 1 TBT@ 2 2.2K_0201_1%
TBT_EE_CS# RT2 1 TBT@ 2 2.2K_0201_1%
better noise immunity.
TBT_EE_WP# RT6 1 TBT@ 2 3.3K_0201_1% (Recommended: FL2500123Z by
TBT_EE_HOLD# RT7 1 TBT@ 2 3.3K_0201_1% Pericom) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt Titanrid (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 57 of 81

5 4 3 2 1
5 4 3 2 1

UT1B
+0.9V_TBT_SVR +3VS

H9 G1
H11 VCC0P9_SVR_PAB_ANA VCC3P3_SVR G2
H12 VCC0P9_SVR_PAB_ANA VCC3P3_SVR H2
H13 VCC0P9_SVR_PAB_ANA VCC3P3_SVR E6
H15 VCC0P9_SVR_PAB_ANA VCC3P3A
H16 VCC0P9_SVR_PAB_ANA L6 +3VALW
VCC0P9_SVR_PAB_ANA VCC3P3_S0
T12 F18
T13 VCC0P9_SVR_PC_ANA VCC3P3_SX R6 +0.9V_TBT_SVR
T15 VCC0P9_SVR_PC_ANA VCC3P3_SX
D VCC0P9_SVR_PC_ANA D
J13
T9 VCC0P9_SVR L11
T11 VCC0P9_SVR_USB_ANA VCC0P9_SVR L13
VCC0P9_SVR_USB_ANA VCC0P9_SVR M8
+0.9V_TBT_PCIE N6 VCC0P9_SVR M11
VCC0P9_SVR_DPAUX_ANA VCC0P9_SVR M13
J18 VCC0P9_SVR N8
L19 VCC0P9_PCIE VCC0P9_SVR N11
M19 VCC0P9_ANA_PCIE_1 VCC0P9_SVR N13
L18 VCC0P9_ANA_PCIE_1 VCC0P9_SVR R8
M16 VCC0P9_ANA_PCIE_2 VCC0P9_SVR R11
M18 VCC0P9_ANA_PCIE_2 VCC0P9_SVR R13
+0.9V_TBT_LC VCC0P9_ANA_PCIE_2 VCC0P9_SVR R16
VCC0P9_SVR T8
+0.9V_TBT_LVR J8 VCC0P9_SVR T16
VCC0P9_LC VCC0P9_SVR E8 +0.9V_TBT_SVR_IND

VCC
H8 VCC0P9_SVR_BRD_SENSE
H6 VCC0P9_LVR K1
+3V_TBT_ANA_USB2 VCC0P9_LVR_SENSE SVR_IND K2
+3V_TBT_ANA_PCIE SVR_IND L1
+3V_TBT_ANA H18 SVR_IND L2
L16 VCC3P3_ANA_USB2 SVR_IND
+3V_TBT_LC E16 VCC3P3_ANA_PCIE H1
VCC3P3_ANA SVR_VSS J1
V6 SVR_VSS J2
VCC3P3_LC SVR_VSS

A6 AB18
A8 VSS_ANA VSS_ANA AB20
A10 VSS_ANA VSS_ANA AB22
A12 VSS_ANA VSS_ANA AC6
A14 VSS_ANA VSS_ANA AC8
A16 VSS_ANA VSS_ANA AC10
A18 VSS_ANA VSS_ANA AC12
C A20 VSS_ANA VSS_ANA AC14 +0.9V_TBT_PCIE +0.9V_TBT_SVR C
A22 VSS_ANA VSS_ANA AC16
B6 VSS_ANA VSS_ANA AC18
B8 VSS_ANA VSS_ANA AC20
VSS_ANA VSS_ANA

10U_0402_6.3V6M

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM
1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM
B10 AC22 1 1 1 1 1 1 1
VSS_ANA VSS_ANA

CT45 TBT@

CT47 TBT@

CT48 TBT@

CT50 TBT@

CT51 TBT@
CT46 TBT@

CT49 TBT@
B12 E4 1 1 1 1 1
VSS_ANA VSS_ANA

CT40 TBT@

CT41 TBT@

CT42 TBT@

CT44 TBT@
CT43 TBT@
B14 F5
B16 VSS_ANA VSS_ANA J12
B18 VSS_ANA VSS_ANA F6 2 2 2 2 2 2 2
B20 VSS_ANA VSS_ANA J15 2 2 2 2 2
B22 VSS_ANA VSS_ANA B2
D8 VSS_ANA VSS_ANA B1
D9 VSS_ANA VSS_ANA D1
D11 VSS_ANA VSS_ANA A2
D12 VSS_ANA VSS_ANA J16
D13 VSS_ANA VSS_ANA V13
VSS_ANA VSS_ANA +0.9V_TBT_LC +0.9V_TBT_LVR

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM
1U_0201_6.3VM

1U_0201_6.3VM
D15 V12 1 1 1 1 1 1 1
VSS_ANA VSS_ANA

CT57 TBT@

CT58 TBT@
CT53 TBT@

CT54 TBT@

CT56 TBT@
CT52 TBT@

CT55 TBT@
D16 V11
GND

D18 VSS_ANA VSS_ANA M6


VSS_ANA VSS_ANA

1U_0201_6.3VM
E9 U23 1
VSS_ANA VSS_ANA 2 2 2 2 2 2 2

TBT@

CT61

10U_0402_6.3V6M

10U_0402_6.3V6M
E11 U22
VSS_ANA VSS_ANA

1U_0201_6.3VM
1U_0201_6.3VM
E15 T20 1 1 1 1
VSS_ANA VSS_ANA

CT59 TBT@

CT60 TBT@

CT63 TBT@
CT62 TBT@
H20 R23
E22 VSS_ANA VSS_ANA R22 2
E23 VSS_ANA VSS_ANA R20
F9 VSS_ANA VSS_ANA R19 2 2 2 2
F16 VSS_ANA VSS_ANA R18
F20 VSS_ANA VSS_ANA W11
G22 VSS_ANA VSS_ANA Y11 +3V_TBT_LC +3V_TBT_ANA_PCIE +3V_TBT_ANA_USB2 +3V_TBT_ANA
G23 VSS_ANA VSS_ANA C23
L20 VSS_ANA VSS_ANA F15
VSS_ANA VSS_ANA

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM

1U_0201_6.3VM
L22 V9 1 1 1 1
VSS_ANA VSS_ANA

CT67 TBT@
CT65 TBT@

CT66 TBT@
CT64 TBT@
L23 V15
J19 VSS_ANA VSS_ANA V20 +0.9V_TBT_SVR_IND +0.9V_TBT_SVR
J20 VSS_ANA VSS_ANA W8
B J22 VSS_ANA VSS_ANA W9 2 2 2 2 B
J23 VSS_ANA VSS_ANA W22 LT4 1 2 0.6UH_TMPC0412HP-R60MG-Z02_6A_20%
M20 VSS_ANA VSS_ANA W23 SHI0000MD00
VSS_ANA VSS_ANA

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
N20 Y9 TBT@
VSS_ANA VSS_ANA

1
CT68 TBT@

CT69 TBT@

CT70 TBT@
N22 Y13
N23 VSS_ANA VSS_ANA AA22
C22 VSS_ANA VSS_ANA AA23

2
E18 VSS_ANA VSS_ANA AB6
W13 VSS_ANA VSS_ANA AB8
AB2 VSS_ANA VSS_ANA AB10
A4 VSS_ANA VSS_ANA AB12 +3VALW
B4 VSS_ANA VSS_ANA AB14
Y8 VSS_ANA VSS_ANA AB16
F2 VSS_ANA VSS_ANA N19
D2 VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N18 Share Same GND plane
F1 F8
VSS_ANA VSS_ANA +3VS

1U_0201_6.3VM

1U_0201_6.3VM
AC4 F13 1 1
VSS_ANA VSS_ANA

CT71 TBT@

CT72 TBT@
AB4 F12
Y5 VSS_ANA VSS_ANA F11
Y12 VSS_ANA VSS_ANA E13
VSS_ANA VSS_ANA 2 2

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M
W12 E12
VSS_ANA VSS_ANA

1U_0201_6.3VM

1U_0201_6.3VM
D6 W15 1 1 1 1 1
VSS_ANA VSS_ANA

CT75 TBT@
CT74 TBT@
CT73 TBT@

CT77 TBT@
CT76 TBT@
AB1 Y15
AC2 VSS_ANA VSS_ANA
VSS_ANA
2 2 2 2 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

TBT@ THUNDERBOLT_BGA337
M15
V16
L12
R15
R9
R12
L9
M9
F4
V18
L15
N15
M1
M2
N12
T6
T18
N9
M12

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt Titanrid (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 58 of 81
5 4 3 2 1
5 4 3 2 1

+5VALW
+3VALW_TBT
TBT@
+5VALW +3VALW_TBT RT219 UT3
D 1 @ 2 1 5 D
VCC VOUT
120mil 3A 0_0402_5% 2
GND

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M
3 4 1
NC EN TBT@
1 1 1 1 1 CT292
RT9069-33GB_SOT23-5 1U_0201_6.3V6M
2

CT90

CT92

CT93
CT91
CT22
4.7U_0402_6.3V6K RT220 1 @ 2 0_0201_5%
2 2 2 2 2
TBT@
TBT@ TBT@ TBT@ TBT@
RT218 1 @ 2 0_0402_5%
Close to UT10 1
TBT@
Close to UT10 CT291
1U_0201_6.3V6M
2

+TBTA_VBUS

120mil 3A

2 TBT@

1
CT260 CT222 TBT@
1U_0402_25V6K 0.1U_0402_25V6 DT246
+3VALW_TBT +5VALW TBT@ NSR20F30NXT5G_DSN2-2

2
1

2
C C
+3VALW_TBT UT10
120mil 3A Close to UT10
7 8
PP_HV1 VBUS1
2

1
3.3K_0201_5%

3.3K_0201_5%

TBTA_CC1 CT265 1 2 220P_0201_25V7K


RT191
@ @ 10K_0201_5% 1 2 TBT_VBUS2 TBT@
TBT@ +3VALW_TBT PP_HV2 VBUS2 +LDO_1V8_PD +3.3V_FLASH TBTA_CC2 CT269 1 2 220P_0201_25V7K
PU at EC side

TBT@
RT189

RT190

1 5 +3.3V_FLASH
3 LDO_3V3 26 +LDO_1V8_PD
CT263 VIN_3V3 LDO_1V8
2
10U_0402_6.3V6M 2 10U_0402_6.3V6M
2 TBT@ 15 TBTA_CC1 10U_0402_6.3V6M CT272
C1_CC1 TBTA_CC1 [60]
17 TBTA_CC2 CT262 TBT@
C1_CC2 TBTA_CC2 [60] 1
[48,64,65] EC_SMB_CK1 18 TBT@
19 I2C1_SCL 36 TBTB_CC1 1
[48,64,65] EC_SMB_DA1 I2C1_SDA C2_CC1
20 38 TBTB_CC2
[48] PD_IRQ# I2C1_IRQ C2_CC2
[57] TBT_I2C_SCL 23
24 I2C2_SCL 4 ADCIN1
[57] TBT_I2C_SDA I2C2_SDA ADCIN1 +5VALW
[57] TBT_TR_PA_I2C_INT 25 6 ADCIN2
I2C2_IRQ ADCIN2 +3.3V_FLASH
16
PP1_CABLE 37
PP2_CABLE 1
TBT_EE_DO 27
[57] TBT_EE_DO SPI_MISO(GPIO8)
TBT_EE_DI 28 41 TP3 @ CT271
[57] TBT_EE_DI SPI_MOSI(GPIO9) C1_USB_P(GPIO18)

1
TBT_EE_CLK 29 42 TP4 @ 4.7U_0402_6.3V6K
[57] TBT_EE_CLK SPI_CLK(GPIO10) C1_USB_N(GPIO19) 2
TBT_EE_CS# 30 RT192 RT193
[57] TBT_EE_CS# SPI_SS(GPIO11) TBT@
43 TP5 @ 10K_0201_1% 10K_0201_1%
C2_USB_P(GPIO20) 44 TP6 @ TBT@ TBT@
C2_USB_N(GPIO21)

2
9 TBT_RST#_R RT194 1 2 0_0402_5% ADCIN1
RT174 1 @ 2 0_0402_5% HRESET 35 GPIO0 10 TBT_GPIO1 TBT_RST# [57] ADCIN2
[48] PD_RESET HRESET GPIO1 11 TBT_GPIO2 TP1 @
GPIO2 21
HPD1(GPIO3) TBT_PA_DPSRC_HPD [57]

1
1
22 TP14 @
45 HPD2(GPIO4) 12 TP15 @ RT195 RT196
46 NC GPIO5 13 TP16 @ 100K_0201_1% 100K_0201_1%
NC GPIO6 14 TP17 @ TBT@ TBT@
B B
47 GPIO7 31 TBT_GPIO12 TP8 @

2
2
G-Pad GPIO12 32 TBT_GPIO13 TP9 @
+3VALW_TBT GPIO13 33 TBT_GPIO14 TP10 @
A1 GPIO14(PWM) 34 TBT_GPIO15 TP11 @ +5VALW
A2 NC1 GPIO15(PWM) 39 TBTA_PPEXT_EN
A3 NC2 GPIO16(PP_EXT1) 40 TBT_GPIO17 TP12 @
RT198 1 @ 2 100K_0201_5% HRESET A4 NC3 GPIO17(PP_EXT2)
NC4 TBTA_PPEXT_EN RT207 1 TBT@ 2 100K_0201_5%
RT180 1 @ 2 1M_0201_5% Pull-down at EC side

4.7U_0402_6.3V6K

4.7U_0402_6.3V6K
TBT@ SN1701012RSLR_VQFN48_6X6
@ SA0000BAN00 TBT_GPIO1 RT208 1 TBT@ 2 1M_0201_5% 2 2

CT225

CT268
0.01U_0201_6.3V7K 2 1 CT231
TBT@ TBT@
TBT_VBUS2 RT209 1 TBT@ 2 1M_0201_5%
1 1

TBTB_CC1 RT210 1 TBT@ 2 1M_0201_5%

TBTB_CC2 RT211 1 TBT@ 2 1M_0201_5%


place near 16,37 pin

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC_TPS65988
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 59 of 81
5 4 3 2 1
5 4 3 2 1

Main source:SC40000AT00
Foorprint: ESD8011MUT5G_X3DFN2-2(SC40000AR00 Footprint)
DT232 ESD@

[57] TBT_A_TTX_C_DRX_P2 1 2

DT233 ESD@
PESD5V0H1BSF_SOD962-2-2
[57] TBT_A_TTX_C_DRX_N2 1 2

DT234 ESD@
PESD5V0H1BSF_SOD962-2-2
D 1 2 D
[57] TBT_A_TRX_R_DTX_P2
DT235 ESD@ LT3 EMI@
PESD5V0H1BSF_SOD962-2-2 1 2 TBT_A_USB20_N5
[14] USB20_N5 1 2
[57] TBT_A_TRX_R_DTX_N2 1 2

DT236

1
ESD@

2
PESD5V0H1BSF_SOD962-2-2
[14] USB20_P5 4
4 3
DLM0NSN900HY2D_4P
3 TBT_A_USB20_P5
EMI
[57] TBT_A_TTX_C_DRX_P1
DT237 ESD@
PESD5V0H1BSF_SOD962-2-2
[57] TBT_A_TTX_C_DRX_N1 1 2

DT238 ESD@
PESD5V0H1BSF_SOD962-2-2
[57] TBT_A_TRX_R_DTX_P1 1 2

DT239 ESD@
PESD5V0H1BSF_SOD962-2-2
[57] TBT_A_TRX_R_DTX_N1 1 2

www.teknisi-indonesia.com
PESD5V0H1BSF_SOD962-2-2

C
different from USB3.0 port's ESD ESD Diode for CC1 CC2 C

ESD DT242 ESD@


ESD@ D26 TBTA_CC2 1 1 10 9 TBTA_CC2
3 6 TBT_A_USB20_N5
I/O2 I/O4 TBTA_CC1 2 2 9 8 TBTA_CC1
+5VALW
TBT_A_SBU2 4 4 7 7 TBT_A_SBU2
2 5
GND VDD TBT_A_SBU1 5 5 6 6 TBT_A_SBU1

3 3
TBT_A_USB20_P5 1 4
I/O1 I/O3 8
AZC099-04S.R7G_SOT23-6
L05ESDL5V0NA-4_SLP2510P8-10-9

SC300001G00 change to SC300006000

+TBTA_VBUS +TBTA_VBUS

B B

JTYPEC1
A1 B12
GND_A1 GND_B12
TBT_A_TTX_C_DRX_P2 A2 B11 TBT_A_TRX_R_DTX_P2
TBT_A_TTX_C_DRX_N2 A3 TX1+ RX1+ B10 TBT_A_TRX_R_DTX_N2
TX1- RX1- TBT@
TBT@ CT94 1 2 0.47U_0402_25V6K A4 B9 CT96 1 2 0.47U_0402_25V6K
VBUS_A4 VBUS_B9
[59] TBTA_CC2 A5 B8
CC1 SBU2 TBT_A_SBU1 [57]
TBT_A_USB20_P5 A6 B7 TBT_A_USB20_N5
TBT_A_USB20_N5 A7 D+_A6 D-_B7 B6 TBT_A_USB20_P5
Bottom

D-_A7 D+_B6
TOP

[57] TBT_A_SBU2 A8 B5
SBU1 CC2 TBTA_CC1 [59]
TBT@ CT95 1 2 0.47U_0402_25V6K A9 B4 1 2
VBUS_A9 VBUS_B4 CT97 0.47U_0402_25V6K
TBT_A_TRX_R_DTX_N1 A10 B3 TBT_A_TTX_C_DRX_N1 TBT@
TBT_A_TRX_R_DTX_P1 A11 RX2- TX2- B2 TBT_A_TTX_C_DRX_P1
RX2+ TX2+
A12 B1
GND_A12 GND_B1

3
1 4
2 GND1 GND4 5 ESD@ DT245
3 GND2 GND5 6
GND3 GND6 L30ESD24VC3-2_SOT23-3

1
JAE_DX07SL24JJ2
A ME@ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2018/7/31 Deciphered Date 2018/7/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.1 TypeC Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G132P
Date: Wednesday, January 09, 2019 Sheet 60 of 81
5 4 3 2 1
5 4 3 2 1

+3VALW +3VALW_KBL
+3VALW_KBL
@
RBL1 1 2 0_0402_5% JKBL1
+3VALW_KBL UBL1 24
QBL13 49 23 GND
1 PGND 48 GND
W=20mils W=20mils [45] AUDIO_SMCLK0 SMCLK0/GPC0 VSS

S
3 1 2 47 COM7 LE 22

D
[45] AUDIO_SMDAT0 SMCLK1_AG_BLC 3 SMDAT0/GPC1 PWM15/GSW7/TACH1/GPB7 22
46 COM6 SCLK 21
SMCLK1/GPC2 Slave PWM14/GSW6/TACH0/GPB6 COM6 [62] 21

1
SMDAT1_AG_BLC 4 45 COM5 SDOL 20
SMDAT1/GPC3 PWM13/GSW5/GPB5 COM5 [62] +3VS [62] SDOL 20
PJ2301_SOT23-3 RBL27 TP@TPBL107 TXD 5 44 COM4 19

G
COM4 [62]

2
TP@TPBL108 RXD 6 TXD/GPC4 PWM12/GSW4/GPB4 43 COM3 GCLK 18 19
10K_0402_5% RXD/GPC5 PWM11/GSW3/GPB3 COM3 [62] 18
7 42 COM2 +3VALW_KBL 17
[39,46,48,55] S5_PWR_EN#
1 2 CBL25 2 1 0.1U_0201_10V6K 8 VSTBY33 IT8295FN PWM10/GSW2/GPB2 41 COM1
COM2
COM1
[62]
[62]
RBL71 1 @ 2 0_0402_5% 16 17

2
D
WRST# WRST# 9 VCOREB2 PWM9/GSW1/GPB1 40 COM0 SDO 15 16 D
COM0 [62]
RBL76
150K_0402_5% 1
CBL38 1 INT_AG_BLC
10
11
WRST#
VSS QFN-48 PWM8/GSW0/GPB0
VSTBY33
39
38 +5VS
14
13
15
14
0.1U_0201_10V6K CBL27 12 GPE0 VSS 37 TP@ 12 13
[52] KB_ESC_LED# GPE1 SSCE1#/PWM7/GPA7 TPBL109 12
1U_0201_6.3V6M KBID0 13 36 TPBL110 TP@ 11
2 14 GPE2 SMOSI1/PWM6/GPA6 35 TP@ COM0 10 11
2 [52] KB_F1_LED# GPE3 SSCK1/PWM5/GPA5 TPBL111 10
15 34 SDO_R RBL2 1 @ 2 0_0402_5% SDO COM1 9
[52] KB_F4_LED# GPE4 GLK1/SMISO1/PWM4/GPA4 9
16 33 LE COM2 8
+3VALW_KBL [52] KB_CAP_LED# GPE5 SSCE0#/PWM3/GPA3 LE [62] 8
17 32 SDI COM3 7
[52] KB_NUM_LED# GPF4 SMOSI0/PWM2/GPA2 SCLK_R RBL68 1 EMI@ SDI [62] 7
2 1 18 31 2 47_0402_5% COM4 6
VCOREB SSCK0/PWM1/GPA1 GCLK_R RBL69 1 EMI@ SCLK [62] 6
0.1U_0201_10V6K CBL26 19 30 2 47_0402_5% COM5 5

[14] USB20_N6
[14] USB20_P6
20
21
22
VSTBY33
DM
DP
GLK0/SMISO0/PWM0/GPA0
VSTBY33
GPD0
29
28
27
GCLK [62]
EMI COM6
COM7
KBID0
4
3
2
5
4
3
KBL_ID 23 VSS VSTBY33 26 SCLK 1 2
24 GPF5 GPG0 25 RBL30 1 2 GCLK 1
+3VALW_KBL GPF6 GPF7 10K_0402_5% CVILU_CF5022FD0RK-05-NH

10P_0402_50V8J

10P_0402_50V8J
ME@

@EMI@

@EMI@
10U_0402_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0201_10V6K
10U_0402_6.3V6M

0.1U_0402_10V6K
IT8295FN-120A-BX_QFN48_6X6 1 1

CBL36

CBL37
1 @ 1 @ 1 @ 1 @ 1 1 RBL26 1 2 2.2K_0402_5% SMCLK1_AG_BLC
CBL19 CBL20 CBL21 CBL22 CBL23 CBL24
RBL28 2 1 2.2K_0402_5% SMDAT1_AG_BLC
2 2
2 2 2 2 2 2
+3VALW_KBL
SKU KB_ID
+3VS
KBL_ID 1 2 15 0
RBL75 @ 10K_0402_5%
RBL46 1 2 2.2K_0402_5% AUDIO_SMCLK0 17 1
Near UBL1's PIN7,19,27,29,39 1 2
RBL47 2 1 2.2K_0402_5% AUDIO_SMDAT0 RBL74 @ 10K_0402_5%

C C

+3VALW +3VALW_AG +3VALW_AG


+3VALW_AG
@
RBL37 1 2 0_0402_5%

CBL31

CBL32
QBL14
+AVCC33_AG +3VALW_AG

0.1U_0201_10V6K
0.1U_0402_10V6K
W=20mils W=20mils 1 1
S

3 1
D

1 1
CBL29 CBL30

0.1U_0201_10V6K

0.1U_0201_10V6K
@ RBL25 1 @ 2 0_0603_5%
2 2

0.1U_0201_10V6K
PJ2301_SOT23-3
G

1
2

CBL18 2 2
1 1

CBL33
1U_0201_6.3V6M
S5_PWR_EN# 1 2 CBL34
2 1000P_0402_50V7K
RBL78 2 2
150K_0402_5% 1
CBL39
0.1U_0201_10V6K
near pin8 near pin18

17

18

32
7

8
UBL3
2

VCOREB2

VSTBY33
VSTBY33

AVCC33
VCOREB
TPBL112 TP@
AG_WRST# 48 TPBL113 TP@
WRST#
1 SMCLK0_AG_EC_R RBL40 1 @ 2 0_0402_5%
SMCLK0/PWM0/GPA0 SMDAT0_AG_EC_R EC_SMB_CK4 [48]
2 RBL41 1 @ 2 0_0402_5%
19
Slave SMDAT0/PWM1/GPA1 3 SMCLK1_AG_BLC_R RBL42 1 @ 2 0_0402_5% SMCLK1_AG_BLC EC_SMB_DA4 [48]
[14] USB20_N4 20 DM SMCLK1/PWM2/GPA2 4 SMDAT1_AG_BLC_R RBL43 1 @ 2 0_0402_5% SMDAT1_AG_BLC
+3VALW_AG [14] USB20_P4 DP Master SMDAT1/PWM3/GPA3

[52] KSI[0..7]
KSI0 37
KSI0/ADC16/STB#/GPD0
1

KSI1 38
B
RBL39 KSI2 39 KSI1/ADC17/AFD#/GPD1 B
KSI3 40 KSI2/ADC18/INIT#/GPD2
10K_0402_5% KSI3/ADC19/SLIN#/GPD3
KSI4 41 5 TPBL102 TP@
KSI5 42 KSI4/ADC20/GPD4 PWM5/GPA5 47 TPBL114 TP@
2

AG_WRST# KSI6 43 KSI5/ADC21/GPD5 PWM4/GPA4


KSI7 44 KSI6/ADC22/GPD6
KSI7/ADC23/GPD7
IT8176FN +3VALW_AG
CBL35
1U_0201_6.3V6M
1

You might also like