沈炜

杭州宇称电子技术有限公司

1
• Digital Design Flow Introduction

• Mixed Signal ASIC Design Flow

• Analog Macro : Processing Steps

• Analog Macro : Liberty / DB

• Analog Macro : LEF (Ant, Abutment, Feedthru)

2
Digital Design Flow Introduction

Mixed Signal ASIC Design Flow

Analog Macro Processing Steps

Analog Macro : Liberty / DB

Analog Macro : LEF (Ant, Abutment, Feedthru)

3
Library & Macro Files Functional netlist Timing Constraints (sdc)
(.lib, .db, .lef) (.v, .vhd, .sv)

Synthesis (DC Compiler, Genus, etc) Formal Verification

(LEC)
Timing netlist (.v), std cells & Macros
not met constraints (.sdc)
Place and Route (Innovus) Formal Verification
Signoff Verification
DRC and LVS (PVS)
STA (Timing Check)
Technology & Library Files
(liberty, qrc techfile, Layout in OA / gds
abstract lef or OA, ...) Netlist in Verilog
post extraction simulations with sdf
Time Closure Checking with spef 4
Library & Macro Files Functional netlist Timing Constraints (sdc)
(.lib, .db, .lef) (.v, .vhd, .sv)

Synthesis (DC Compiler, Genus, etc) Formal Verification

(LEC)
Timing netlist (.v), std cells & Macros
not met constraints (.sdc)
Place and Route (Innovus) Formal Verification
Signoff Verification
DRC and LVS (PVS)
STA (Timing Check)
Technology & Library Files
(liberty, qrc techfile, Layout in OA / gds
abstract lef or OA, ...) Netlist in Verilog
post extraction simulations with sdf
Time Closure Checking with spef 5
Synthesizable Functional Verilog / VHDL / S-Verilog
• no delay in functional netlist
o e.g. `timescale 1ns/10ps
• correct partitioning
o Partition for design reuse
o partition the top level , avoid top level glue logic
IPs, IOs, Macros without any combinational logic on top level
o IOs / Pads separated from core logic
o avoid multiple clock within one block
• synthesis-aware coding (Latch, Register, Mux, etc)
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SDC constraint File :
Clocks : system clock, slow clock, debug clock, generated clock
set clock transition / latency / uncertainty
set_clock_groups -asynchronous
set_propagated_clock
Multi-Cycle :
set_multicycle_path -setup/hold
Ports : set load
Exceptions : set false path, set dont touch (minimizing parasitic)

Special Constraints :
set case analysis (Clock Multiplexing)
set input/output delay ( A/D interface, Hierarchical Digital Blocks )
set max/min delay (Large Combinational Logics in Sequential Cells)
set driving cell (Block-wise synthesis, A/D interface)
…… 7
Library & Macro Files Gate & IP Macro Timing Constraints (sdc)
(.lib, .db, .lef) Netlist (.v)
Formal Verification (LEC)

Initialization (Import)
Floorplan
Placement + Opt
CTS
PostCTS
Formal Verification
Route
Signoff Verification
Postroute
DRC and LVS (PVS)
STA (Timing Check)
Technology & Library Files
(liberty, qrc techfile, Layout in OA / gds
abstract lef or OA, ...) Netlist in Verilog
post extraction simulations with sdf 8
Time Closure Checking with spef
globalNetConnect -pgpin / -tiehi / -tielo , analog / digital separation ,
pwron reset (IO) 9
• Placement & Opt combined together
• Using Placement constraints
• Gcell overlapping

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• Ccopt_design w or w/o –cts : useful skew

11
12
Check the compatibility of tech.lef & caliber rules
13
Library & Macro Files Functional netlist (.v)
Timing Constraints (sdc)
(.lib, .db, .lef) Design Simulation/Verification

Synthesis (DC Compiler, Genus, etc) Formal Verification

(LEC)
Timing netlist (.v), std cells & Macros
not met constraints (.sdc)
Place and Route (Innovus) Formal Verification
Signoff Verification
DRC and LVS (PVS)
STA (Timing Check)
Technology & Library Files
(liberty, qrc techfile, Layout in OA / gds
abstract lef or OA, ...) Netlist in Verilog
post extraction simulations with sdf
Time Closure Checking with spef 14
Universal Verification Methodology Logic Equivalence Verification
Design Verification Formality (S)/Conformal(C)

systemverilog / e – language RTL Design

Modelsim / Questa

Synthesis LEC
Sequencer Score
board Gate Netlist

Place & Route LEC

Driver DUT Monitor
Layout Netlist

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• Adding Filler : with / without Capa ， dynamic power integrity
• Standard Parasitic Exchange Format File Generation
• Standard Delay Format File generation

• Logic Equivalence Checking

• Simulation with SDF file / Modelsim
• Timing Closure with SPEF file / Tempus / PrimeTime

• DRC and LVS(short) checks using INNOVUS

• Streamout GDS/DEF/Verilog

• DRC/LVS Signoff
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• Power & IR Drop Analysis (Voltus within innovus)

Vector (VCD) file (modelsim)

Vectorless (TCF) file

For activity estimation

IR Drop / EM / Power
Static/dynamic estimation

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Digital Design Flow Introduction

Mixed Signal ASIC Design Flow

Analog Macro Processing Steps

Analog Macro : Liberty / DB

Analog Macro : LEF (Ant, Abutment, Feedthru)

18
Library & Macro Files Functional netlist (.v)
Timing Constraints (sdc)
(.lib, .db, .lef) Design Simulation/Verification

Synthesis (DC Compiler, Genus, etc) Formal Verification

(LEC)
Timing netlist (.v), std cells & Macros
not met constraints (.sdc)
Place and Route (Innovus) Formal Verification
Signoff Verification
DRC and LVS (PVS)
STA (Timing Check)
Technology & Library Files
(liberty, qrc techfile, Layout in OA / gds
abstract lef or OA, ...) Netlist in Verilog
post extraction simulations with sdf
Time Closure Checking with spef 19
Addition to the digital design flow :

• Macro Timing / Abstract generation

• Special Floorplan / Route

• Special Timing Closure for analog-wise drawn digital blocks

• Ground / Power Separation & Signoff

• IO & Substrate Separation & Signoff

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Digital Design Flow Introduction

Mixed Signal ASIC Design Flow

Analog Macro Processing Steps

Analog Macro : Liberty / DB

Analog Macro : LEF (Ant, Abutment, Feedthru)

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• Timing & Abstract Files Generation
o Liberty / DB file : lib -> db [Library Compiler (S) ]
delay , rise/fall time , noise , power etc.
o LEF file : abstract generator (C)
blockage , antenna , abutment , feedthru
o GDS file : streamout (virtuoso)
o CDL file : lvs (virtuoso)
o Verilog file
o DEF file

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Digital Design Flow Introduction

Mixed Signal ASIC Design Flow

Analog Macro Processing Steps

Analog Macro : Liberty / DB

Analog Macro : LEF (Ant, Abutment, Feedthru)

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• In principle, for an non-so-complicated Macro, the lib file can be
generated manually, as long as the correct format is followed

• Definition Part
(units, library properties, PVT conditions, versions )
+
Description Part
(timing, noise, power, etc.)

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• general library info
• units
• PVT condition library(Test_ARRAY){
• level definition delay_model:table_lookup;
• delay definition revision: 1.0;
date: "Sat Jan 30 15:37:50 2019";
• default pincap , derate , fanout comment: "xxxx";
• default max transition
• etc ……

/* operation conditions */ /* unit attributes */

nom_process: 1 time_unit: "1ns";
nom_temperature: -40; voltage_unit: "1V";
nom_voltage: 0.88; current_unit: "1uA";
operating_conditions(fast) { pulling_resisitance_unit: "1kohm";
process: 1; leakage_power_unit: "1pW";
temperature: -40; capacitive_load_unit(1,pf);
voltage: 0.88;
tree_type: balanced_tree；}
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 /* threshold definitions */ 1
input_threshold_pct_fall: 50; ideal 0
input_threshold_pct_rise: 50;
1
output_threshold_pct_fall: 50; real
0
output_threshold_pct_rise: 50;

1
1 input
input input_threshold_pct_rise 1 port
port 50
5
input_threshold_pct_fall 0 0
input 1
port 0 5
output port 1
0
50 output_threshold_pct_ris
output_threshold_pct_fall output port 0 e

Dela 0 Dela
y y

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 /* threshold definitions */
slew_lower_threshold_pct_fall: 10;
slew_upper_threshold_pct_fall: 90;
slew_lower_threshold_pct_rise: 10;
slew_upper_threshold_oct_rise: 90;

fall rise
slew slew

1 1
90 90
slew-
slew-
10 10 upper_threshold_pct_rise
upper_threshold_pct_fall
slew-
slew-lower_threshold_pct_fall 0 0 lower_threshold_pct_rise

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Most Simplified Description of Macros : Port Constraints
8 Types of Ports, treated & constrained differently:
digital input (syn, asyn) : input cap
digital output : max_fanout, max_cap, max_transition(DRV)
syn： related_pin(clock ), timing_sense(unate), timing_type(rising/falling),
rise_time, fall_time, delay, etc
asyn： related_pin(clock ), timing_sense(unate), timing_type(rising/falling),
rise_time, fall_time,
delay(virtual + real)
Table : 1 pf: 1ns+50ps (real + virtual)
1.5pf: 1.3ns+50ps (real + virtual)
1.8pf: 1.7ns+50ps (real + virtual)

analog input：cap (not mandatory)

analog output：max_cap, max_fanout
power: current（power, not mandatory)
ground : not mandatory , used for lp design

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Timing (NLDM) Description in
Look Up Table formats /*2-D Power Template*/
lu_table_template(power_template_3x3)
{
variable_1:input_net_transition;
variable_2:tatal_output_net_capacitance;
/*2-D Input Dependence Template*/
index_1("100, 101, 102");
lu_table_template(template_3x3) {
index_2("100, 101, 102"); }
variable_1:constrained_pin_transition;
variable_2:related_pin_transition;
index_1("100, 101, 102");
index_2("100, 101, 102"); } /*2-D Delay Template */
lu_table_template(delay_template_3x3) {
variable_1:input_net_transition;
variable_2:tatal_output_net_capacitance;
index_1("100, 101, 102");
index_2("100, 101, 102"); }
cell(xxxx){ #定义cell名称 /*定义端口B的时序信息*/
cell_footprint:xxx; #定义引脚名称 timing(){
area: xxx; #定义单元面积大小 related_pin: "A"; #定义相关输入信号为A
pin(A){ timing_sense: positive_unate； #定义B与A正相关
direction:input; #定义端口A是输入端口 timing_type: rising_edge; #定义时序类型，为上升
capacitance：xx；} #定义端口A的电容大小 沿
#定义输出信号B 上 升的
pin(B){ cell_rise(delay_template_3x3){
单元传播延时，index_1是
direction:output; #定义端口B为输出端口 index_1("1.1, 1.2, 1,3");
输入信号A的转换时间
capacitance：xx； #定义端口B的电容大小 index_2("2.1, 2.1, 2.3");
function: "A"; #定义端口B是同A的一个操作 values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
internal_power(){ #定义单元内部的功耗 cell_fall(delay_template_3x3){ #定义输出信号B 下 降的
related_pin: "A"; #定义相关输入信号 index_1("1.1, 1.2, 1,3"); 单元传播延时，index_1是
rise_power(power_template_3x3){ #定义端口B上升所消耗的功耗 index_2("2.1, 2.1, 2.3"); 输入信号A的转换时间
index_1("1.1, 1.2, 1.3"); values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
index_2("2.1, 2.2, 2.3"); rise_transition(delay_template_3x3){
#定义与输入信号A相关
values( "1 , 4, 7, 2, 5, 8, 3, 6, 9"); } index_1("1.1, 1.2, 1,3");
的输出信号B上升的转换
fall_power(power_template_3x3){ #定义端口B下降所消耗的功耗 index_2("2.1, 2.1, 2.3");
时间
index_1("1.1, 1.2, 1.3"); values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
index_2("2.1, 2.2, 2.3"); fall_transition(delay_template_3x3){ #定义与输入信号A相关
values( "1 , 4, 7, 2, 5, 8, 3, 6, 9"); } index_1("1.1, 1.2, 1,3"); 的输出信号B下降的转换
index_2("2.1, 2.1, 2.3"); 时间
values( /* 2.1 2.2 2.3 */ values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }

/* 1.1 */ 1, 4, 7,
/* 1.2 */ 2, 5, 8,
/* 1.3 */ 3, 6, 9, );
timing_sense:
defines the output polarity w.r.t. input，3 types of unate

A
(1)positive_unate : BUF；
Y

(2)negative_unate : INV； Y

(3)non_unate : not well defined ;

Y
timing_type: (1) combinational
(2) sequential
/*定义端口ZN的时序信息*/
timing(){
related_pin: "A"; #定义相关输入信号为A
(1) combinational timing_sense: negative_unate； #定义ZN与A反相关
timing_type: combinational; #定义时序类型，为组合逻辑
cell_rise(delay_template_3x3){
index_1("1.1, 1.2, 1,3"); #定义输出信号ZN上升的
index_2("2.1, 2.1, 2.3"); 单元传播延时，index_1是
A 输入信号A的转换时间
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
Z cell_fall(delay_template_3x3){
index_1("1.1, 1.2, 1,3"); #定义输出信号ZN下降的
B index_2("2.1, 2.1, 2.3"); 单元传播延时，index_1是
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } 输入信号A的转换时间
rise_transition(delay_template_3x3){
C Z index_1("1.1, 1.2, 1,3"); #定义与输入信号A相关
N index_2("2.1, 2.1, 2.3"); 的输出信号ZN上升的转换
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } 时间
fall_transition(delay_template_3x3){
index_1("1.1, 1.2, 1,3"); #定义与输入信号A相关
index_2("2.1, 2.1, 2.3"); 的输出信号ZN下降的转换
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } 时间

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 timing_type: (1) conbinational pulse width
(2) sequential

CLK
(2) sequential
setup hold

(1)setup_rising, setup_falling
D
Q D
CLK to D
(2)hold_rising, hold_falling
CL CLK to Q
K CLK to D
(3)rising_edge, falling_edge
Q
CLK to Q

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 /*定义端口D的hold时间*/ /*定义端口Q的时序信息*/
timing(){ pin(Q){
related_pin: "CLK"; #定义相关输入信号为CLK direction:output;
timing_type: hold_rising; #定义CLK的上升沿用于hold时间检 max_fanout:1;
查 fall_constraint(template_3x3){ max_capacitance:0.5;
index_1("1.1, 1.2, 1,3"); #定义输入端口D从高电 max_transiton:1;
index_2("2.1, 2.1, 2.3"); 平转化低电平的hold时间 timing(){
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } related_pin: "CLK"; #定义相关输入信号为
rise_constraint(template_3x3){ CLK
index_1("1.1, 1.2, 1,3"); #定义输入端口D从低电 timing_sense: positive_unate； #定义Q与CLK正相关
index_2("2.1, 2.1, 2.3"); 平转化高电平的hold时间 timing_type: rising_edge; #定义时序类型，为上升
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } 沿
cell_rise(delay_template_3x3){ #定义CLK到Q上升的延迟
index_1("1.1, 1.2, 1,3"); 时间
/*定义端口D的setup时间*/ index_2("2.1, 2.1, 2.3");
timing(){ values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
related_pin: "CLK"; #定义相关输入信号为CLK cell_fall(delay_template_3x3){ #定义CLK到Q下降的延迟
timing_type: setup_rising; #定义CLK的上升沿用于setup时间检 index_1("1.1, 1.2, 1,3"); 时间
查 fall_constraint(template_3x3){ index_2("2.1, 2.1, 2.3");
index_1("1.1, 1.2, 1,3"); #定义输入端口D从高电 values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
index_2("2.1, 2.1, 2.3"); 平转化低电平的setup时间 rise_transition(delay_template_3x3){ #定义输出Q上升的转换
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } index_1("1.1, 1.2, 1,3"); 时间
rise_constraint(template_3x3){ index_2("2.1, 2.1, 2.3");
index_1("1.1, 1.2, 1,3"); #定义输入端口D从低电 values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
index_2("2.1, 2.1, 2.3"); #定义输出Q下降的转换
平转化高电平的setup时间 fall_transition(delay_template_3x3){
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); } 时间
index_1("1.1, 1.2, 1,3");
index_2("2.1, 2.1, 2.3");
values("1 , 4, 7, 2, 5, 8, 3, 6, 9"); }
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• pure capacitive loading
NLDM (non-linear delay model)
vs .
R-C based parasitic
CCS (composite current source) &
ECSM (effective current source models)

Major Differences :
receiver Capa lookup table for different timing arcs
output current instead of voltage

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pin (OUT) { pin (OUT) {
... ...
timing () { timing () {
related_pin : "IN" ; related_pin : "IN" ;
receiver_capacitance1_rise ...
("Lookup_table_4x4") { output_current_fall () {
index_1("0.1, 0.2, 0.3, 0.4"); /* Input vector ("LOOKUP_TABLE_1x1x5") {
transition */ reference_time : 5.06; /* Time of input crossing
index_2("0.01, 0.2, 0.4, 0.8"); /* Output threshold */
capacitance */
values("0.001040 , 0.001072 , 0.001074 , index_1("0.040"); /* Input transition */
0.001075", \ index_2("0.900"); /* Output capacitance */
"0.001148 , 0.001150 , 0.001152 , index_3("5.079e+00, 5.093e+00, 5.152e+00,
0.001153", \ 5.170e+00, 5.352e+00");/* Time values */
"0.001174 , 0.001172 , 0.001172 , /* Output charging current: */
0.001172", \ values("-5.784e-02, -5.980e-02, -5.417e-02,
"0.001174 , 0.001171 , 0.001177 , 0.001174");} -4.257e-02, -2.184e-03");
... }
} ...
... }
} ...
}
...
}

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• Crosstalk Noise (glitch) Modelling - (CCSN Model, propagation,
multiple stages)
propagated_noise_low () {
vector (ccsn_pnlh) {
index_1 ("0.5"); /* Input glitch height */
index_2 ("0.6"); /* Input glitch width */
index_3 ("0.05"); /* Output net capacitance */
index_4 ("0.3, 0.4, 0.5, 0.7"); /* Time */
values ("0.19, 0.23, 0.19, 0.11");

• Power Modelling : active + leakage power (multiple power domain)

pin (Z1) { power (template_2x2) {
... index_1 ("0.1, 0.4"); /* Input transition */
power_down_function : "!VDD + VSS"; index_2 ("0.05, 0.1"); /* Output capacitance */
related_power_pin : VDD; values ( /* 0.05 0.1 */ \
related_ground_pin : VSS; /* 0.1 */ "0.045, 0.050", \
internal_power () { /* 0.4 */ "0.055, 0.056");
related_pin : "A"; }
}
}
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Digital Design Flow Introduction

Mixed Signal ASIC Design Flow

Analog Macro Processing Steps

Analog Macro : Liberty / DB

Analog Macro : LEF (Ant, Abutment, Feedthru)

38
 Cadence: abstract

Scripting is preferred because of its convenience & flexibility!

Virtuoso : lefout is much too simple for a proper backend design!
39
 • Thickness in the cadence pdk tech.db updated!!!

PIN en
DIRECTION INPUT ;
USE ANALOG ;
ANTENNAPARTIALMETALAREA 10.033 LAYER M3 ;
ANTENNAMODEL OXIDE1 ;
ANTENNAGATEAREA 2.21 LAYER M3 ;
ANTENNAMAXAREACAR 6.678281 LAYER M3 ;
PORT
LAYER M3 ;
RECT 181.98 35.92 182.18 36.12 ;
END
END en

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• No 45 degree traces for ANT extraction (virtuoso bug)

• MetalSide Area or Antenna MetalArea

dependent on the ANT rules not the design!
MetalArea

MetalSideArea

41
• Specify antenna fixing option
o setNanoRouteMode -drouteFixAntenna true
o setNanoRouteMode -routeAntennaCellName « my_diode »
o setNanoRouteMode -routeInsertAntennaDiode true

• When you have setup NanoRoute, route your design

Tcl command : routeDesign

42
PIN vref_vcc
DIRECTION INOUT ;
abutment
USE ANALOG ;
SHAPE ABUTMENT ;
ANTENNAPARTIALMETALAREA 8550 LAYER M6 ;
ANTENNAPARTIALMETALAREA 8550 LAYER M7 ;
ANTENNAPARTIALCUTAREA 972 LAYER MV6 ;
ANTENNADIFFAREA 381.6 LAYER M6 ;
ANTENNADIFFAREA 381.6 LAYER M7 ;
ANTENNAMODEL OXIDE1 ;
ANTENNAGATEAREA 93600 LAYER M6 ; feedthru
ANTENNAGATEAREA 93600 LAYER M7 ;
ANTENNAMAXAREACAR 0.451233 LAYER M6 ;
ANTENNAMAXAREACAR 0.547387 LAYER M7 ;
ANTENNAMAXCUTCAR 0.019882 LAYER MV6 ;
PORT

Used in mixed signal floorplan / routing

43