15/11/2023, 15:51 PV Check-CSDN Blog

PV inspection
A small footprint every day Published on 2019-12-05 10:47:30 5.5k reads Collection 132 Likes 5
Classification column: Backend design

Backend design The column contains this content 133 subscriptions 39 articles S

Physical verification is a task that must be done for physical signoff of the chip. Similar to the timing signoff stage, PrimeTime is used for timing clos
Caliber tool produced by Mentor Graphics is currently recognized in the industry. It provides efficient DRC, LVS and ERC solutions. It also supports
and Flatten mode inspection methods, which greatly improves the efficiency of the entire verification process.

DRC check

DRC check means that the tool checks whether the GDS of the current design meets the process production requirements based on the rule file pro
Foundary, such as base layer check, spacing check between metal, spacing check between vias, via enclosure check and metal denstiy. Check etc

If a DRC is found, the tool will mark the corresponding error and also indicate which rule is violated in this place. After users use caliber to check DR
import the DRC results into the PR tool, highlight them, analyze the root causes of such DRCs, and then fix them.

How to use tools to automatically repair digital IC back-end design to achieve physical DRC after winding?

Hierarchical DRC

Through the content sharing of the previous two hierarchical flows, we know that current designs basically follow the hierarchical flow (the chip scale
relatively large, and the signoff cycle can be shortened).

Still using the case shared before, Design A consists of sub-module B, sub-module C and Other Logic. When we complete the implementation of ea
module and the top-level digital backend, we need to merge the GDS of these modules into a Flatten A_merge.gds. Finally, take the merged GDS a
DRC check.

Since the DRC check is not just a check, it can be converged immediately after being modified once. Therefore, if a design has to merge each sub-
a GDS and then run DRC every time, the entire DRC check cycle may be doubled or even more. Therefore, we generally do not use this method in
and mid-term stages of DRC inspection.

So, how can we significantly reduce the DRC check cycle for designs implemented in hierarchical designs?

Think it’s O
pretty good? co
DRC inspection process
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GDS Merge of respective modules

Respective module DRC Check & Fixing

Top-level A only GDS merge (the submodules below do not need to be merged here)

Top A only DRC Check & Fixing

DRC inspection using this method should pay special attention to the following points:

PG for module splicing (Metal’s spacing & Base layer DRC)

Antenna effect of module interface

Teach you to easily play with the antenna effect (Process Antenna Effect)

Methods and means of DRC Fixing

The editor of Wuai IC Community emphasizes again that DRC Fixing must not be done manually. This really should not be your job, it should be the
tool . Things that can be automated should be implemented automatically as much as possible. Especially at the 22nm and below process nodes, s
are several layers of metal on the bottom layer that belong to the double pattern , manual repair of DRC has become unrealistic. Often, manua
DRC will result in more and more repairs.

Add route guide (route blockage)

Adjust the position of the cell

Change VIA type or VIA quantity

If you want to completely get rid of the dilemma of manually repairing DRC, you can check it out on the editor's knowledge planet. If you still have te
confusion, you can also ask questions on the planet.

LVS inspection

The LVS (Layout VS Schematic) check is mainly to check whether the layout (Physical) after automatic placement and routing is consistent with the
(Logic). Many beginners may think that since the PR tool completes the layout and routing itself, the written GDS must be theoretically consistent w
function. Why bother?

Indeed, from the perspective of the APR tool itself, it does not change the original logical function, but only does some optimizations. However, the c
run APR is artificially specified, and the entire PR process is not as beautiful as you think. There are still many problems. manual intervention steps.
example, if you delete some lines in ICC to repair the short, you may open some lines in order to repair the spacing problem of DRC. Once there is
it is obvious that physical and logical do not match, and the LVS check result must be incorrect.

I don’t know if you still remember the method that the editor shared before to ensure that the GDS sent for PR must be LVS clean?

Verify_pg_net (check_pg_connectivity) Think it’s O

pretty good? co
Verify_lvs (check_lvs)
A small footprint e… focus on 5

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Please understand the above two magic weapons clearly and use them skillfully at work.

Hierarchical LVS inspection process

PR tools spit out GDS and Netlist

In the LVS data preparation stage, after PR completes automatic placement and routing, it needs to write out the designed GDS and Netlist. Specia
needs to be paid when writing netlist. For example, physical only cell does not need to be written out.

Organize Hcell list

In general, for the convenience of LVS checking and debugging, we strongly recommend using HCELL for LVS comparison. This hcell list mainly co
cells with devices, which can be obtained by writing a small script in the PR tool.

MergeGDS

The Merge GDS here needs to merge both sub-modules A and B into a whole GDS, unlike when running Hierarchical DRC, you do not need to mer
modules below. This requires special attention.

Create_text

Before LVS, you need to label the GDS of the design with text, mainly to label the power net groud net with the corresponding net name. For power
design, sometimes it is necessary to text the local power net, depending on the situation. This step of typing text can be done in either PR tools or c

V2LVS

The netlist spit out by PR is the gate level netlist, and the data input netlist required by caliber LVS must be in spice format, so it needs to be conver
v2lvs provided by the caliber tool.

It is worth mentioning that in hierarchical design, the signals at the module interface may have inconsistent bit width order. For example, for an eigh
signal, the sub-module may be from 0-7, while the top-level call may be from 1-7. When encountering this situation, you need to bring the -l option
read the netlist of the submodule when converting the spice netlist.

Extract GDS

The essence of LVS check is to compare two netlists, so the netlist of the design's GDS needs to be extracted, which often takes a lot of time. In ord
improve work efficiency, the same GDS only needs to extract the netlist once, and subsequent LVS comparisons only need to use the extracted net

Netlist comparison

Compare the netlist extracted by GDS with the spice netlist converted by v2lvs. For hierarchical LVS comparison, you also need to set bbox for sub
and B. In this way, when the tool does LVS inspection, it only checks the submodules and top-level interfaces, and does not trace into the interior of
submodule, which greatly saves LVS. check the time.

Regardless of DRC check or LVS check, it is recommended that you develop the method of using scripts to check, instead of still using the GUI inte
operate. Every time I see many people using GUI to operate, I feel anxious for them. Why do you have to click with the mouse every time when som
be automated? The detailed scripts for create text, Merge GDS, DRC and LVS checks used in this article can be found on Knowledge Planet.

ERC check

ERC inspection mainly checks the electrical performance of the layout, such as whether the substrate is correctly connected to the power supply or
whether the gate is floating, etc. To put it more straightforwardly, it is to check whether there is floating input in the circuit. Do you still remember the
script for checking input floating that the editor shared on Knowledge Planet before? That script is to check the input floating of the gate level. For ex
an input terminal of the NAND gate is floating, it can be reported directly through this script. The ERC check is an input floating check at the device
can understand it as an input floating check at the GDS flatten level .

The checking rules of ERC are quite complicated. Generally, the rule file provided by foundary is relatively general. In actual projects, many false er
often reported, such as tie high and tie low cells reporting ERC errors. Therefore, in order to debug ERC problems more efficiently, you need to cha
file according to your own needs, and then run ERC. Otherwise, there will be too many false errors in ERC and it will be difficult to locate the real pr

PV MPPT simulation Think it’s O

PV maximum power tracking simulation, using boost circuit. matlab 2016a version can run. pretty good? co
A small footprint e… focus on 5
caliber simple usage process

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Detailed description of the drc and lvs process of the circuit for caliber

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