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Design and analysis of FPGA based 32 bit ALU using reversible gates

Conference Paper · April 2017

DOI: 10.1109/ICEICE.2017.8191959

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2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)

Design and Analysis of FPGA Based 32 Bit

ALU Using Reversible Gates
S.M.Swamynathan[1], V.Banumathi[2],
Dept. of ECE, Dept. of ECE,
SNS College of Technology, Anna University Regional Centre,
Coimbatore. India Coimbatore. India
mmsuresh6@gmail.com v_bhanu02@yahoo.com

Abstract— An Arithmetic logic Unit (ALU) is used in
arithmetic, logical function in all processor. It is also
an important subsystem in digital system design.
Arithmetic Logic Unit (ALU) is one of the most
important components of any system and is used in
many appliances like calculators, cell phones, and
computers .A 32-bit ALU was designed using Verilog
HDL with the logical gates such as AND and OR for
each one bit ALU circuit. The design was
implemented in Xilinx. It can work fast than the ALU
processor using less power. The design of an ALU and
a Cache memory for use in a high performance
processor was examined. Reversible logic vital in
recent years because it has ability to reduce the
power dissipation which is main requirement in low
power design. ALU which are designed using non
reversible logic gates consume more power. So there
is a need for lesser power consumption and the
reversible logic has been playing vital role during
recent years for low power VLSI Design techniques.
This technique helps in reducing power consumption
and power dissipation. This paper presents an
implementation of ALU based on reversible logic
while comparing it to an ALU architecture with the
normal logic gates. All the modules are simulated in
modelsim SE 6.4c and synthesised using Xilinx ISE
14.5. ALU which is designed using non reversible
logic gates consume more power of about 0.312 mw
and the implementation of ALU based on reversible
logic reduces the power consumption during
operations to about 5.1 percentages.
Keywords—Reversible gate, Verilog Hardware
Description Language, Feynman gate, Peres
gate, Toffoli gate, Fredkin gate, Arithmetic
Logic Unit.
I. INTRODUCTION
of this work is to address the design of the
functional blocks. An Arithmetic Logical Unit is
the very important subsystem in the digital system
design. It is an integral part of a computer
processor and a combinational logic unit that
performs its arithmetic and logic operations. ALUs
of various fixed bit-widths and full precision bit
width are frequently required in very large-scale
integrated circuits (VLSI) from processors to
application specific integrated circuits (ASICs).
nowadays ALU is getting smaller and more
complex to enable the development of a more
powerful but smaller computer and processors. The
need for high speed, less power consumption and
compatible processors has been increasing as a
result of computer, digital signal processing and
networking applications. Arithmetic operations
such as multiplication, addition, division and
subtraction and logical operations such as AND,
OR,NOT,XOR are using all type of processors
used in various applications.
II. ALU WITH IRREVERSIBLE LOGIC
GATES
The 16 bit ALU is designed which allows the
computer to add, subtract, multiplication and
division and to perform basic logical operations
such as AND, OR, XOR, XNOR, NAND and
inverter etc. Since every computer needs to be able
to do these functions, they are always included in a
CPU these functions. An ALU is a combinational
logic circuit that can have more inputs and only one
output.

Due to wide spread use of microprocessors and

signal processors, implementation of high
performance arithmetic hardware has always
remained an attractive design problem. Arithmetic
and Logic Unit (ALU) is the workhorse of
microprocessors and determines the speed of
operation of the processor. All modern processors
include stand alone hardware for computation of
basic arithmetic operations. In addition to fast
arithmetic hardware, processors are also equipped
with on-chip memory (cache) to achieve significant
performance improvement by avoiding delay due to
data access from main memory. The key objective
2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)
Fig. 1 Functional diagram of ALU architecture
A low power 16 bit ALU is designed using
Verilog HDL. Verilog HDL is an industry standard
language for the description, modelling and
synthesis or simulate of digital circuits and
systems.
Fig. 2 Functional block diagram of one bit ALU
Addition is the most commonly used
arithmetic operation and hence the performance of
an ALU is greatly dependent on the performance of
its adder. A variety of choices exists for addition
depending on speed and area requirements.
Table 1 Function of 1-bit ALU
S1 S0 FUNCTION
0 0 xi OR yi ORci-1
0 1 xi AND yi
1 0 xi OR yi
1 1 xi
Basically AND operation is performed
using an AND gate, the OR operation is performed
using an OR gate and the addition of two numbers
is carried out by the one bit full adder circuit as
shown in fig 2. A One Bit ALU will perform AND,
OR, and ADD operations as shown in the table
above.
III. ALU WITH REVERSIBLE GATES
In ALU architecture, a high performance
arithmetic hardware with minimum possible clock
cycles capable of computing square, square root
and inverse in addition to basic arithmetic
operations. Design of ALU was undertaken in this
thesis in the context of high performance and
testability. Architectures with high degree of
parallelism were explored for design of high speed
arithmetic unit. For simplicity, functional units
were designed with 8 bit capability. Due to
architectural parallelism, increase in operand size
would only require replication of hardware parallel
to existing circuitry. The ALU has stand alone
hardware for performing basic integer arithmetic
operations and is capable of computing square,
square root and inverse as well. A logic unit
performing 8 bit logic operations was built using
logic cells available in the IC cell library and was
found to have a high operating frequency close to
1GHz. Hardware for addition and subtraction was
implemented as a combined ADD/SUB unit.
Subtraction is generally performed using two’s
complement addition. Two’s complement of a
number is obtained by negation of the operand
followed by an increment-by-1. The XOR gate
inverts the other input if the CTRL input is ‘High’.
The CTRL signal is applied to Cin to perform the
increment needed to complete two’s complement
calculation. When CTRL signal is ‘Low’, the unit
performs addition.
A) FEYNMAN Gate
Feynman gate is also known as 2X2 reversible
gate. The input and output vectors for Feynman
gate is In (A, B) and Out (P, Q) respectively. The
outputs of FEYMAN gate are denoted as P=A,
Q=A XOR B and Quantum cost of a Feynman gate
is one. The application of this gate is used in many
circuits because of low cost of the FEYMAN gates
2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)

Fig. 3 Feynman Gate Fig. 7 Fredkin gate

B) PERES Gate IV. SIMULATION OUTPUT

It is also called as 3X3 reversible gate. The
input and output vector for PERES gate is In (A, B,
C) and Out (P, Q, R) respectively. The output is
defined as P = A, Q = A XOR B and R=AB XOR
C and the Quantum cost of Peres gate is 4. Because
of its lowest quantum cost in many designs Peres
gate is used. half adder is designed by Single Peres
gate .
A. ALU using logical gates
The figure 8 shows the arithmetic operations. The
Control inputs for these operations are M = ‘0’ and
Cin= ‘1’ and output is F and Cout. The Figure 10
shows logical operations. The control inputs for
these operations are M = ‘1’ and Cin= ‘0’ and
outputs are F and Cout.

Fig. 4 Peres gate

C) TOFFOLI Gate

Let IPv and OPv be the input and output

vector of a 3*3 Toffoli Gate (TG) respectively, Fig 8 Output wave form of irreversible gate ALU
where IPv =(A, B, C) and OPv=(P=A, Q=B,
R=AB⊕ C). Fig 6 shows the 3*3 Toffoli gate. B. ALU using reversible gates
(Quantum Cost = 5).
Fig 9 shows the output waveform
configuration of 16 bit irreversible
adder/subtractor. The 16bit data A, B are the
module inputs and M is a control signal. If the
control input is “0‟, the addition operation is
performed and if the control input is “1‟
subtraction operation is taken. “Cin‟ indicates the
carry in, “Cout” indicates the carry out or borrow
out obtained from the circuit.

Fig. 6 Toffoli gate

D) FREDKIN Gate:

Let us consider IPv and OPv be the input and

output vector of a 3*3 Fredkin Gate respectively,
where IPv=(A,B,C) and OPv=(X=A,Y=A’B XOR
AC , Z=A’C XOR AB). Fig 7 shows the Functional
block diagram of 3*3 Fredkin gate. (Quantum Cost
= 5)
2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)
Fig. 9 Output wave form of irreversible gate ALU
C. Results and Discussion
One of the low power technique,
Reversible logic gates are used to reduce the power
dissipation as compared to irreversible logic gates.
ALU which is designed using non reversible logic
gates consume more power of about 0.312 mw and
the implementation of ALU based on reversible
logic reduces the power consumption during
operations to about 5.1% as shown in table below.
Table 2 Comparison of Delay and Power
METHODS DELAY POWER
(ns) DISSIPATION
(mw)
ALU using 2.266 0.312
irreversible gates
ALU using 1.907 0.261
Reversible gates
V. CONCLUSION
The design has been able to achieve best
power inflation over the past work in the same
field.Also delay, power dissipation is compared
between reversible and irreversible gates. The total
area of FPGA which is used just 7 percentage of
the complete area. Thus the design is upgraded to
less amount of chip area When comparing
irreversible gate logic delay has been decreasing
from 2.266ns to 1.907ns also power dissipation is
reducing from 0.312mw to 0.261mw.
VI. FUTURE ENHANCEMENT
Future work in this paper may extend to
include pipelined reconfigurable FPGA architecture
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of RISC, which will increase the speed of the
processor. The paper may also be expanded by
making it application specific integrated circuit.
The delay generated by using irreversible logic gate
has decreased drastically as the bit size increased in
the input side in compare with normal logic gates.
The implementation and design using different
FPGA families can also be done as a future work.
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