IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO.
8, AUGUST 2010
ADC Static Characterization Using
Nonlinear Ramp Signal
Santosh C. Vora and L. Satish, Senior Member, IEEE
Abstract—Static characteristics of an analog-to-digital con-
verter (ADC) can be directly determined from the histogram-
based quasi-static approach by measuring the ADC output when
excited by an ideal ramp/triangular signal of sufficiently low
frequency. This approach requires only a fraction of time com-
pared to the conventional dc voltage test, is straightforward, is
easy to implement, and, in principle, is an accepted method as
per the revised IEEE 1057. However, the only drawback is that
ramp signal sources are not ideal. Thus, the nonlinearity present
in the ramp signal gets superimposed on the measured ADC
characteristics, which renders them, as such, unusable. In recent
years, some solutions have been proposed to alleviate this problem
by devising means to eliminate the contribution of signal source
nonlinearity. Alternatively, a straightforward step would be to get
rid of the ramp signal nonlinearity before it is applied to the ADC.
Driven by this logic, this paper describes a simple method about
using a nonlinear ramp signal, but yet causing little influence on
the measured ADC static characteristics. Such a thing is possible
because even in a nonideal ramp, there exist regions or segments
that are nearly linear. Therefore, the task, essentially, is to identify
these near-linear regions in a given source and employ them
to test the ADC, with a suitable amplitude to match the ADC
full-scale voltage range. Implementation of this method reveals
that a significant reduction in the influence of source nonlinearity
can be achieved. Simulation and experimental results on 8- and
10-bit ADCs are presented to demonstrate its applicability.
Index Terms—Analog-to-digital converter (ADC) static charac-
teristics, ADC testing, best segment identification, nonlinear ramp,
quasi-static histogram testing, ramp testing.
I. I NTRODUCTION
T HE RESOLUTION and speed of analog-to-digital con-
verters (ADC) are constantly increasing due to advances
in very large scale integration design techniques, manufactur-
ing, and newer architectures. It is well recognized that perfor-
mance of even the best available high-speed high-resolution
ADC is known to decline when acquiring fast-rising high-
frequency nonrepetitive signals. Errors arising due to a lowered
ADC performance can tend to be unacceptable, particularly
when higher accuracies have to be achieved, e.g., when the
ADC is a part of a reference measuring system and/or during
calibration activities. Static and dynamic nonlinearities of the
ADC are accepted indices that assist in the evaluation of
Manuscript received May 15, 2009; revised August 8, 2009; accepted
August 12, 2009. Date of publication October 16, 2009; date of current version
July 14, 2010. The Associate Editor coordinating the review process for this
paper was Dr. Dario Petri.
The authors are with the High Voltage Laboratory, Department of Electri-
cal Engineering, Indian Institute of Science (IISc), Bangalore 560012, India
(e-mail: santoshvora@yahoo.com; satish@hve.iisc.ernet.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2009.2031852
0018-9456/$26.00 © 2009 IEEE
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2115
performance and to ascertain suitability of ADCs for use in such
environments.
Literature reveals that estimation of static nonlinearity char-
acteristic by conventional dc test [1]–[3] involves 6–9 h for a
12-bit ADC. Undoubtedly, this much test time is prohibitively
high, and in fact, it becomes unrealistic to test ADCs with more
than 12 bits. Therefore, there arises a need to reduce static test
time. This paradox attracted the attention of standardization
committees, and the outcome is evident in the IEEE 1057-
2007 [1]. Specifically with a view to reduce static test time,
this standard, in addition to the conventional dc test method,
now permits the use of triangle-based histogram methods for
static testing of ADCs. Although, overall testing time has been
significantly reduced with this inclusion, the attention now
shifts to tackling the issue of nonlinearity contribution from
the input signal. This is a bottleneck, and it affects the ADC
results. Therefore, it is imperative that newer methods that not
only reduce overall time of static test, but also can overcome
the effects of source nonlinearity on the measured ADC results
are devised.
II. R EVISED IEEE 1057-2007 AND M OTIVATION
There is no doubt whatsoever that evaluation of static char-
acteristics of high-resolution ADCs has to be accomplished by
the quasi-static histogram-based method using a ramp signal
excitation possessing a nonlinearity of less than one least
significant bit (LSB) [4]. As per definition, ramp nonlinearity is
the maximum deviation of the input excitation with reference
to the ideal ramp of the same amplitude and is quantified
as a percentage [4]. The presence of any linearity error in
the excitation automatically gets carried forward and appears
as an equivalent error in the measured ADC characteristics,
significantly affecting its shape and magnitude. Separation of
the error contribution due to source nonlinearity from the actual
ADC errors is certainly not a trivial issue.
The histogram-based static testing of high-resolution ADCs
necessitates a source, which can produce a highly linear spec-
trally pure stable low-noise ramp/triangular signal [5]. As a
matter of fact, signal sources satisfying these stringent require-
ments may not be easily available (and even if available, they
would be expensive) to test such high-resolution ADCs. For
example, to test a 16-bit ADC with an accuracy of 1/4 LSB,
a source with a resolution of at least 18 bits and a linearity
error better than 0.0015% is needed. In contrast, commercially
available analog ramp sources possess a linearity error of 0.1%
[6] and a 16-bit digital source comes with an error of 0.0015%
[7]. Thus, sources satisfying required specifications are hard to
2116 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010
find, if not impossible. Therefore, some relaxations must be
permissible so that available nonideal sources could be used,
of course, with suitable mechanisms to eliminate source error
contributions from the measured ADC characteristics.
Most probably, as a direct consequence of taking this mat-
ter into consideration, the revised IEEE 1057 includes three
methods based on triangular wave excitation, depending on
the resolution of the ADC under test and the accuracy of
the triangle/ramp signal available. Individually, each of these
methods has demonstrated its ability to significantly reduce test
time. Further, the estimated ADC characteristics using these
methods are in good agreement with those obtained from dc
test. Perhaps, the only matter of concern is that every ramp
application covers only a few code bins. Hence, the number of
ramp applications and the overall test time may tend to become
high with an increase in ADC resolution.
Therefore, in summary, it is evident that although ramp-
signal-based characterization is the most appropriate for high-
resolution ADCs, the presence of ramp nonlinearity is the main
issue that needs to be resolved. Fortunately, from a study of
the analytical models of ramp signals reported in the literature
and based on actual measurements by authors on a few signal
sources, it emerges that there exist particular regions or seg-
ments of a nonideal ramp that are nearly linear compared to the
entire ramp. Hence, identifying and utilizing the “most linear”
segment of the ramp to estimate static characteristics appears to
be encouraging and worthy of further consideration.
III. L ITERATURE
Ever since the standards included the conventional dc-based
test, it was quite obvious that the overall time for a static test
was going to be very high for high-resolution ADCs. Search
for alleviating this problem began and led to the following
alternatives, which were, in principle, adhering to the main
philosophy of the dc test, but were innovative and reduced
total test time. Nevertheless, the reduction achieved was not
sufficient enough. In this context, particular mention must be
made about the following methods: 1) the servo-loop-based
method [8]; 2) variable step-size estimation using extrapolated
convergence factor algorithm [9]; 3) small triangular signal
method [10]; and 4) the authors’ method based on a staircase
signal [11]. As a matter of fact, the superiority demonstrated
by the triangular/ramp-based methods has been instrumental
in their inclusion into the standard [1], and a brief summary
emphasizing their ideas is included.
• A method proposed in [7] exploits the noise property of
ADCs and employs an imperfect ramp with a resolution
of about one standard deviation of ADC equivalent noise.
In this method, every ramp application covers a few code
bins. The signal ramps up the discrete steps to cover the
full-scale (FS) range of the ADC. A histogram of the
output codes is generated, and the transfer characteristic
is extracted from the resultant response.
• The quasi-static histogram-based ramp vernier test [10],
[12] is now one of the three standard methods [1]. It
employs small-amplitude triangular signals with accurate
dc biases to achieve reduction in ramp nonlinearity. This
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method permits the use of low-linearity ramp sources, and
the reduced slope gives rise to nearly static test conditions
and uniformly stimulates code bins.
• An algorithm is proposed to identify the stimulus error
and remove it accurately from the output data to estimate
ADC nonlinearity [13], employing two functionally re-
lated excitations. It is an accurate full-code test suitable
for production line tests and offers BIST capabilities.
• In [6], a unified error model based on triangular excitation
is proposed. Determination of the model parameters with
sufficient accuracy can be achieved. The histogram proce-
dures employed are different and utilize signal processing
algorithms to meet the source accuracy requirements.
In summary, it is evident that the ramp signal nonlinear-
ity undermines the estimation of actual static characteristic
of the ADC under test. It becomes imperative to attempt
removal/reduction of source nonlinearity contribution before it
is applied to the ADC or employ postprocessing techniques
to eliminate it from the ADC output data. Adopting the for-
mer option, this paper attempts a simple solution wherein a
ramp source having about 10–12 times more than the specified
nonlinearity could still be employed. Basically, the concept
is to make the ADC to “see” the most linear part of the
nonlinear ramp and then estimate static characteristics by the
conventional histogram-based test procedures.
IV. C ONCEPT
The principle of the proposed method depends on the follow-
ing two basic facts.
1) The percentage linearity of the ramp/triangle waveform
remains practically unaltered irrespective of its ampli-
tude [4]. This implies that the ramp/triangular waveform
amplitude can be increased or decreased without signifi-
cantly affecting the percentage nonlinearity of the signal.
This fact is verified (and found to be true) for a signal
source, whose result is presented later.
2) A nonlinear ramp waveform can be thought of as a
curve, which can be approximated by a number of short
segments of different lengths. It can easily be visualized
that some of these segments can be much more linear (in
a local sense), compared to the entire curve. Utilizing
this important concept, the most linear segment of the
nonlinear ramp is to be determined. Once such a segment
is identified, its amplitude is suitably altered to match
the FS voltage (FSV) range of the ADC to be tested.
Finally, the ramp signal is provided with an appropriate
dc bias/offset to ensure that only the most linear segment
of the ramp will be “seen” by the ADC. This is exactly
what is required to measure the static characteristics. As
the ramp amplitude is higher than the ADC FS range,
the ADC converts only the most linear part of the ramp
waveform that falls within its voltage range, while the
remaining parts (lying outside the voltage range) are
clipped and, later, discarded.
Analysis of models for source nonlinearity existing in literature
reveals that certain segments of the ramp could, in fact, be
VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL
Fig. 1. Nonlinear ramp and its nonlinearity considering the FS signal com-
pared to that due to a segment. The reduction in % NL is evident.
more linear than the entire ramp. (Note: In some models, the
opposite can also be true, i.e., some segments can possess
higher nonlinearity than the entire waveform.) Fig. 1 depicts
this basic idea. From the figure, it is evident that considering
the entire waveform yields a nonlinearity of p%, whereas an
arbitrarily chosen segment has only a small fraction of p%
nonlinearity.
The amount of overdrive to be used is an important parameter
to be selected in an FS ramp-based histogram testing. The
overdrive requirement in a ramp signal is preferred mainly to
minimize the bias error caused by input-equivalent noise. An
overdrive also helps in avoiding influence of high nonlinearity
at the discontinuity. An overdrive, in most cases, equivalent to
three standard deviation of input equivalent noise is found to
be sufficient. Further details can be found in [14]. However,
in the proposed method, only a part of the ramp (i.e., a ramp-
segment) is being used as the input to the ADC. Parts of the
ramp signal above and below the selected segment are automat-
ically clipped. Hence, the need for the overdrive is eliminated,
unless the best segment is located at the extreme ends of
the ramp.
A. Best Segment Identification
Generate a low-frequency ramp signal (about 10 Hz or less)
with an amplitude equal to N times the ADC input voltage
setting Vfs . Typically, N can be chosen as 2 or more, de-
pending on signal source capabilities. To determine the most
linear segment (based on its percentage nonlinearity in a local
sense) of the source output voltage Vs (i.e., N ∗ Vfs ), it is
necessary to scan the entire ramp signal for a selected segment
length. One simple way is to select a segment length such
that it exactly covers the ADC input voltage range. This is a
convenient choice, as this will excite all the ADC bins in a
single application. To begin with, let m overlapping segments
be chosen to scan the entire ramp signal. The number of
segments (m) considered for identification of the best segment
is dictated by the overlapping desired. A larger value of m leads
to a higher identification time, and hence, initially selecting
m to 11 was found convenient. The next task is to mea-
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2117
sure the segment linearity, and the following possibilities are
included:
1) measuring the ramp generator values using a precision
instrument during a calibration cycle and assumed to be
known to an appropriate absolute accuracy [7];
2) using a high-accuracy high-resolution sampling oscillo-
scope or a data acquisition board;
3) obtaining the histogram-based static characteristics of
the ADC for every segment of the imperfect ramp and
comparing the segment-wise integral nonlinearity (INL)
with the conventional dc-based static INL (i.e., true INL)
obtained for the same ADC, thus establishing nonlinear-
ity of each segment, from which best segment can be
identified.
The identified best segment, for a fixed N and ADC FS
range, can be used for the future static testing of other ADCs.
The actual procedure adopted for the identification of the best
segment is described in Section VII. A ramp signal with an
appropriate dc offset will produce a particular segment at the
ADC input. For a bipolar ADC, the dc offset Ci for the ith
segment is given as follows:
 
2(i − 1)
Ci = Vfs × (N − 1)× − 1 , i = 1, . . . , m (1)
m−1
where segment count starts from the positive peak and goes
down the ramp.
Fig. 2 depicts the difference between the conventional FS
ramp testing and the proposed method. Fig. 2(a) shows the
conventional FS ramp testing, where the signal source output
voltage (with small overdrive) is the same as the ADC FS range.
As opposed to this, in the proposed case, the ratio of source
voltage output and the ADC input range (N = 4) is shown
in Fig. 2(b). The ADC captures only a segment of the ramp
that is within its vertical range (Fig. 2b), while the waveform
outside this range gets clipped. Data points corresponding to
the “linear” portion are gathered to build the histogram, while
those corresponding to the “clipped” regions are discarded.
V. S IMULATION —D ETAILS AND R ESULTS
Simulations were performed for three nonlinear ramp models
available in the literature [4], [6], [12] for different ADC
resolutions and percentage nonlinearities. For brevity, results
are presented for 12-bit ADCs. The ADCs are modeled by
confining its static INL (chosen randomly) to lie within ±0.5%
of the FSV or equivalent LSB. Further, this range of static
INL happens to be the prescribed limit recommended for a
digital impulse waveform recorder to be used in an approved
measuring system [2]. The source models along with their
maximum nonlinearity for producing a 1-V ramp signal is given
as follows:
x1 (t) = t1.03 or t0.97 (1.09%NL)[4] (2)
x2 (t) = tp + tq (p = 0.8, q = 1.2, 1.1%NL, scaled)[6] (3)
x3 (t) = t + 0.04 ∗ (t2.0 − t) (1.00%NL)[12] (4)
By definition, the nonlinearity of a segment (or FS signal) is the
maximum deviation of the segment (or FS signal) with respect
2118 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010

Fig. 2. (a) Conventional FS ramp testing. (b) Principle of the proposed method. (Note: Signal source amplitudes for FS range and proposed method are different.)

Fig. 3. Nonlinear ramp signals (exaggerated for the sake of clarity), position of maximum nonlinearity, and best segment are marked for the models described
by (a) (2), (b) (3), and (c) (4).

to an ideal ramp of the same amplitude [4]. Fig. 3 depicts
the output signal produced due to the above three models,
respectively, together with the ideal ramp and maximum non-
linearity (vertical lines) marked. The best segment identified is
also marked with a thick line in Fig. 3(a) and (b). Particular
attention must be paid to their individual shapes, nonlinearities,
and locations as well.
All the three models output a ramp signal whose amplitude
is four times (N = 4) the ADC input voltage range, and the
segment amplitude equal to ADC voltage range is selected. It is
now required to examine which segment of the nonlinear ramp,
in each model, is the most linear. The value of nonlinearity
considering the entire ramp (FS) and for different positions of
the segment along the ramp are determined and plotted in Fig. 4
(starting by initially aligning the segment from the positive peak
of the ramp). It is evident from Fig. 4 that, by using the proposed
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method, as much as 90% and 96% reduction in nonlinearity is
achievable for the model in (2) and (3), respectively, whereas
it is 77% in the case of the model represented by (4). Since
each source has its own nonlinearity (value and shape), one
should not attach too much importance to the position of the
best segment with respect to the FS ramp.
In simulation studies, an ideal ramp signal and a nonideal
ramp signal modeled by (2) were used as the excitation for a
simulated ADC. To begin with, maximum nonlinearity of an
input ramp wave was chosen to be 1.09%, which is much higher
than the desired value of 0.024% (corresponding to the 1 LSB
requirement of the 12-bit ADC [4]). The resulting static INL
characteristics are presented in Fig. 5. The INL estimated from
the FS ideal and FS nonlinear ramp is shown in Fig. 5(a), from
which it is evident that the ADC nonlinearity is superimposed
on the concave-shaped source nonlinearity. However, Fig. 5(b)
VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL
Fig. 4. FS and segment-wise percentage nonlinearity of the nonideal ramp
models described by (a) (2), (b) (3), and (c) (4).
Fig. 5. (a) INL characteristics due to FS ideal ramp and FS nonlinear ramp
wave [defined by (2)]. (b) INL characteristics due to FS ideal ramp and best
segment of nonlinear ramp.
demonstrates the outcome due to the proposed technique. Using
the most linear segment [segment 1, as per Fig. 4(a)] of the
nonlinear ramp, the INL estimated is shown in Fig. 5(b) and
compared with the true INL. It is important to note that ΔINL
(ΔINL is the maximum difference between the true and the
estimated INLs [4], [10]) in Fig. 5(a) is 44.6 LSB, confirming
the 1.09% nonlinearity, whereas ΔINL in Fig. 5(b) is just
4.41 LSB (0.107%). It emerges that a reduction of 90% on the
influence of source nonlinearity is achievable, and hence, such
a ramp source with a nonlinearity as high as 0.24% can still be
used to test a 12-bit ADC employing the proposed method.
Next, consider the nonlinear ramp model defined by (3), with
p = 0.9 and q = 1.1 corresponding to a maximum nonlinearity
of 0.271% (or equivalently 11.08 LSB ΔINL). Fig. 6(a) shows
INL characteristics obtained for a different ADC model due to
FS ideal and FS nonlinear ramp, whereas the INL estimated
due to the FS ideal ramp and that due to the best segment
(segment 7) are depicted in Fig. 6(b). The estimated INL when
the best segment is used is almost indistinguishable from that
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2119
Fig. 6. (a) INL characteristics due to FS ideal ramp and FS nonlinear ramp
[defined by (3), with p = 0.9 and q = 1.1]. (b) INL characteristics due to FS
ideal ramp and best segment of nonlinear ramp.
due to the ideal ramp, thus proving the potential of the pro-
posed idea.
The source model corresponding to (4) [Fig. 3(c)], as re-
ported in [12], has an “almost” uniform nonlinearity in all the
segments, as depicted in Fig. 4(c). In such a case, any segment
along the ramp would produce similar results. By raising the
source voltage to six times the ADC input range, an 84% reduc-
tion in nonlinearity became achievable. This is a peculiar case,
and such a source should be avoided, unless the best segment
nonlinearity is less than 1 LSB of the ADC. However, for
real sources, in general, the source contribution to nonlinearity
can be further reduced by raising the source amplitude and/or
reducing the ADC input range setting by selecting shorter
segment lengths.
VI. E XPERIMENTAL D ETAILS
The proposed technique was validated for three ADCs [two
8-bit digital storage oscilloscopes and a 10-bit real-time digi-
tizer (RTD)] using a 12-bit arbitrary waveform generator. The
devices were computer controlled over GPIB and programs
were coded in VEE Pro. The INL obtained for every device
under test (DUT) using the proposed test was compared with
that obtained by a conventional dc-based static test.
For testing of 8-bit digital storage oscilloscopes (DSOs) with
an FS ramp, the digital signal source was set to output an
in-built ramp at a frequency of 10.01243398 Hz (fraction of
frequency intentionally used to avoid coherent sampling) with
the voltage amplitude set to 0.25 V, with no offset. The DSOs
were set to operate in 50 mV/div input range with a sampling
frequency of 20 ksamples/s. For implementing the proposed
test, the source voltage amplitude was set to 1.0 V (implying
N = 4).
For a 10-bit ADC FS testing with an FS ramp, the digital
signal source was set to output an in-built ramp at the frequency
of 10 Hz with the voltage amplitude set to 0.5 V, with no offset.
For implementing the proposed method, the source voltage
amplitude was set to 0.8 V (corresponding to N = 1.6). The
RTD was set for a voltage range of 0.5 V and a sampling
interval of 9 μs.
2120 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010

A small overdrive, as suggested in [14], was used while

performing FS ramp testing of ADCs. An appropriate dc offset
was calculated as per (1) for 11 overlapping segments, and each
segment amplitude was set equal to the ADC input range in
all the tests. The number of sample required to maintain the
accuracy level (to avoid code transition level uncertainty due
to noise as suggested by [1]) was met for FS histogram-based
testing, as well as for the proposed testing, after discarding the
clipped portions of the ramp. A minimum of 1024 samples per
code bin were gathered to ensure uncertainty of code transition
level estimate to correspond to 12% of the rms noise level Fig. 7. Percentage nonlinearity estimated for individual ramp segments of the
[1, clauses 4.7.3 and 4.7.10.1.1]. 12-bit signal source.

VII. E XPERIMENTAL R ESULTS

A. Signal Nonlinearity Invariance Verification
The proposed technique exploits one of the basic properties
of signal sources—invariance of the signal nonlinearity with
its amplitude. Hence, linearity testing at various FSV ranges is
necessary. Of the three possibilities mentioned in Section IV-A,
the results reported here are based on possibility #2, viz.
employing an accurate high-resolution sampling oscilloscope.
The sampling oscilloscope used in this case offered a 13-bit
resolution when operated in the high-resolution mode. Select
a nonlinear ramp of frequency fin (e.g., 10.01243398 Hz)
that is slightly offset with the oscilloscope sampling frequency
fs (e.g., 10 Hz). The signal amplitude and the scope vertical
range are set to be equal. Acquiring data with these settings
results in the capture of successive samples on every subsequent Fig. 8. Static INL characteristics of an 8-bit ADC (DSO-1). (a) True INL
ramp cycle. Acquire sufficient samples to form an FS nonlinear and INL due to the FS nonlinear ramp. (b) True INL and INL due to the best
ramp, and construct an ideal ramp using the selected voltage segment of the nonlinear ramp.
range to determine the ramp nonlinearity. The nonlinearity
invariance property was verified for a 12-bit signal source used tion of the ADC. To achieve a similar resolution, N > 4 is not
in this work. The linearity tests for FS ramp inputs were carried feasible for an 8-bit ADC using a 12-bit signal source. Hence,
out for four signal amplitudes, i.e., 200 mV, 800 mV, 2 V, and for the 8-bit DSO testing, the proposed method is employed
4 V at 10 Hz, and nonlinearity was found to be 1.194%, 1.206%, with N = 4. (Note: ADCs have a maximum voltage that can
1.245%, and 1.285%, respectively (results are based on an safely be applied to their inputs without risking damage. As a
average of ten measurements). Assuming the nonlinearity at precaution, when use of larger N is possible, it is recommended
2 V range as reference, the variation in nonlinearity for the to use a limiting circuit at the ADC input as a safeguard.)
tested range is about ±0.04%, which can be considered as The static INL measurements for two 8-bit ADCs are pre-
reasonable for low-precision testing. sented in Figs. 8 and 9, respectively. In Fig. 8(a), static INL
characteristics for DSO-1 obtained by the conventional dc-
B. Segment-Wise Linearity Estimation based test (true INL) and histogram-based FS nonlinear ramp
are compared. It is observed that the ADC characteristic is
The above-described procedure is repeated to determine the
superimposed on the signal source nonlinearity, rendering the
segment-wise nonlinearity, with N = 4, m = 11, oscilloscope
INL results unusable and the source unfit for the testing. The
input range based on N , and signal source frequency and
ΔINL obtained from these data sets is 2.85 LSB, which implies
oscilloscope sampling rate settings as above. The measured
a source nonlinearity of 1.12%. Contrary to this, when the
% NL for these settings is plotted in Fig. 7. It is evident that
identified best segment (segment 2) of the source was used to
segment 2 appears to be the best, and the nonlinearity has been
excite the same ADC, the INL characteristic shown in Fig. 8(b)
reduced to 0.28% which implies a reduction of 77% from its
results. The true INL is also plotted in the same subplot. A
initial value (FS NL of 1.206%). It is evident that the best
good match is seen at majority of the code bins, with ΔINL
segment with a nonlinearity of 0.28% is suitable for static
being 0.6 LSB. Further, the true shape of the INL characteristics
testing of an 8-bit ADC.
and its fine structure are well reproduced. However, the minor
differences in the INL that still exist are due to the presence
C. ADC Static Characterization by the Proposed Method
of the residual nonlinearity in the best segment. Nonlinearity
In conventional static testing of ADCs, the input signal reso- has been significantly reduced but not entirely eliminated. The
lution is expected to be at least four times better than the resolu- time required to complete this test is about 3 min, which is
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VORA AND SATISH: ADC STATIC CHARACTERIZATION USING NONLINEAR RAMP SIGNAL
Fig. 9. Static INL characteristics of an 8-bit ADC (DSO-2). (a) True INL and
INL due to the FS nonlinear ramp. (b) True INL and INL due to best segment
of the nonlinear ramp.
inclusive of source signal generation, sample acquisition by the
ADC, data transfer to a personal computer, and removal of the
clipped portion of the signal. In all, about 1.05 Msamples were
collected, of which 270 000 (∼1/N times) corresponded to the
linear portion and used to construct the histogram.
A necessity was felt to verify the possibility of using the
same best identified segment for another ADC (DSO-2), and the
results are presented in Fig. 9. Again, the effect of nonlinearity
existing in FS ramp is visible in Fig. 9(a), with reference to
the true INL of DSO-2. The identified best ramp segment
was then applied for the determination of static INL, and the
excellent match is evident in Fig. 9(b). It thus proves the claim
of the proposed method. The shape of the INL is preserved,
and the INL values are very close to the true values. A minor
influence of the residual nonlinearity of the best segment is still
perceivable in the results.
The proposed concept was next examined for a 10-bit ADC
using the same 12-bit signal source. Obviously, N in this case
cannot exceed 1 for reasons discussed earlier. A large N will
result in a large number of hits for certain bins, which is
undesirable. As a compromise to avoid this phenomena and yet
examine the applicability of the method, N = 1.6 was selected
for 10-bit ADC characterization, letting the source to be just
2.5 times better than the DUT. The best segment identification
was reworked for the desired ADC input range, and segment 1
emerged as the best segment. This shows that the best segment
location does not significantly change with variations in N . The
results are presented in Fig. 10. A considerable influence of
the existing nonlinearity of the FS ramp (indicating N = 1)
on the ADC INL is observed in Fig. 10(a). The ΔINL of
11.6 LSB, again, proves the source nonlinearity of 1.1%.
Testing the ADC with the best segment (segment 1) results
in the static INL shown in Fig. 10(b). In this particular case,
1.7 Msamples were acquired, of which 1 050 000 corresponded
to the best segment and were used to build the histogram. The
reduction in the ramp nonlinearity influence is evident, while
ΔINL is 2.35 LSB, indicating a nonlinearity of 0.23%. The
large variations observed at certain code bins in Fig. 10(b) can
be attributed to the signal and DUT resolution ratio not being
four times or better.
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2121
Fig. 10. Static INL characteristics of a 10-bit ADC (RTD). (a) True INL and
INL due to the FS nonlinear ramp. (b) True INL and INL due to the best
segment of the nonlinear ramp.
The simulation and experimental results prove that a low-
linearity ramp source with an appropriate dc bias can be effec-
tively employed to estimate the static INL characteristics of an
ADC. Some of the related issues are summarized as follows.
• The method proposes to use a low-frequency ramp signal.
However, the change in signal slope when using increased
values of N will not be appreciable since in all the cases, it
will be much less than the device slew rate, thus ensuring
“static-ness” of the test.
• The method excites all the ADC code bins in a single
application when the segment length spans a voltage that
is same as the ADC input voltage range. The sample
requirement and, hence, the test time, is N times the
number of samples required by FS ramp and remains
constant, irrespective of the ADC resolution. It indicates
that the method is time efficient compared to the other
histogram-based ramp test techniques.
• The choice of N is governed by the resolutions of the
source and the ADC, or in other words, digital sources
with a resolution better by at least 3 bits is preferred.
Furthermore, with a greater value of N , subject to the
source capability, the segment linearity is expected to
improve.
• Once the best segment is identified, acquisition of a large
number of samples is the only component that involves
time since the proposal does not necessitate any major post
processing.
VIII. C ONCLUSION
A simple and effective method has been described by which
a nonideal low-frequency ramp generator possessing more than
the stipulated nonlinearity could still be employed to test an
ADC for estimating its static characteristics. Normally, a source
must have a nonlinearity of less than 1 LSB to qualify for use
in such tests. However, by employing the proposed method,
a significant reduction in source nonlinearity accrues, thereby
rendering it usable. The basic idea is to identify and use only
the most linear segment/region of the nonlinear ramp to test the
2122 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 8, AUGUST 2010
ADC, and a simple procedure for its identification is discussed.
In summary, the proposed approach is not only time efficient,
but also excites all the ADC code bins in a single application,
involves very little post processing, and is capable of addressing
issues concerning source nonlinearity to an acceptable extent.
Experimental results on two 8-bit and one 10-bit ADCs demon-
strate the applicability of the approach.
R EFERENCES
[1] Standard for Digitizing Waveform Recorders, IEEE Standard 1057-2007,
2008.
[2] Instruments and Software Used For Measurements in High-Voltage Im-
pulse Tests—Part 1: Requirements for Instruments, IEC Standard 61083-
1(2001), 2001.
[3] Standard for Terminology and Test Methods for Analog-to-Digital Con-
verters, IEEE Standard 1241-2000, 2001.
[4] F. C. Alegria, “Proposal for high accuracy linearity test of triangular
waveform generators,” in Proc. AFRICON, Sep. 26–28, 2007, pp. 1–5.
[5] T. Kuyel, “Linearity testing issues of analog to digital converters,” in Proc.
Int. Test Conf., 1999, pp. 747–756.
[6] L. Michaeli, J. Saliga, and P. Michalko, “Triangular testing signal for
identification of unified error model parameters,” Measurement, vol. 40,
no. 5, pp. 491–499, Jun. 2007.
[7] S. Max, “Ramp testing of ADC transition levels using finite resolution
ramps,” in Proc. Int. Test Conf., 2001, pp. 495–501.
[8] S. Max, “Fast accurate and complete ADC testing,” in Proc. Int. Test
Conf., 1989, pp. 111–117.
[9] A. Cruz Serra, “A new measurement method for the static test of ADCs,”
Comput. Stand. Interfaces, vol. 22, no. 2, pp. 149–156, Jun. 2000.
[10] F. C. Alegria, P. Arapia, P. Daponte, and A. C. Serra, “An ADC histogram
test based on small-amplitude waves,” Measurement, vol. 31, no. 4,
pp. 271–279, Jun. 2002.
[11] L. Satish, S. C. Vora, and A. K. Sinha, “A time efficient method for de-
termination of static non-linearities of high-speed high-resolution ADCs,”
Measurement, vol. 38, no. 2, pp. 77–88, Sep. 2005.
[12] F. Alegria, P. Arpaia, A. Cruz Serra, and P. Daponte, “Performance analy-
sis of an ADC histogram test using small triangular waves,” IEEE Trans.
Instrum. Meas., vol. 51, no. 4, pp. 723–729, Aug. 2002.
Authorized licensed use limited to: NXP Semiconductors. Downloaded on November 09,2023 at 06:14:24 UTC from IEEE Xplore. Restrictions apply.
[13] L. Jin, K. Parthasarathy, T. Kuyel, D. Chen, and R. L. Geiger, “Accurate
testing of analog-to-digital converters using low linearity signals with
stimulus error identification and removal,” IEEE Trans. Instrum. Meas.,
vol. 54, no. 3, pp. 1188–1199, Jun. 2005.
[14] F. Alegria and A. Cruz Serra, “Overdrive in the ramp histogram test
of ADCs,” IEEE Trans. Instrum. Meas., vol. 54, no. 6, pp. 2305–2309,
Dec. 2005.
Santosh C. Vora was born in 1974. He received the
B.E. degree in electrical engineering from Saurashtra
University, Gujarat, India, in 1997, and the M.E.
degree in electrical engineering, with specialization
in high-voltage engineering, from the Indian Insti-
tute of Science (IISc), Bangalore, India, in 2004.
He is currently on deputation from the Institute of
Technology, Nirma University, Ahmedabad, India,
to work toward the Ph.D. degree with the High
Voltage Laboratory, Department of Electrical Engi-
neering, IISc.
His research interests include evaluation of ADC test techniques and high-
voltage measurements related instrumentation and diagnostics.
L. Satish (SM’02) was born in 1964. He received
the Ph.D. degree from the Indian Institute of Science
(IISc), Bangalore, India, in 1993.
He is currently a Professor with the High Voltage
Laboratory, Department of Electrical Engineering,
IISc. His research interests include ADC testing, ap-
plication of signal processing to HV impulse testing,
diagnostics, and condition monitoring.
Dr. Satish is a member of the International Council
on Large Electric Systems (CIGRE) Working Group
D1-33.