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A Practical Self-Calibration Scheme

Implementation for Pipeline ADC
B. Provost

IEEE Transactions on Instrumentation and Measurement

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448 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004

A Practical Self-Calibration Scheme

Implementation for Pipeline ADC
Benoit Provost, Student Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE

Abstract—An efficient pipeline analog-to-digital converter
(ADC) self-calibration implementation is presented. The tech-
nique uses a highly linear on-chip analog ramp generator,
performs a simplified on-chip integral nonlinearity (INL) mea-
surement, and extracts the compensation coefficients. Except for
the ramp generator, the whole calibration is performed in the
digital domain and is done at the nominal ADC speed (at-speed).
The approach does not require any modification to the original
analog section of the ADC. The INL measurement can be carried
off-chip to simplify the production testing or to perform perfor-
mance verification in the application environment. Simulation
and measurement results show an INL improvement of more than
2 bits (from 2.1 LSB to 0.5 LSB).
Index Terms—Analog-digital conversion, analog-to-digital con-
verter (ADC) calibration, pipeline processing.
I. INTRODUCTION
tions. Moreover, the approach involves an on-chip, simplified
computation of the integral nonlinearity (INL) in real-time. The
on-chip INL computation can greatly simplify the production
test of ADCs and allow for simple monitoring of the ADC per-
formance while in the application environment. The approach
has first been validated by calibrating a realistic ADC modeled
by a simulator which includes controls on capacitor mismatch
and noise level.
Section II describes the proposed self-calibration scheme and
defines the performance requirement from the main blocks. Sec-
tion III provides a brief overview of the on-chip ramp-generator
(OCRG) used in the system. Then, the theory behind the coef-
ficient extraction technique is described in Section IV. In Sec-
tion V, the circuit implementation of the digital self-calibration
loop is presented in detail. Section VI shows the experimental
test setup and measurement results. Finally, Section VII gives

W HILE THE demand for high-performance analog-to-

digital converters (ADCs) continues to grow, the
accuracy limit of pipeline ADCs forces the designers to use
the conclusions.

II. SELF-CALIBRATION SCHEME

self-calibration techniques. The matching of analog compo-
The most important source of nonlinearity in pipeline ADCs
nents is the main cause of nonlinearity. Several early approaches
is the capacitor mismatch in the multiplying DAC (MDAC) [6].
proposed to compensate for the capacitor mismatch by using
The MDAC block is usually a switched-capacitor (SC) circuit
a programmable capacitor bank in the sub-digital-to-analog
that implements the functionality of a DAC, an adder and a gain
converters (DACs) [1]. Other techniques correct the analog
stage (Fig. 1) [7]. The capacitor mismatch affects the gain and
mismatch with digital compensation values for each stage
the DAC binary weights. Other sources of nonlinearity include
using the precision provided by all the other stages [2], or only
inter-stage reference mismatch, sub-ADC offsets, opamp gain
the remaining stages [3], [4]. A recent technique uses a precise
bandwidth (GBW) product, finite dc gain and speed-related is-
and slow DAC to compensate for the errors in the ADC under
sues such as clock-feedthrough, charge injection, and settling
calibration [5].
time. The inter-stage reference mismatch can be minimized by
The problem with analog compensation is the deterioration of
proper layout and digital error correction circuit used in all typ-
the analog data path by addition of capacitor banks. Digital com-
ical pipeline ADCs easily compensates for the sub-ADC offsets.
pensation is preferable, but so far, the analysis required to de-
The proposed self-calibration system compensates for the ca-
termine the compensation coefficients was intensive. The tech-
pacitor mismatch and finite opamp dc gain in the MDAC. The
nique used in [4] is simple, but reshuffling the analog stages also
technique does not add to the speed-related problems like charge
means deterioration of the analog data path. Finally, the tech-
injection and clock feedthrough since it is performed at-speed
nique used in [5] necessitates a very precise DAC, which is still
and does not modify in any ways the analog data path of the
process-dependent.
ADC. From this analysis, we conclude that the approach will
In this paper, we propose an approach for digital self-calibra-
improve the performance of any “1-bit mode” or “Lewis mode”
tion of 1 bit per stage pipeline ADCs. No high-frequency per-
pipeline ADC. These modes will be described in Section IV.
formance degradation will result since the technique does not
The general block diagram of the self-calibration system
require any change on the analog blocks and their interconnec-
is shown in Fig. 2. An OCRG first generates a low-slope and
highly linear analog ramp. This is the only analog block in
Manuscript received June 19, 2002; revised November 15, 2003. This work the whole calibration loop. Details on this block will be given
was supported in part by the Texas Instruments Data Converters Group.
B. Provost is with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: in Section III. The analog pipeline, delay lines, and error
benoit.provost@intel.com correction blocks form the original data path of the pipeline
E. Sánchez-Sinencio is with the Analog and Mixed-Signal Center, Texas ADC and are not modified. The remaining blocks form the
A&M University, College Station, TX 77843 USA (e-mail: sanchez@
ee.tamu.edu; http://amesp02.tamu.edu/~sanchez). digital self-calibration loop. First, a simplified INL calculation
Digital Object Identifier 10.1109/TIM.2004.823317 is performed on-chip by the INl built-in (INBI) block, located
0018-9456/04$20.00 © 2004 IEEE
PROVOST AND SÁNCHEZ-SINENCIO: PRACTICAL SELF-CALIBRATION SCHEME IMPLEMENTATION 449

Fig. 1. Analog stage of a 1 bit per stage pipeline ADC.

Fig. 2. Detailed block-diagram of the self-calibration scheme.

in the INl jump (INJU) block. The INJU computes the INL the ramp’s slope from one iteration to the next should result
jumps, which will be used to form the compensation code. in an HPC variation of less than one. In order to set the slope
These blocks will be described in details in Section V. The stability needed from the ramp generator, we need to relate
compensation coefficients are extracted from the INL jumps the slope variations to the HPC variations. Using the relation
supplied by INJU. The digital data going from the delay lines , we relate the slope error to the HPC error
to the error correction is also sent to the compensation block,
after it has been scaled according to the extracted coefficients. (1)
Finally, the compensation code is added to the original data
to produce the corrected digital output code. Only the first where and are the variations on HPC and
three stages are being calibrated to minimize the hardware and slope, respectively. We also have
because the precision limit of the on-chip INL extraction tech-
nique makes the coefficient extraction for subsequent stages
(2)
unreliable. Moreover, the nonlinearity errors of a pipeline ADC
are mostly due to the limitations of the first few stages. where is the error on the final voltage of the ramp in
In order to obtain the required precision on the INL calcu- LSB units, assuming that the starting point does not have any
lations, the input ramp must have a maximum INL defined error. From (1) and (2), we obtain a limit on the offset of the
by , where FSR is the full-scale ramp’s final value necessary to satisfy the specification on the
range of the ADC, is the resolution of the ADC in bits, and HPC variation
HPC is the hit-per-code used in the histogram testing for INL
computation. The HPC represents the number of times the
(3)
same code is obtained at the output of the ADC while the input
ramp is slowly rising. The higher the HPC is, the more precise
In order to obtain the same HPC measurement from one iteration
the INL and other computations will be. For this reason, we set
to the next, should be limited to 0,5. If we assume
the slope of the ramp to a value low enough to obtain an HPC
that , it yields
of at least 16. The self-calibration system will adapt to the exact
value of the input ramp’s slope by computing the real HPC and
taking it into account in the rest of the processing. As will be (4)
described in Section V, the calibration process is performed
in two ramp iterations. Therefore, the relative variations on (5)
450 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004
Fig. 3. Basic principle of the ramp generation.
Fig. 4. Block-diagram of the adaptive approach for precise ramp generation.
where is expressed in voltage units. This expression is
independent from the resolution of the converter under calibra-
tion. Our target ADC is a 10-bit structure with a 0.5-V fully dif-
ferential input (1 V total) range and the typical HPC provided
by the slope of the OCRG is 32. Therefore, the final value offset
should always be less than 15 mV. If the amplitude of the input
ramp is set slightly larger than the input range of the ADC, the
average offset is unimportant, as all the possible codes of the
ADC are hit.
III. ON-CHIP RAMP GENERATOR
This section briefly describes the adaptive OCRG [8] used
in our self-calibration technique and provide its measurement
results. The principle of the basic ramp generator is to charge
a capacitor with a constant current source. In Fig. 3, is
directly proportional to the pulse width of the Step signal ap-
plied to the switch: . analog block is between
To achieve the required performance (linear ramp with small
slope), we need a very low current source with a near infinite
output impedance and a very large capacitor. Both have to be
precise and constant. If we want to use an on-chip ramping
capacitor in the range of 10 pF, the design of the extremely
small current source required to test a typical ADC becomes
a challenge. Moreover, the process variation affecting the abso-
lute value of the current-source and on-chip capacitor ( 20%)
would result in significant slope errors. Fig. 4 shows the con-
ceptual block diagram of the adaptive scheme used to solve this
problem. The advantage of the adaptive approach is that a pre-
cise and process independent current reference is not needed
since the adaptive scheme will automatically generate the proper
value to satisfy the least mean square (LMS) condition. The dis-
crete adaptive calibration procedure is based on two reference
values: the clock signal and a reference voltage used as a target.
The calibration procedure consists of letting the output ramp
during a constant delay (derived from the clock) and then
comparing with the target dc level . The LMS
block uses this information to vary the control voltage
of the current source. This process of ramping and adjusting
the control voltage is repeated until becomes exactly the
same as . A simplified implementation of the LMS block
avoiding multipliers is to make a discrete-time (DT) integration
of the difference between and and apply a gain
that guarantees stability of the adaptive loop
(6)
where is the final voltage obtained at the end of iteration
and is the initial value at the output of the integrator.
The circuit of the adaptive OCRG is shown in Fig. 5. A dif-
ferential current source (self-biased Wilson topology) charges
the capacitors in feedback with an op-amp to increase
linearity. The ramps on and are fully differential.
The final values of the ramps are subtracted from the targets
( and ) and the error is integrated. The accu-
mulated error signal is converted to single-ended and fed back
to the current source as a control signal. The circuit was fabri-
cated with a 0.18- technology from Texas Instruments, using
a single power supply of 1.8 V.
Once calibrated, the ramp goes from 0.7 to 1.3 V in 1.024
ms. The maximum INL of the ramp is 175 V, representing
about 11 bits. This result is mainly limited by measurement
setup accuracy (a 12-bit analog acquisition board from National
Instruments). Post-layout simulations showed a precision of
15 bits. This accuracy satisfies the linearity test requirement of
our target ADC.
IV. COMPENSATION COEFFICIENT EXTRACTION
FROM INL CURVE
The following analysis is a brief overview of the technique
described in [9]. It is based on the pipeline stage transfer curve
shown in Fig. 6(a). Since this is a 1 bit/stage with one bit of re-
dundancy, we will call this transfer curve the “1-bit mode” [7].
The curve is divided into three regions. When the input of the
and , the sub-ADC gen-
erates “00” (region 0). If the input is from and ,
the digital output is “01” (region 1) and if it is between
and , the output is “10” (region 2). The transfer curve pro-
posed by Lewis [10] is much more used in commercial prod-
ucts [Fig. 6(b)]. While the analysis is based on the former tech-
nique, simulation and experimental results show that our tech-
nique works equally well with the latter transfer curve (which
we will call the “Lewis mode”). The actual code at any particular
sample resulting from a conversion by the ADC can be written
as
(7)
where is the number of stages in the ADC, is the actual
region (0, 1, or 2) of the sub-ADC for stage , is the
PROVOST AND SÁNCHEZ-SINENCIO: PRACTICAL SELF-CALIBRATION SCHEME IMPLEMENTATION
Fig. 5. Detailed view of the OCRG.
Fig. 6. Tranfer curve of the analog stage in (a) 1-bit mode and (b) Lewis mode.
digital offset that must be subtracted from the output code after
digital correction when using the “1-bit mode,” and is the
INL of the current output code. The term “actual” is used to
signify that it is affected by nonidealities (gain errors, analog
offsets, dc gain errors, etc.). The INL term is expressed as
(8)
where is a correction coefficient for stage . The goal here
is to find a simple procedure to predict the value of each of the
and then recover the ideal code with
(9)
Fig. 7 shows the large jumps in the INL curve obtained from a
pipeline ADC (with typical gain errors equal on all stages). The
locations of the largest jumps correspond exactly to the transi-
tion locations between each region on the transfer curve of the
first stage. Also, the locations of the second largest jumps cor-
respond exactly to the transition locations between each region
on the transfer curve of the second stage, and so on. When the
input to the first stage makes the transition from region 0 to 1, its
residue will go from to , where and are
errors due to capacitance mismatch. This forces the second stage
to go from region 2 to region 0 and its output residue will be
close to 0 (before and after the transition). Therefore, the output
residues for the next several stages will also be close to 0, both
before and after the transition. From (8), we can compute the
451
difference in INL of the codes just before and just after the first
region transition of the first stage (region 0 to region 1)
(10)
where is the digital output of stage after/before
the transition on the first stage. Furthermore, can be general-
ized as follows:
(11)
where is the stage number. Therefore, we can compute each
stage’s coefficient starting from the last to the first. Since we are
only calibrating the first three stages, the compensation equation
now becomes
(12)
V. CALIBRATION CIRCUITS IMPLEMENTATION
Fig. 8 gives a simplified version of the timing diagram for the
self-calibration system (refer to Fig. 2 for the block diagram).
The jump locations (Jump Locs) are the code values where the
large INL jumps occur in Fig. 7. Initially, the jump locations,
HPC, INL, and coefficients (coeffs) are all unknown (“wrong”
in Fig. 8). Once a “calib” signal is sent by the user, the first ramp
generated and the INL jump locations are registered (“building”).
At the same time, the ramp’s HPC is estimated (both by sub-
blocks in INJU). When the second ramp is generated, the INL is
computed in real-time by INBI and the “coefficient extraction”
block computes the compensation coefficients according to (11).
The calibration process is complete at the end of the second ramp.
At this point, the jump locations, HPC and coefficients are all
right, and the INL is accurately computed for any new data from
the ADC. The coefficients are then applied according to (12) and
a third ramp is input to observe the effect of the compensation.
452 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004
Fig. 7. INL from a typical uncalibrated pipeline ADC.
Fig. 8. Self-calibration timing diagram.
Fig. 9. INJU computation block structure.
A. INL Jump Extraction
The INJU block diagram is shown in Fig. 9. During the first
calibration step, the “jump loc register” detects the location of
each INL jump by monitoring the changes on the Regions and
using windows of expected ranges for each stage. Also, during
the first ramp, the HPC is estimated. The averager (implemented
by a moving average Filter) [11], [12] removes most of the dig-
ital noise present in the data. Four levels of averaging are avail-
able. Level 0 uses a 4-byte window, therefore resulting in a min-
imum filtering. Levels 1, 2, and 3 use windows of 8, 16, 32, and
64 bytes, respectively. During the second calibration step, the
averaged data is sent to the “window” block which generates a
“in-window” signal whenever the code falls within the neigh-
borhood of a registered INL jump, along with a number identi-
fying the INL jump. Meanwhile, the INL of the data is computed
in real-time by the INBI block. The maximum and minimum
INL in the neighborhood of an INL jump and registered and the
INL jump is computed when the data leaves the neighborhood
of the jump. The “jump register” block registers the INL jump
value for each of the ranges stored in the Jump Loc Register and
computes the average INL jump caused by the first, second, and
third stage.
B. HPC Computation
The HPC resulting from the ramp’s slope is estimated by
counting how many hits (clock cycles) were spent between the
detection of the codes number and and dividing
by . Fig. 10 shows a graph depicting the approach. 1
LSB window of acceptability is used around the counter start
and stop detection values to allow for possible missing codes.
Start values of and were used instead of the full
range because nonlinearity often eliminates the first and last few
codes.
C. INL Computation
The INBI block implements a simplified version of the tra-
ditional INL computation typically performed by an external
production tester by computing the INL of the input data in
real-time. Fig. 11 illustrates the approach for the simple case of
6 and Fig. 12 shows the block-diagram of INBI, where
is the maximum HPC allowed (64 in our implementation).
First a counter is incremented at each clock cycle and multiplied
by (“counterx64” in Fig. 12; curve 1 in Fig. 11). The actual
data from the ADC (“data in” in Fig. 12) is also multiplied by
. Since the actual data is incremented every HPC clock cy-
cles and multiplied by (“actual curve,” curve 2), it will be
HPC times lower than counterx64 (ignoring INL on the actual
PROVOST AND SÁNCHEZ-SINENCIO: PRACTICAL SELF-CALIBRATION SCHEME IMPLEMENTATION
Fig. 10. HPC computation graph.
Fig. 11. INL computation approach for the case of HPC = 6.
Fig. 12. INBI (INl built-in) block diagram.
ramp for simplicity). Therefore, we divide counterx64 by HPC
(“ideal curve,” curve 3). The INL of the actual data is obtained
by subtracting the actual curve from the ideal curve whenever
the actual curve shows a new code. An arbitrarily large offset
value of half the total range is added to the ideal curve before
subtraction to ensure that the result will be positive, thereby sim-
plifying the circuitry. This offset has no effect on the final result
since only the difference between two INL values is of interest
453
(the INL jump), thereby eliminating the offset. The result of the
INBI block is the ADC INL multiplied by 64.
The delay caused by the “div by HPC” block is dependent on
the HPC value. Assuming that the nominal HPC will always be
equal or higher than 16, it can be shown that the maximum delay
will be 12 clock cycles. Since this is lower than the nominal
HPC, the division result will be available before a new code
appears. If a particular code step is so short that the divider result
is not available on-time, the divider will skip the new code and
will wait for the next one. This has minimal effect on the final
INL jump value. It can be shown that the inaccuracy on the INL
measurement caused by the truncation error in INBI is given by
(13)
where is the maximum HPC, is the hit number, and Floor
is the truncation to the lower integer. We then have
LSB (14)
Therefore, the maximum INL computation error caused by
the truncation is equal to the error caused by the finite HPC.
D. Coefficient Computation
The role of the coefficient extraction [see (11) and Fig. 2]
is to compute the compensation coefficient for each of the first
three stages. From (11), we can define each of the first three
coefficients with bitwise shifters and adders. Then, from (14),
we find that each coefficient will have a maximum cumulative
error given by
(15)
When the compensation coefficients (numbered , 2, 3)
are applied, they are first scaled by their corresponding and
then added together [see (7) and (8)]. The s can take values of
0, 1, or 2. Therefore, the largest error on the final compensation
code is
LSB (16)
454 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004

Fig. 13. Matlab simulation (for 1.5% mismatch) of the self-calibration with on-chip coefficient extraction scheme showing INL (a) before calibration and (b) after
calibration.

In the case where 6, this represents approxi-

mately 0.3 LSB, which is acceptable for our application. We
can now determine the limitation on the number of stages under
calibration due to the cumulative error and limited INL jump
accuracy.
To verify the validity of the approach and implementation
algorithms, a MATLAB program called fast and intuitive
pipeline ADC simulator (FIPAS) was written in which a
pipeline ADC was simulated with nonidealities (capacitor mis-
match, adjustable noise level) and the INL curve was obtained. Fig. 14. Test setup.
Additional subprograms for the system’s blocks such as the
INJU and coefficient extraction were written in a way that
would simulate exactly their respective implemented circuits.
The simulation is performed in three steps. During the first
step, a ramp is sent to the ADC and the real HPC is estimated
from the output codes (HPC computation). In the second step,
a second ramp is sent and the compensation coefficients are
computed (INL jump extraction and coefficient computation). A
third step is sent to the ADC so that the INL improvements can
be observed. The actual calibration process necessitates only the
first two steps. Fig. 13 illustrates the INL of an ADC with 1.5%
mismatch and typical noise level, (a) before and (b) after cali-
bration. An improvement of more than 2 bits is obtained.

VI. TEST SETUP AND RESULTS

The ultimate goal of the self-calibration scheme is to integrate
the entire system on one chip. The OCRG has been separately
fabricated [7] and it was demonstrated that it could be used for
the task of calibrating a typical pipeline ADC using the proposed
approach.
It was decided to emulate a nonideal ADC on software instead
of fabricating a real ADC on silicon because the latter would
have required additional tunability on several key error sources
in the ADC. Furthermore, this control circuitry would have in-
troduced additional sources of error, imposible to separate from
the intended nonideality. On the other hand, the use of a softwa-
reemulated ADC offers more flexibility, allowing to easily and
precisely test many cases of errors and ADC implementation
(1 bit mode or Lewis mode), noise level, etc. Using FIPAS, we
injected typical nonidealities such as capacitor mismatch, refer-
ence offsets and dc gain errors on the opamps in a pipeline ADC.
Various cases were simulated and the output data of the nonideal
Fig. 15. INL calculated by (a) software and (b) on-chip. The black and gray
curves represent the INL before and after calibration, respectively. This case
uses the 1-bit mode, typical uncalibrated capacitor mismatch (1.5%) and typical
noise level (0.18 SD).
ADC was stored in a file. A data acquisition system from Na-
tional Instruments (NIDAQ) was then used to read the data file
and generate it on a digital data bus. The NIDAQ consisted of
a PXI-1000 module with a PXI6533 and PXI6534 high-perfor-
mance digital I/O card (see Fig. 14). In this way, the NIDAQ
system can be seen as the ADC under calibration with variable
nonidealities. The chip containing the digital self-calibration
loop receives the uncalibrated data, computes the compensation
PROVOST AND SÁNCHEZ-SINENCIO: PRACTICAL SELF-CALIBRATION SCHEME IMPLEMENTATION
TABLE I
EXPERIMENTAL RESULTS
Fig. 16. Zoom on noisy data with 0.3 S.D. noise.
coefficients, and applies them to the input data. The output data
is also acquired by NIDAQ in real-time. The circuits described
in Section V were implemented in VHDL and a Xilinx XCS200
SPARTAN FPGA was programmed using the Digilent “Digilab
2” development board. The FPGA contains all the digital cir-
cuits of the self-calibrating ADC. The digital I/O card supplies
the 20 uncompensated bits (“regions”) to the FPGA, which com-
putes the calibration, compensates and returns the 10 corrected
bits (total of 30 bits, plus several control bits). The I/O limitation
on the acquisition card and their possible configuration limited
the ADC accuracy to 10 bits. The whole system operates at a
frequency of 10 MHz. This speed could be increased by elimi-
nating speed paths in the FPGA implementation. There are no
fundamental speed limitations in the circuit of Fig. 2 and in each
sub-block.
The first test was done using a 10 bits ADC with 1.5% capac-
itor mismatch in all the gain stages and a typical noise level with
a standard deviation (SD) of 0.09 LSB. The results are shown in
Fig. 15. In Fig. 15(a), we see the INL of the output digital ramp
before (black) and after (gray) calibration, showing that it goes
from 2.05 LSB to 0.48 LSB, an improvement of more than 2
bits. This INL was computed from the output digital data using
the traditional method in LabView (DNL for each code, then in-
tegrating to get the INL). In Fig. 15(b), we show the INL before
and after as it was generated by the INBI block within the FPGA.
We can see that the INL curves in Fig. 15(a) and (b) are prac-
tically identical, showing that the on-chip INL computation is
excellent. The apparent “drop” in the overall computed INL be-
fore calibration [in Fig. 15(a)] is caused by some missing codes
at the end of the ramp. Table I shows test results for several addi-
tional nonideal scenarios. Not shown in this table are cases with
reference offset errors resulting in INL lower than 0.5 LSB,
even before calibration, because of the digital error correction
455
(standard in most pipeline ADCs). The effect of the averager
setting (0, 1, 2, or 3) was also observed. As expected, a low
averaging setting under large noise levels results in a decrease
in performance (INL after calibration of 0.83 LSB). An exces-
sively high level of filtering also degrades the performance of
the self-calibrating circuit (INL after calibration of 0.75 LSB).
Fig. 16 shows a close-up on the output data of the ADC before
(black) and after (gray) the Averager when the noise has a SD
of 0.3 LSB. This gives a visual appreciation of the amount of
noise present in the digital data.
VII. CONCLUSION
The proposed self-calibration scheme presents key advan-
tages over the previous approaches. First, it does not require any
modification to the original analog section of the ADC. This in-
sures that the system does not degrade the high-speed perfor-
mance. Second, the self-calibration process does not require the
use of a higher speed micro-controller. Third, the INL measure-
ment can be carried off-chip to simplify the production testing or
to perform performance verification in the application environ-
ment. This is a major advantage for high reliability applications
such as biomedical equipment or security monitoring.
The approach has been proven with behavioral and structural
simulations, as well as experimental measurements. The results
are excellent, showing that the system can calibrate an ADC
with an initial INL of 2.1 LSB to lower than 0.50 LSB.
These typical results were obtained for ADCs using the “1-bit
mode” as well as the “Lewis mode” transfer curves. It can
also withstand a large amount of noise while still extracting
the compensation coefficients accurately. The on-chip INL
extraction provides results that are practically identical to the
external INL computation. The area overhead is 0.18 mm for
456 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004
the ramp generator and the equivalent of 45 000 gates. The
number of gates could be easily reduced since approximately
10% are presently used only for the buffer in the averager
block. Depending on the expected amount of noise in the chip,
the buffer size could at least be reduced by half. This buffer
could also be implemented in RAM for a more efficient use
of the silicon. The “max-min detect” block in INJU occupies
another 30% of the area. This block could be greatly optimized
with a custom “winner-takes-all” circuit.
ACKNOWLEDGMENT
The authors would like to thank E. Bilhan for preliminary
technical discussions.
REFERENCES
[1] J. Goes, J. C. Vital, and J. E. Franca, “An analogue self-calibration
technique for high-resolution video-rate pipelined A/D converters,” in
Proc. 38th Midwest Symp. Circuits and Systems, vol. 2, Aug. 1996, pp.
740–743.
[2] E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for
fully digital correction of monolithic pipelined ADCs,” IEEE Trans. Cir-
cuits Syst. II, vol. 42, pp. 143–153, Mar. 1995.
[3] M. K. Mayes and S. W. Chin, “A 200 mW, 1 Msample/s, 16-b pipelined
A/D converter with on-chip 32-b microcontroller,” IEEE J. Solid-State
Circuits, vol. 31, pp. 1862–1872, Dec. 1996.
[4] A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s
digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits,
vol. 28, pp. 1207–1215, Dec. 1993.
[5] M. Jun and S. H. Lewis, “An 8-bit 80-Msample/s pipelined analog-to-
digital converter with background calibration,” IEEE J. Solid-State Cir-
cuits, vol. 36, pp. 1489–1497, Oct. 2001.
[6] T. Kuyel and H. Bilhan, “Relating linearity test results to design flaws of
pipelined analog-to-digital converters,” in Proc. Int. Test Conf., Atlantic
City, NJ, Sept. 1999, pp. 772–779.
[7] I. E. Opris, L. D. Lewicki, and B. C. Wong, “A single-ended 12-bit
20 Msample/s self-calibrating pipeline A/D converter,” IEEE J. Solid-
States Circ., vol. 33, pp. 1898–2003, Dec. 1998.
[8] B. Provost and E. Sánchez-Sinencio, “Auto-calibrating analog timer for
on-chip testing,” in Proc. Int. Test Conf., Atlantic City, NJ, Sept. 1999,
pp. 541–548.
[9] E. Bilhan, E. Soenen, and F. Maloberti, “An efficient digital method for
nonlinearity correction in pipelined ADCs,” in Proc. Inst. Elect. Eng.
Int. Analog VLSI Workshop, Stockholm, Sweden, June 2–3, 2000, pp.
57–62.
[10] S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-
digital converter,” IEEE J. Solid-State Circuits, pp. 954–961, Dec. 1987.
[11] J. G. Proakis and D. G. Manolakis, Digital Signal Processing, Princi-
ples, Algorithms, and Applications. Englewood Cliffs, NJ: Prentice-
Hall, 1996.
[12] B. Provost and E. Sánchez-Sinencio, A Simple Pass/Fail Digital BIST
for ADCs Based on Improved Monotonicity Test.
Benoit Provost (S’03) was born in Montréal, QC,
Canada, in 1970. He received the B.S. and M.S.
degrees in electrical engineering from the École
Polytechnique de Montréal in 1993 and 1995,
respectively, and the Ph.D. in electrical engineering
from the Analog and Mixed-Signal Center, Texas
A&M University, College Station, in 2002. His
M.S. thesis focused on the design of an implantable
bladder volume monitor to correct urinary dysfunc-
tions and his Ph.D. dissertation focused on analog
and mixed signal built-in self-test and pipeline ADC
self-calibration.
In 1997 and 2000, he was with Texas Instruments, Dallas, TX, working on
ADC self-test and self-calibration. He joined Intel Corporation, Hillsboro, OR,
in 2002, where he concentrates on high-speed design-for-testability techniques.
Edgar Sánchez-Sinencio (F’92) was born in Mexico
City, Mexico. He received the degree in commu-
nications and electronic engineering (Professional
degree) from the National Polytechnic Institute of
Mexico, Mexico City, in 1966, the M.S.E.E. degree
from Stanford University, Stanford, CA, in 1970,
and the Ph.D. degree from the University of Illinois,
Champaign-Urbana, in 1973.
In 1974, he held an industrial Postdoctoral posi-
tion with the Central Research Laboratories, Nippon
Electric Company, Ltd., Kawasaki, Japan. From 1976
to 1983, he was the Head of the Department of Electronics at the Instituto Na-
cional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was
a Visiting Professor in the Department of Electrical Engineering, Texas A&M
University, College Station, during the academic years of 1979 to 1980 and
1983 to 1984. He is currently the TI J Kilby Chair Professor and Director of
the Analog and Mixed-Signal Center, Texas A&M University. He was the Gen-
eral Chairman of the 1983 26th Midwest Symposium on Circuits and Systems.
He is coauthor of the book Switched Capacitor Circuits (New York: Van Nos-
trand-Reinhold, 1984), and coeditor of the book Low Voltage/Low-Power Inte-
grated Circuits and Systems (New York: IEEE Press, 1999). His present interests
are in the area of RF-communication circuits and analog and mixed-mode cir-
cuit design.
Dr. Sánchez-Sinencio is presently a member of the IEEE Solid-State Circuits
Award Committee. He was an Associate Editor for IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS from 1985 to 1987, and an Associate Editor for the
IEEE TRANSACTIONS ON NEURAL NETWORKS. He is the former Editor-in-Chief
of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. In November 1995,
he was awarded an Honoris Causa Doctorate by the National Institute for Astro-
physics, Optics and Electronics, Mexico, the first honorary degree awarded for
microelectronic circuit design contributions. He received the 1995 Guillemin-
Cauer for his work on cellular networks. He was also the corecipient of the
1997 Darlington Award for his work on high-frequency filters. He received the
Circuits and Systems Society Golden Jubilee Medal in 1999. He was Represen-
tative to the Solid-State Circuits Society (2000–2002) for the IEEE Circuits and
Systems Society. He is a former IEEE CAS Vice President-Publications. He was
an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS from
1985 to 1987, and an Associate Editor for the IEEE TRANSACTIONS ON NEURAL
NETWORKS. He is the former Editor-in-Chief of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS II.