This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2833866, IEEE
Transactions on Circuits and Systems II: Express Briefs
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm
CMOS
Yi Xie, Yuhua Liang, Maliang Liu, Shubin Liu, and Zhangming Zhu
 hybrid VCO-SAR ADC architecture. The principles of the
Abstract—This brief presents a 10-bit 5 MS/s hybrid
analog-to-digital converter (ADC) combining successive
approximation register (SAR) with voltage-controlled oscillator
(VCO) in 0.18-µm CMOS. Non-ideal factors from practical circuit
implementations are theoretically considered and modeled in
Simulink. To improve the linearity and the reliability of the
bootstrapped switch circuit, the body-effect compensation is
adopted. The asynchronous clock generation circuit with a
variable-time control cell is presented, which optimizes the DAC
settling time of the MSB DAC and LSB DAC in a SAR conversion.
Verilog codes and a standard digital library make it possible to
synthesize the most parts of the VCO-based Nyquist ADC, greatly
reducing the design costs. At Nyquist input frequency and a 5
MS/s sampling rate, a signal-to-noise and distortion ratio (SNDR)
of 56.7 dB and a spurious-free dynamic range (SFDR) of 72.2 dB
are achieved, respectively. The core occupies 450 μm×280 μm.
Index Terms—analog-to-digital converter (ADC), successive
approximation register (SAR), voltage-controlled oscillator
(VCO), hybrid ADC
I. INTRODUCTION
A NALOG-TO-DIGITAL converters (ADCs) play an
essential role in transforming analog signals into digital
codes. Charge-redistribution successive approximation register
(SAR) ADCs, which do not need high-gain/bandwidth
operational amplifiers, are widely used in medium resolution
application areas [1]-[2]. Hybrid ADCs based on SAR ADCs
have also been reported in order to improve the ADC
performance. To accelerate the conversation speed, Flash-SAR
[3] and pipeline-SAR [4] architectures are commonly seen. In
addition, the sigma-delta theory has been utilized in [5]-[8] to
enhance the ADC resolution.
In this brief, a 10-bit 5 MS/s hybrid VCO-SAR ADC in
the SMIC 0.18-μm 1P6M CMOS process is presented. Most
of the circuits in the VCO-based ADC can be implemented in
Verilog codes, which is friendly to the advanced CMOS
process. Meanwhile, thanks to the use of the SAR ADC, not
only the proposed architecture could be energy-efficient but
also the linearity requirement of the VCO can be relaxed
compared to the pure VCO-based ADCs without calibration.
This brief is organized as follows. Section II describes the
Manuscript received. This work was supported by the National Natural
Science Foundation of China (61625403, 61574105, 61574103)
The authors are with the Shaanxi Key Lab. of Integrated Circuits and
Systems, School of Microelectronics, Xidian University, Xi’an 710071, China
(e-mail: zmyh@263.net, zhangmingzhu@xidian.edu.cn)
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non-ideal effects are discussed and modeled in Section III. A
detailed circuit design of the proposed ADC is described in
Section IV. Section V shows the measured results, followed by
a conclusion given in Section VI.
II. PROPOSED VCO-SAR ADC
The proposed architecture of a hybrid VCO-SAR ADC is
shown in Fig. 1. This 10-bit ADC architecture consists of a
7-bit SAR ADC as the coarse ADC and a 3-bit VCO-based
Nyquist ADC as the fine ADC. The proposed ADC yields
advantages compared with both the VCO-based Nyquist ADC
and the SAR ADC. As for the VCO-based Nyquist ADC, the
proposed architecture relaxes the linearity requirement of the
VCO. For the SAR ADC, the proposed hybrid ADC reduces the
total area of the capacitance array used in the conventional SAR
ADC.
The workflow of the proposed ADC is described as follow.
When CLK_SMP goes high, analog differential input signals
VIP and VIN are sampled on differential DACs by the S/H
circuits. During the SAR conversion time, a comparator and the
SAR logic triggered by an asynchronous clock signal perform a
successive approximation operation. According to the
comparison result, the SAR logic converts switch signals Pi and
Ni (i = 6,5,…,0) to change VDAC_P and VDAC_N (VDAC_P represents
the voltage on the DACP and VDAC_N represents the voltage on
the DACN), respectively. When the successive approximation
process finishes, the coarse ADC exports quantization codes
D[9:3]. From then on, two ring VCOs can generate stable
oscillation waves under the residual voltage VDAC_P and VDAC_N.
With the presence of two DACs, VDAC_P and VDAC_N can be held
during the operation of the VCO-based ADC. Two multi-phase
counters are reset to zero by CLK_RST and then begin to
record the number of the rising edges from two VCOs,
respectively. Once the CLK_SUM becomes high, the total
rising edge numbers corresponding to the residual voltage on
the differential VCOs are produced by two adders. Also, the
value representing differential voltages on DACs is observed
through the subtraction operation. Finally, an encoder outputs
remaining binary codes D[2:0].
In the VCO-based Nyquist ADC [9], the VCO is seen as a
voltage-to-time converter. The output frequency is linearly
controlled by an input voltage if the VCO has a good linearity.
With the use of the 7-bit SAR ADC, the maximum absolute
magnitude of the input voltage difference is 4 LSB, so that the
linearity requirement of the VCOs can be ensured.
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Transactions on Circuits and Systems II: Express Briefs

SAR ADC VCO-based ADC

D[9:3]
SAR Logic
Pi&Ni
(i=6,5,…,0) … ... ... ... ∑
VDAC_P Counter
VIP Differential + N
CLK_RST CLK_SUM Encoder D[2:0]
VIN DACs -

VDAC_N Counter
... ... ... ∑
CLK_SMP

Fig. 1. Block of the proposed VCO-SAR ADC.

(a) (b) (c)

Fig. 2. Influence of non-idealities about (a) VCO gain error, (b) differential VCO gain mismatch and (c) counting time error.

The output value N (shown in Fig. 1) can be obtained as that ΔKVCO causes changes of the input of the encoder, which
N  KVCO VDAC _ P  VDAC _ N TCounting (1)
will cause the actual digital codes to deviate from the designed
codes eventually. If the non-ideal term into the encoder is
where KVCO is the gain of the VCOs (unit: Hz/V), VDAC_P and regarded as a noise term, we can obtain an expression for the
VDAC_N are the differential analog input voltage from the signal-to-noise ratio (SNR). Because the non-ideal term and the
corresponding DACs and TCounting is a counting time determined ideal term will experience the same linear process, their
by CLK_RST and CLK_SUM. difference comes from ΔKVCO /KVCO. Therefore, the SNR due to
We employ multi-phase counters to perform an integration the gain error is given as
of rising edges during one counting period. Evidently, a
  K 
2
 
1-phase counter can only differentiate a phase more than 2π,   VCO
SNRGain  10log10  PowerN0  PowerN0  Powernoise  
while an N-phase counter can distinguish a phase more than   KVCO ,0  
 
2π/N. Hence, it is wiser to adopt the multi-phase counter when
the multi-phase VCO are employed. (3)
where 0
represents the ideal signal power and Power noise

III. NON-IDEALITIES represents a noise power except the VCO’s linearity error.
When the noise power from the linearity error is much greater
In this section, we will analysis the non-ideal effects from the
than Powernoise, (3) can be rewritten as
VCO-based ADC and execute a behavioral modeling based on
this 10-bit hybrid ADC. According to (1), the influence factors  K 
SNRGain  20log10  VCO,0 . (4)
of N involve the VCO gain and the counting time.  KVCO 
A. Gain Error of VCOs
B. Mismatch of Differential VCOs
The absolute magnitude of (VDAC_P−VDAC_N) is restricted to 4
The mismatch of the differential VCOs, caused by an
LSB, so the VCO gain can be treated as a constant. However,
asymmetric layout or a non-uniform doping concentration
KVCO will deviate from the desired value because of process,
distribution during the fabrication, affects the performance of
voltage and temperature (PVT) variations.
the VCO-based ADC. In order to analysis the mismatch’s effect
When the differential VCOs have the same gain KVCO, the
simply, we assume the deviation term ΔKVCO is only caused by
actual value consists of two parts: one is the ideal value KVCO,0,
the mismatch.
the other is the deviation value ΔKVCO. Equation (1) can be
For the differential VCOs, the differential VCO gains can be
rewritten as
seen as two parts, or common mode and differential mode.
 KVCO 
N   KVCO,0  KVCO  VDAC _ P  VDAC _ N TCounting  N0 1 
Assuming that the expressions of KVCO,P and KVCO,N is
 
 KVCO,0  KVCO,P  KVCO,0 +KVCO (5)
(2) KVCO, N  KVCO,0  KVCO (6)
where N0 represents the desired number. From (2), one finds

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2833866, IEEE
Transactions on Circuits and Systems II: Express Briefs

VDD VDD
M2 CLK_B CLK_CMP
M1 M3 M3 M4
M7
VP VN
M11 M12
M5 VIP M1 M2 VIN
C1 C2 C3 CLK_SMP Sampling Switch
M8
M6 M10
CLK_CMP M0
CLK_B Vout
M9
M4
Vin CLK_B VDD
M13 M14 M5 M6
CLK_SMP

Fig. 3. Bootstrapped switch with body-effect compensation. M7 M8

OP ON
COMP COMN
where KVCO,0 is the designed value and ΔKVCO is the mismatch
term, the non-ideal effect from the mismatch is obtained as CLK_B
CLK_CMP CLK_B
 
M11 M9 M10 M12
N   KVCO,0  KVCO VDAC _ P   KVCO,0  KVCO VDAC _ N TCounting

 K VCO ,0 V
DAC _ P  VDAC _ N   KVCO VDAC _ P  VDAC _ N  TCounting  Fig. 4. Dynamic latch comparator.

 KVCO VDAC _ P  VDAC _ N  

 N 0 1  .

 KVCO,0 VDAC _ P  VDAC _ N  
(7)
By comparing (7) and (2), one finds that the effects of the
mismatch involve not only the VCO gain but also VDAC, and the
influence of the mismatch is magnified by a factor of
[(VDAC_P+VDAC_N)/(VDAC_P−VDAC_N)]. If the mismatch term is
much greater than the other noise term, the theoretical
restriction on the SNR by the mismatch can be calculated as
 KVCO,0 VDAC _ P  VDAC _ N 
SNRMismatch  20log10  .
 KVCO VDAC _ P  VDAC _ N  
 
C. Error of Counting Time
The counting time is another factor that can influence the
performance of the proposed ADC. Similarly, we can derive
this non-ideality as
N  KVCO VDAC _ P  VDAC _ N TCounting ,0  TCounting 
 TCounting 
 N 0 1   connects the source terminal and the body terminal of M10,
 TCounting ,0 
 (9)
where ΔTCouting is the deviation value from the designed value
TCounting,0. It should be noted that the counting time error has the
same effect on the SNR like the VCO gain error, expressed as
 TCounting ,0
SNRCounting  20log10 
 TCounting
 
These non-idealities are respectively behavioral modeled in
Simulink, as shown in Fig. 2. The effects from the VCO gain
error and the counting time error are almost the same and these
SNRs both drop at a rate of -20 dB/dec, while the SNR
restricted by the differential VCO gain mismatch falls faster
than the former ones.
IV. CIRCUIT IMPLEMENTATION
The proposed VCO-SAR ADC mainly includes a SAR ADC,
two ring VCOs and other digital circuits. The digital circuits
including the counter, the adder and the encoder, are all realized
by Verilog hardware description language (HDL).
A. Capacitive DAC
In a 7-bit SAR ADC design, the mismatch is dominant over
the thermal noise. In this 0.18-μm CMOS technology, the
mismatch of the minimum metal-insulator-metal (MIM)
capacitor is 1.0142% with 1-sigma, whose area is 4μm×4μm.
Monte-Carlo simulation results made in MATLAB show that
the minimum MIM capacitor can cover the requirement of the
(8) SAR ADC linearity. Hence, the minimum MIM capacitor is
chosen as a unit capacitor and the single-end capacitance is
about 2 pF in total.
B. Bootstrapped Switch
The schematic of the bootstrapped switch in the proposed
design is shown in Fig. 3. To enhance the linearity and the
reliability of the bootstrapped switch, nMOS M13 and M14 are
added. During the sampling time (or CLK_SMP= “1”), M13
eliminating the body-effect of M10 and increasing the
on-resistor linearity. When CLK_SMP is low, M14 is switched
on to connect the body terminal of M10 to VGND, hence, both the
source-substrate PN junction and the drain-substrate PN
junction of M10 as well as M13 are either reverse-biased or

. zero-biased, enhancing the robustness of the S/H circuit.
 (10) If N-bit accuracy is required, and the settling error must be
less than 0.5 LSB, the on-resistor of sampling switch [10] is
Tsmp
Ron 
 N  1  C  C  ln 2
s p
(11)
where Tsmp is the sampling time for the bootstrapped switch, Cs
and Cp are the total DAC capacitance and the total parasitic
capacitance in the single-ended DAC, respectively. For the
proposed ADC, Ron should be less than 220 Ω.
C. Dynamic Latch Comparator
Fig. 4 shows the dynamic comparator where a dynamic

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2833866, IEEE
Transactions on Circuits and Systems II: Express Briefs

OP
ON
Clk Clk Clk Clk
D Q D Q D Q D

bit-slice

bit-slice

bit-slice

bit-slice
CLK_SMP EN
COMP P6 COMP P5 COMP P3 COMP P0
COMN N6 COMN N5 COMN N3 COMN N0
Q3

Fig. 5. Asynchronous SAR control logic.

VDD VDD
M1 M3 M6 M4
CLK_SMP OP M3 ON M4
VA
M5
CLK_CMP NOR Q3 M7 M8
AND2 M7 VB
EN M1 M2 VB
Cdelay VA In+ In−
M6 VB VDAC
AND1
Variable-Time
Control Cell
M2 M5
Fig. 6. Asynchronous clock generator.
M9
VDAC EN_B
Out− Out+
EN_B
EN
Fig. 8. VCO delay cell.

M1 whereas VB is charged to VDD via pMOS M5. Besides,

Buffer Array
PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PH16
Fig. 7. 8-stage ring VCO.
pre-amplifier is introduced to save power. This dynamic
comparator can also isolate the kickback noise. The
input-referred integrated noise [11] is given as
4kT Vthermal
V  2
CVP,VN Vth,latch
where k is the Boltzmann constant, T is the absolutely
temperature, CVP,VN is the parasitic capacitance at VP/VN node,
Vthermal and Vth,latch are the thermal voltage and the threshold
voltage of the latch, respectively. In the extracted netlist, CVP,VN
is about 9.4 fF. Assuming that Vth,latch is 0.9 V under a 1.8-V
supply, the comparator input-referred noise is 0.32 mVrms, so it
would not be a main restraint in this 7-bit coarse ADC.
D. Asynchronous SAR control logic
By adopting an asynchronous SAR control logic, a
high-frequency clock for the comparator is avoided and the
DAC settling time for different capacitors is adjustable. The
schematic of the asynchronous control logic is shown in Fig. 5.
Pi and Ni (i=6,5…,0) serve as control signals for the DAC
control logic. Q3 acts as a control signal for a variable-time
comparator clock generator and EN is used as an enable clock
for the differential VCOs.
Fig. 6 is the schematic of the comparator clock generator
with the variable-time control cell. Based on feedback, the
asynchronous clock is produced. The procedure of the
asynchronous clock generation is described as follows: (1)
during the sampling time, VA is discharged to VGND via nMOS
CLK_CMP and EN are also reset to low when Q3 is reset to
high. (2) Once the SAR conversion starts, CLK_CMP goes
high since both inputs of NOR gate are “0”, and then the
comparison is executed. (3) Either OP or ON is connected to
VGND according to comparison results. Then VA becomes high,
forcing CLK_CMP discharge to VGND. Due to the existence of
the variable-time control cell, VA needs more time to rise up
when Q3=“1”, so the DAC settling time for MSB capacitors
becomes longer than that for LSB capacitors. (4)
Simultaneously, VB falls down by the action of AND1 gate and
nMOS M6, so does VA via nMOS M2. CLK_CMP goes high
again. (5) The following CLK_CMP will be generated by
(12)
repeating the (3)-(4) procedures till the rising edge of EN
arrives.
E. Ring VCO
The 8-stage ring VCO is shown in Fig. 7, which has 16-phase
outputs. The outputs can be reshaped by inverters in the buffer
array and then be sent to the counters. The delay cells in the ring
VCO are implemented as shown in Fig. 8. EN comes from the
SAR logic, and EN_B is the control signal for the VCOs. When
EN goes high (EN_B goes down), the SAR conversion ends
and the differential VCOs start to work. When EN goes down
(EN_B goes high), the differential VCOs stop oscillating. The
VCO gain is 402 MHz/V.
V. MEASUREMENT RESULTS
The proposed hybrid VCO-SAR ADC is fabricated in the
SMIC 0.18-μm 1P6M CMOS process. Fig. 9 shows the die
microphotograph of the proposed ADC. The core occupies 450
μm×280 μm. The proposed ADC operates at a 1.8-V analog
power supply and a 1.2-V digital power supply, consuming
2.36 mW in total. The asynchronous SAR ADC and two ring
VCOs consume 630 μA and 340 μA from a 1.8-V analog
supply, respectively; meanwhile, the digital circuits following

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2833866, IEEE
Transactions on Circuits and Systems II: Express Briefs

TABLE I
PERFORMANCE SUMMARY AND COMPARISON
ISCAS’15 TVLSI’16 TCASI’17
This Work
[12] [13] [14]

280 μm
Architecture VCO-SAR Cyclic Two-step Pipeline

CMOS
180 180 180 28
(nm)
450 μm Resolution
10 9 12 11
(bit)
Fig. 9. Die microphotograph of the proposed ADC. Sampling Rate
5 16.7 3.4 20
(MHz)
Total Power
2.36 4.7 2.9 2.24
(mW)
Active Area
0.126 0.045 0.603 0.052
(mm2)
SNDR
56.7 52.5 64.3 56.6
(dB)
ENOB
9.13 8.43 10.39 9.11
(bit)
FOM
(a) (b) 0.845 0.818 0.66 0.203
(pJ/conv.-step)
Fig. 10. FFT spectra with (a) 2.50 MHz input and (b) 0.25 MHz input.

Fig. 11. Dynamic performance versus input frequency.
the VCOs are synthesized drawing 513 μA from a 1.2-V digital
supply.
The fast Fourier transform (FFT) spectra of this 5 MS/s ADC
are shown in Fig. 10. At Nyquist input frequency, the measured
spurious-free dynamic range (SFDR) and signal-to-noise and
distortion ratio (SNDR) are 72.2 dB and 56.7 dB, respectively,
shown in Fig. 10(a). The corresponding effective number of
bits (ENOB) is 9.13 bit. With the input frequency of 0.25MHz,
an SFDR of 76.5 dB and an SNDR of 59.8 dB are achieved,
respectively, shown in Fig. 10(b). Fig. 11 plots the measured
SFDR and SNDR as a function of the analog input frequency.
Table I summarizes the performance of the proposed ADC
compared to [12]-[14].
VI. CONCLUSION
In this brief, a 10-bit 5 MS/s VCO-SAR Nyquist ADC
fabricated in the 0.18-μm CMOS is described. After the SAR
conversion, the VCOs realize the conversion from voltage to
frequency. To improve the dynamic performance of the
VCO-based Nyquist ADC as well as the proposed hybrid ADC,
two multi-output ring VCOs and two multi-phase counters are
both introduced in the proposed ADC architecture. The
measured results show that the proposed VCO-SAR ADC
achieves an SFDR of 72.2 dB and an SNDR of 56.7 dB at
Nyquist rate, resulting in an ENOB of 9.13 bit.
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