Analog Circuits

Ankesh Jain

Indian Institute of Technology, Delhi

India, 110016
 Introduction 2

§ Transfer function of the circuit shown in figure is

𝑉! 1
=−
𝑉" 𝑠𝑅𝐶
§ It functions as an integrator
§ It acts like a low pass filter
C

R
Vi -
Vo
+
 Introduction 3

R 𝑉! 1
=−
Vi - 𝑉" 𝑠𝑅𝐶
Vo
+

• On chip realization of R and C has some

tolerances
• It can range somewhere 20% to 30%
• Mismatch in time constant can be 40% to 60%
• This problem occurs as R and C varies differently
 Introduction 4

R
Vi -
Vo
+
𝑉! 1
=−
𝑉" 𝑠𝑅𝐶
• R effectively transfers some charge from input to
capacitor
• Can it be done through some other ways?
 Resistor using switched capacitor 5

R
VA VB

Charge transfer fromφ1A-B φ2

VA 𝑉! − 𝑉" VB
𝑄=# C 𝑑𝑡
𝑅 φ1
φ2
Charge transfer during one clock period
𝑉! − 𝑉" 𝑉! − 𝑉"
𝑄= 𝑇=
𝑅 𝑅𝑓
 Resistor using switched capacitor 6

R Charge transfer during one

VA VB
clock period

φ1 φ2
VA VB 𝑄 = 𝐶(𝑉! −𝑉" )
C φ1 1
𝐶=
φ2 𝑅𝑓

1
𝑅=
𝑓𝐶
 Switched capacitor Integrator 7

Cf
φ1 φ2
Vi -
Ci Vo
+
φ1
φ2
§ During phase f1, top plate of Ci connects to input
§ Ci gets charged to Vi
 Switched capacitor Integrator 8

Cf

Vi -
Ci Vo
+

§ During phase f1, top plate of Ci connects to input

§ Ci gets charged to Vi
§ Charge on Cf remains unchanged
 Switched capacitor Integrator 9

Cf

-
Ci Vo
+

§ During phase f2, top plate of Ci connects to virtual ground

§ Charge on Ci in f2 is 0
§ As top plate has only one way to lose its charge
§ It transfer charge to Cf
 Switched capacitor Integrator 10

Cf
φ1 φ2
Vi -
Ci Vo
+
φ1
φ2

𝑄𝑓 𝑛 = 𝑄𝑓 𝑛 − 1 − 𝑄𝑖 𝑛 − 1
𝐶𝑓𝑉𝑜 𝑛 = 𝐶𝑓𝑉𝑜 𝑛 − 1 − 𝐶𝑖𝑉𝑖 𝑛 − 1
𝐶𝑓𝑉𝑜 𝑧 = 𝑧 #$ 𝐶𝑓𝑉𝑜 𝑧 − 𝑧 #$ 𝐶𝑖𝑉𝑖 (𝑧)
𝑉% (𝑧) 𝐶& 𝑧 #$
=−
𝑉& (𝑧) 𝐶' (1 − 𝑧 #$ )
 Realization of capacitor 11

Top plate
C Cp1
Bottom plate
Cp2

Substrate

§ C is desired capacitor
§ Cp1 and Cp2 are parasitic capacitor
§ 𝐶𝑝1 < 𝐶𝑝2
 Switched capacitor Integrator 12

Cp3 Cf
Cp1 Cp4
φ1 φ2
Vi -
Ci Vo
+
φ1
Cp2
φ2

§ During phase f1, top plate of Ci connects to input

§ Ci and Cp1 gets charged to Vi
§ Cp3 is always connected to 0V and do not store any charge
§ Cp2 and Cp4 are connected to low impedance source and do
not transfer charge to Cf
 Switched capacitor Integrator 13

Cp3 Cf
Cp1 Cp4
φ1 φ2
Vi -
Ci Vo
+
φ1
Cp2
φ2

§ During phase f2,

§ Top plate of Ci and Cp1 connects to virtual ground
§ Charge from Ci and Cp1 is transferred to Cf
§ Cp2 and Cp3 is still charged to 0
 Switched capacitor Integrator 14

Cf
φ1 Cp1 φ2
Vi -
Ci Vo
+
φ1
Cp2 φ2

𝑄𝑓 𝑛 = 𝑄𝑓 𝑛 − 1 − 𝑄𝑖 𝑛 − 1 − 𝑄𝑝1[𝑛 − 1]
𝐶𝑓𝑉𝑜 𝑛 = 𝐶𝑓𝑉𝑜 𝑛 − 1 − 𝐶𝑖𝑉𝑖 𝑛 − 1 − 𝐶𝑝1𝑉𝑖 𝑛 − 1
𝐶𝑓𝑉𝑜 𝑧 = 𝑧 #$ 𝐶𝑓𝑉𝑜 𝑧 − 𝑧 #$ 𝐶𝑖𝑉𝑖(𝑧) −𝑧 #$ 𝐶𝑝1𝑉𝑖(𝑧)

𝑉! (𝑧) 𝐶" + 𝐶%$ 𝑧 #$

=−
𝑉" (𝑧) 𝐶& (1 − 𝑧 #$ )
 Switched capacitor Integrator 15

Cf
φ1 Cp1 φ2
Vi -
Ci Vo
+
φ1
Cp2 φ2

𝑄𝑓 𝑛 = 𝑄𝑓 𝑛 − 1 − 𝑄𝑖 𝑛 − 1 − 𝑄𝑝1[𝑛 − 1]
𝐶𝑓𝑉𝑜 𝑛 = 𝐶𝑓𝑉𝑜 𝑛 − 1 − 𝐶𝑖𝑉𝑖 𝑛 − 1 − 𝐶𝑝1𝑉𝑖 𝑛 − 1
𝐶𝑓𝑉𝑜 𝑧 = 𝑧 #$ 𝐶𝑓𝑉𝑜 𝑧 − 𝑧 #$ 𝐶𝑖𝑉𝑖(𝑧) −𝑧 #$ 𝐶𝑝1𝑉𝑖(𝑧)

𝑉! (𝑧) 𝐶" + 𝐶%$ 𝑧 #$

=−
𝑉" (𝑧) 𝐶& (1 − 𝑧 #$ )
 Switched capacitor Integrator 16

Cf
φ1 Cp1 φ2
Vi -
Ci Vo
+
φ1
Cp2 φ2

𝑉! (𝑧) 𝐶" + 𝐶%$ 𝑧 #$

=−
𝑉" (𝑧) 𝐶& (1 − 𝑧 #$ )
§ Gain is sensitive to parasitic capacitance
§ This integrator is inverting integrator
§ Input is sampled over top plate of input capacitance
 Noninverting delayed integrator 17

Cf
φ1 Cp2 Cp1 φ2
Vi -
Ci Vo
φ1 +
φ2

§ During phase f1
§ Input is sampled on bottom plate of capacitor
§ Cp2 is charged to Vi and Cp1 is charged to 0
 Noninverting delayed integrator 18

Cf
φ1 Cp2 Cp1 φ2
Vi -
Ci Vo
φ1 +
φ2

§ During phase f2
§ Top plate of Ci is connected to virtual ground
§ Charge on Cp2 is discharged to ground
§ Cp1 is connected to ground in phase f1 and virtual ground in f2
§ Only charge stored on Ci in f1 gets transferred to Cf
Noninverting delayed integrator 19

Cf
φ1 Cp2 Cp1 φ2
Vi -
Ci Vo
φ1 +
φ2

𝑄𝑓 𝑛 = 𝑄𝑓 𝑛 − 1 − 𝑄𝑖 𝑛 − 1
𝐶𝑓𝑉𝑜 𝑛 = 𝐶𝑓𝑉𝑜 𝑛 − 1 − 𝐶𝑖𝑉𝑖 𝑛 − 1
𝐶𝑓𝑉𝑜 𝑧 = 𝑧 #$ 𝐶𝑓𝑉𝑜 𝑧 − 𝑧 #$ 𝐶𝑖𝑉𝑖 𝑧
𝑉! (𝑧) 𝐶" 𝑧 #$
=
𝑉" (𝑧) 𝐶& (1 − 𝑧 #$ )
 Inverting delay free integrator 20

Cf
φ1 Cp2 Cp1 φ1
Vi -
Ci Vo
φ2 +
φ2

𝑄𝑓 𝑛 = 𝑄𝑓 𝑛 − 1/2 − 𝑄𝑖 𝑛
𝐶𝑓𝑉𝑜 𝑛 = 𝐶𝑓𝑉𝑜 𝑛 − 1 − 𝐶𝑖𝑉𝑖 𝑛
𝐶𝑓𝑉𝑜 𝑧 = 𝑧 #$ 𝐶𝑓𝑉𝑜 𝑧 − 𝐶𝑖𝑉𝑖 𝑧
𝑉! (𝑧) 𝐶" 1
=−
𝑉" (𝑧) 𝐶& (1 − 𝑧 #$ )
 Inverting delay free integrator 21

Cf
φ1 Cp2 Cp1 φ1
Vi -
Ci Vo
φ2 +
φ2

𝑉! (𝑧) 𝐶" 1
=−
𝑉" (𝑧) 𝐶& (1 − 𝑧 #$ )
§ The gain has negative sign
§ The transfer function does not have any delay
 Inverting amplifier 22

Cf
φ1 Cp2 Cp1 φ1
Vi -
Ci Vo
φ2 +
φ2

𝑄𝑓 𝑛 = −𝑄𝑖 𝑛
𝐶𝑓𝑉𝑜 𝑛 = −𝐶𝑖𝑉𝑖 𝑛
𝐶𝑓𝑉𝑜 𝑧 = −𝐶𝑖𝑉𝑖 𝑧
𝑉! (𝑧) 𝐶"
=−
𝑉" (𝑧) 𝐶&
 23

Thank
you