Week 5: Assignment 5

Q1: For a combinational logic gate, 𝛼 = 0.2, 𝐶𝐿 = 150 𝑓𝐹, 𝑉𝐷𝐷 = 2𝑉, and 𝑓𝑐𝑙𝑘 = 2 𝐺𝐻𝑧. (A)
Calculate circuit power dissipation, (B) Calculate circuit power dissipation if 𝑉𝐷𝐷 = 1.5 𝑉.

a. 120 𝜇𝑊, 67.5 𝜇𝑊

b. 110 𝜇𝑊, 57.5 𝜇𝑊
c. 130 𝜇𝑊, 77.5 𝜇𝑊
d. 100 𝜇𝑊, 57.5 𝜇𝑊

Ans: (a) 120 𝜇𝑊, 67.5 𝜇𝑊

Q2: In a CMOS inverter short circuit power is consumed ______.

a. During charging and discharging of load capacitor
b. Due to short circuit paths between supply rails during switching
c. Due to Leaking diodes and transistors
d. None of the above
Ans: (b) Due to short circuit paths between supply rails during switching
Q.3 Estimate the delay (d) of a fanout-of-5 (FO5) inverters, as shown in Figure below

a. 3
b. 4
c. 5
d. 6
Ans: (d) 6
Q 4: Calculate the delay for 2-input NAND gate which drives 10, 2-input NAND gates as shown in
figure .
 a. 15.33 delay units
b. 20 delay units
c. 10 delay units
d. 40 delay units
Ans: (a) 15.33 delay units
Q.5 A four-input nor gate drives 7 identical gates, as shown in Figure below. What is the
delay in the driving nor gate?

a. 28 delay units
b. 30 delay units
c. 32 delay units
d. 25 delay units
Ans: (d) 25 delay units
Q.6 Consider the path from A to B involving three two-input NAND gates shown in Figure
below. The input capacitance of the first gate is C, and the load capacitance is also C. Using
the concept of logical effort, what should be the least delay of this path?
 a. 10 delay units
b. 9 delay units
c. 11 delay units
d. 12 delay units
Ans: (a) 10 delay units
Q.7 In CMOS technology, NMOS and PMOS devices are fabricated on:
a. Same metal layer
b. Different metal layer
c. on same substrate
d. on different substrate
Ans: (c) on same substrate
Q.8 The main reason of the application of CMOS circuits for IC-chips fabrication is:
a. low static power dissipation
b. low packing density
c. low cost
d. operable at low voltage
Ans: (a) low static power dissipation
Q. 9 In the Twin-tub process of CMOS fabrication following steps are employed
i. Gate and Field oxide formation
ii. Metallization
iii. N-well and P-well formation
iv. Source and Drain implantation
(a) ii iii iv i
(b) iv iii ii i
(c) i ii iv iii
(d) iii i iv ii
Ans: (d) iii i iv ii
Q. 10 In CMOS technology, shallow P-well or N-well regions can be formed using _____.
a. low energy spattering
b. low-pressure chemical vapor deposition
c. low energy ion implantation
d. low-temperature dry oxidation
Ans: (c) low energy ion implantation

Week 5: Assignment 5: Brief Explanation

Q1. Explanation:
1 1
𝑃𝐷 = 𝐶𝐿 𝑉𝐷𝐷2 𝛼𝑓 = × 150 × 10−15 × 22 × 0.2 × 2 × 109 = 120 µ𝑊
2 2
If VDD changed to 1.5V
1 1
𝑃𝐷 = 𝐶𝐿 𝑉𝐷𝐷2 𝛼𝑓 = × 150 × 10−15 × 1.52 × 0.2 × 2 × 109 = 67.5 µ𝑊
2 2
Q2. Explanation:

Short circuit power is consumed due to short circuit paths between supply rails during
switching. While dynamic power is consumed during charging of load capacitor and leakage
power is due to leakage currents of the transistors,
Q3. Explanation:

𝑓 =𝑔×ℎ =1×5=5

𝑃𝑖𝑛𝑣 = 1

𝑑 = 𝑓 + 𝑃𝑖𝑛𝑣 = 5 + 1 = 6 𝑑𝑒𝑙𝑎𝑦 𝑢𝑛𝑖𝑡𝑠

Q4. Explanation:

4 40
𝑓 =𝑔×ℎ = × 10 =
3 3
𝑃𝑎𝑟𝑎𝑠𝑖𝑡𝑖𝑐 𝑑𝑒𝑙𝑎𝑦 = 𝑛𝑃𝑖𝑛𝑣 = 2 × 1 = 2
40
𝑑 = 𝑓 + 𝑃𝑖𝑛𝑣 = + 2 = 15.33 𝑑𝑒𝑙𝑎𝑦 𝑢𝑛𝑖𝑡𝑠
3
Q5. Explanation:
9
𝑓 =𝑔×ℎ= × 7 = 21
3
𝑃𝑖𝑛𝑣 = 4
 𝑑 = 𝑓 + 𝑃𝑖𝑛𝑣 = 21 + 4 = 25 𝑑𝑒𝑙𝑎𝑦 𝑢𝑛𝑖𝑡𝑠

Q6. Explanation:

4 4 4 64
𝐺 = 𝑔1 × 𝑔2 × 𝑔3 = × × =
3 3 3 27
𝐶𝐿 𝐶
𝐻= = =1
𝐶𝑖𝑛 𝐶

𝐵=1
64 64
𝐹 = 𝐺𝐵𝐻 = ×1×1=
27 27

3
3 64 4
𝑓 = √𝐹 = √ =
27 3

𝑃 =2+2+2=6
4
𝐷 =𝑁×𝐹+𝑃 =3× + 6 = 10 𝑑𝑒𝑙𝑎𝑦 𝑢𝑛𝑖𝑡𝑠
3
Q7. Explanation:

In CMOS technology, NMOS and PMOS devices are fabricated on same substrate.
Q8. Explanation:

CMOS circuits have low static power dissipation.

Q9. Explanation:

In the Twin-tub process of CMOS fabrication following steps are employed

N-well and P-well formation → Gate and Field oxide formation → Source and Drain implantation →
Metallization.

Q10. Explanation:

In CMOS technology, shallow P-well or N-well regions can be formed using low energy ion
implantation.