Department of Electrical Engineering

Digital Logic Design

EE-272L

Lab # 8 Manual

Magnitude Comparator & Multiplexer

Name

Roll No

Marks Obtained

Date Performed

Instructor: Ms. Naureen Shaukat

Lab Engineer: Engr. Maria Rehman

Fall 2023 DLD Lab 08 Version 2.0

Version 1.0-Prepared by Dr. Syed Asad Alam

Version 2.0-Dr. Majid Ali
1. Objectives
The main objective of this lab is to gain an understanding of magnitude comparators and multiplexers.
The students will also learn how to construct a large magnitude comparator using smaller ones.

2. Learning Outcomes
This lab satisfies the following learning outcomes of the course:
• CLO1: Build digital circuits for open-ended, complex, and real-world applications.
• CLO2: Construct combinational and sequential logic circuits using model sim software.

3. Equipment & Components

• Trainer board
• 4–bit magnitude comparator → 7485
• Computer with ModelSim

4. Instructions
• There will be no concept of make-up labs. If missed, the lab may be performed later for practice and
knowledge required for the coming labs on your own and will be graded for partial marks unless there
is any valid reason.
• Plagiarism cases would be sent to the student disciplinary committee (SDC) without any prior
warnings.

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Fall 2023 DLD Lab 08 Version 2.0
5. Introduction
5.1. Magnitude Comparator
A magnitude comparator is made up of standard gates to compare digital signals and produce output
depending on the condition of those signals. It generally has three results, one each for equality (A = B),
greater than (A > B), and less than (A < B).
Commercially available magnitude comparators, like the 7485 4–bit magnitude comparator, have
additional input terminals to allow more individual comparators to be cascaded together to form larger
than 4–bits width. The pin diagram of 7485 is shown in Fig. 1.

Figure 1: Pin diagram of 4–bit magnitude comparator, 7485

5.2. Multiplexer
A multiplexer is a combinational circuit that selects binary information from many input lines and directs
the data to a single output line. A particular input line selection is controlled by a set of input variables,
called selection inputs. Typically, there are 2 n input lines and n selection inputs whose bit combinations
determine selected input. Multiplexers with different inputs are available as discrete ICs. Following is a
brief list of ICs available:

• 2-to-1 line multiplexer → 74157

• 4-to-1 line multiplexer → 74153
• 8-to-1 line multiplexer → 74151

Multiplexers can be implemented using a variety of ways in Verilog. It can be implemented using the
if...else if...else and case statements. Another way to implement multiplexers is using the conditional
operator ? : which can be used within and outside the always block. This operator takes three operands
[2]: Condition ? true-expression : false-expression;

If the evaluated condition results in logic 1, the true expression is evaluated and used to assign a value to
the left-hand side of an assignment statement. If the result is logic 0, the false expression is evaluated. A
simple conditional operator can implement a simple 2-to-1 line multiplexer, but multiple conditional
operators can be nested to allow larger multiplexers.

6. Procedure
6.1. Task 1: 8–bit Magnitude Comparator
Using the 4–bit magnitude comparator IC, 7485, construct an 8–bit magnitude comparator and implement
it on the trainer board. Think of reasons why cascading two 4–bit magnitude comparators results in a8–bit
magnitude comparator. It will be helpful if the following steps are followed:
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Fall 2023 DLD Lab 08 Version 2.0
• Test the given 7485, the 4-bit magnitude comparator IC, to understand its functionality.
• Connect four switches with A3 . . . A0 and four switches with B3 . . . B0.
• Make Vcc and ground connections.
• Connect the three outputs to three LEDs.
• After verification, connect another 7485 IC and make the required connections.

6.2. Task 2: Multiplexer in Verilog HDL

1. Write a Verilog code for 2 x 1 Multiplexer using dataflow modeling.
2. Write a Verilog code for 2 x 1 Multiplexer using behavioral modeling. 3. Write a
Verilog code for 4 x 1 Multiplexer using behavioral modeling
4. Construct an 8 x 1 Multiplexer using seven 2 x 1 Multiplexers.

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Fall 2023 DLD Lab 08 Version 2.0
7. Observations and Conclusion

8. Submissions
You need to submit a hard copy of the manual.

References
[1]. Digital Design: With an Introduction to the Verilog HDL, by M. Morris Mano and Michael D. Ciletti,
5th Edition, Pearson, 2013.

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 Lab Rubrics
Marking Rubric

Performance Excellent 20-17 Good 16-13 Average 12-8 Poor-0 Marks

Successfully performed but

Successfully completed in not with a clear Had difficulty in Not completed about
time with complete understanding, can use lab completing the tasks, can half of the tasks, does
Performance understanding, was good in equipment with minor use some lab equipment not know how to use
using lab equipment. errors. lab equipment.
with errors.
Students answered questions
comprehensively.
Students gave outstanding and Not able to answer to
Exhibited confidence in Students provide basic
detailed answers. asked questions, and
answers. Strong answers to questions.
Showed exceptional was not confident.
understanding of the Somewhere confident,
Lab Viva confidence in responses. No Significant gaps
subject matter. Minimal limited gaps in
significant gaps in in knowledge
gap in knowledge and knowledge and
knowledge and and
comprehension. comprehension.
comprehension. comprehension.

Not very clear

Clean and clear without any Clean and clear but slight and clean, and
Not very clear and clean
match with fellow students overlap with other students most of the
Report and partial
content
overlap with fellow students
overlapping with
fellow students
• Method of Evaluation: Reports submitted by students
• Measured Learning Outcomes:
CLO1: Build Digital Circuits, complex and real-world examples.
CLO3: Present concise yet comprehensive technical reports.