IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO.

12, DECEMBER 2015 2825

An Error-Based Controlled Single-Inductor

10-Output DC-DC Buck Converter With
High Efficiency Under Light Load
Using Adaptive Pulse Modulation
Min-Yong Jung, Sang-Hui Park, Student Member, IEEE, Jun-Suk Bang, and Gyu-Hyeong Cho, Senior Member, IEEE

Abstract—An error-based control method is proposed for a

single-inductor multiple-output (SIMO) converter that maintains
high efficiency under various load conditions. A peak efficiency
of 88.7% was achieved with one output of 5 mA, while the
other outputs are at 432 mA. A hybrid topology composed of a
switching converter and a linear regulator is also presented for
fast load transient response. The proposed SIMO buck converter
was fabricated with a 1P4M 0.35 m BCD process and has 10
independently regulated outputs. The measured load transient
waveform shows cross regulation of 0.1 mV/mA and a load tran-
sient of 0.17 mV/mA. This was achieved under load transient
conditions for one output in between 1 mA and 100 mA
with the other outputs at 422 mA.
Index Terms—Pulse modulation, SIMO, switching converters.

I. INTRODUCTION

R EDUCING the number of large external components, es-

pecially inductors, is a very important issue for power-
management ICs (PMICs). Demand is increasing for PMICs
that occupy a small PCB area and use few external compo-
nents. One very attractive solution is the single-inductor mul-
tiple-output (SIMO) converter shown in Fig. 1(a), which can
supply multiple outputs using only one inductor, enabling sub-
stantial reduction of the PCB area and the number of external
components. However, the SIMO converter has disadvantages
such as poor cross regulation, large ripple, low current capa-
bility, instability, and inefficiency under light load.
One solution for the issue of multi-output regulation used
a pseudo-continuous or discontinuous conduction mode
(PCCM/DCM) single-inductor dual-output (SIDO) boost con-
verter [1]. The PCCM SIDO converter used a freewheeling
period, as shown in Fig. 1(b). However, this method con-
sumes excessive power, and a slow load transient response
and large output ripple are caused by the time-multiplexing
operation, in which an inductor supplies only one output during
Manuscript received April 22, 2015; revised July 09, 2015; accepted
August 15, 2015. Date of publication September 11, 2015; date of current
version November 24, 2015. This paper was approved by Guest Editor
Makoto Takamiya.
The authors are with the Department of Electrical Engineering, KAIST, Dae-
jeon 305-701, Korea.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2015.2471839
Fig. 1. Power stage architecture of the SIMO boost converter (a) with inductor
current waveforms of PCCM control (b) and OPDC control (c).
one switching cycle. To resolve these problems, an ordered
power-distributive controlled (OPDC) SIMO boost converter
was presented [2]. This converter supplies all the outputs
during only one switching cycle, and there is no freewheeling
period, as shown in Fig. 1(c). Thus, high efficiency, fast load
transient, and small ripple were achieved. However, there were
still problems with instability.
The PLL-based controlled SIMO buck converter controls all
outputs except for the last channel by comparator output signals
for high regulation stability and simple control [3]. However, the
last channel, which was controlled by the accumulative error of
the other channels, had problems with poor cross regulation in
load transient conditions. Another control method was proposed
to reduce cross regulation using adaptive energy recovery con-
trol in the SIMO buck converter [4]. The energy recovery du-

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2826
Fig. 2. Power stage architecture of the SIMO boost converter with switching node waveform (a) and the SIMO buck converter with switching node waveform (b).
ration decoupled the sub-channels and operated like a buffer in
transient conditions. However, this increases power consump-
tion like in the SIMO converter with PCCM [1]. The ripple-
based adaptive off-time (RBAOT) control approach changes the
switching frequency of the SIMO converter in transient condi-
tions, and all the outputs are controlled by comparator output
signals [5]. This method achieved good cross regulation and fast
load transient response without excessive power consumption,
but it could not overcome the slew-rate limitation caused by the
inductor.
The comparator-based control method has mostly been used
in previous SIMO buck converters for simplicity of control and
fast load transient response. However, poor cross regulation
has been a critical problem with SIMO converters, along with
inefficiency and regulation instability under light load condi-
tions for any of the outputs. The output voltage ripple of the
SIMO converter is determined by its load conditions and the
load conditions of the other outputs. Since each output load
current is limited to maintain low output voltage ripple, the
SIMO converters are very suitable for light load applications,
and the light load inefficiency and regulation instability must
be improved.
To accomplish this, the switching frequency and the
switching order of the output power switches need to be con-
trolled based on the load conditions. However, it is difficult
to implement such features using conventional SIMO control
methods. As a solution, a new error-based control (EBC)
SIMO converter is proposed. In this method, the switching
frequency and switching order of the output power switches are
arbitrarily controlled according to each error while achieving
high light-load efficiency and regulation stability.
The paper is organized as follows. The conventional com-
parator-based control method is discussed in Section II. Then,
the proposed EBC and a time-based multi-input comparator
used for the control method are presented in Section III. A
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015
hybrid topology is presented in Section IV to improve cross
regulation in transient conditions. In Section V, the circuit
implementations of the proposed EBC and hybrid topology
are discussed. The measurement results and a performance
comparison are provided in Section VI. Finally, the conclusion
follows in Section VII.
II. CONVENTIONAL COMPARATOR-BASED CONTROLLED
SIMO BUCK CONVERTER
A. Two Controllers of the SIMO Buck Converter
Unlike a SIMO boost converter, a SIMO buck converter re-
quires a set of input power switches and a set of output power
switches. As shown in Fig. 2(a), the average voltage of
can be adjusted to based on the on-time of . The
average voltage of is determined by the output load
conditions and is lower than , as shown in Fig. 2(b).
The average voltage of should be adjusted to that of
using either the total output error information or the in-
ductor current information. The SIMO buck converter requires
two control loops for the input power switch controller and the
output power switch controller, as shown in Fig. 3.
The output power switch controller operates such that each
output error is reduced to zero, and the input power switch con-
troller controls the average voltage of . The EBC is pro-
posed to control the output power switches to achieve high effi-
ciency and high regulation stability under light load conditions.
A hybrid topology is also used for input power switch control
to achieve good cross regulation.
B. Major Performance Barriers in Conventional
Comparator-Based Control
Fig. 4 shows the operational principle of a conventional com-
parator-based controlled SIMO buck converter with a timing di-
agram. Each output voltage of the converter is regulated by each
JUNG et al.: AN ERROR-BASED CONTROLLED SINGLE-INDUCTOR 10-OUTPUT DC-DC BUCK CONVERTER 2827

Fig. 3. System block diagram of the SIMO buck converter with two power switches controllers.

Fig. 4. Architecture of the conventional comparator-based controlled SIMO buck converter with timing diagram.

comparator output signal. Thus, this converter has high regula-
tion stability, fast load transient response, and good cross regu-
lation. The controller architecture and operational principle are
simple and straightforward. Under normal load conditions, on
which the design of previous SIMO converters is mainly based,
the converter shows good cross regulation, high regulation sta-
bility, and high efficiency. However, under the light load condi-
tions mainly considered in this work, there are issues with low
efficiency and regulation stability.
1) Low Efficiency: The switching loss of the output power
switch is substantial in the SIMO converter and seriously de-
grades the efficiency of the SIMO converter under light load
conditions. To achieve high efficiency under such conditions,
the switching frequency of each output power switch should be
controlled based on the load conditions. However, the switching
frequency of each output power switch remains the same, re-
gardless of the load conditions (Fig. 4). This reduces efficiency
for any output under light load.
2) Regulation Stability: During on and off operation of an
output power switch, switching noise appears due to parasitic
inductance, as shown in Fig. 5. This switching noise directly
affects the comparator operation. Under heavy load, the noise
is not a significant problem because the output ripple voltage is
large compared to the switching noise. However, the switching
noise causes regulation issues under light load because the
output voltage ripple is reduced. The regulation issues also
appear when any output is under no load condition because
the output receives energy from the inductor in every cycle
despite the load conditions. Unregulated output caused by
such conditions affects the other outputs because the input
power switch controller operates using the total output error
information, including inexact error.
III. ERROR-BASED CONTROLLED SIMO BUCK CONVERTER
A. Operational Principle of EBC
The proposed controller is composed of an error generation
block ( through ) and an error comparison block
(Fig. 6). The error generation block generates information
about the error ( through ), which is used by the

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2828 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015

Fig. 5. Output voltage waveform with switching noise.

Fig. 6. Architecture of the proposed error-based controlled SIMO buck converter with timing diagram.

maximum error selector. Then, the maximum error selector where Dmax is the maximum difference between the average
turns on the output power switch with the largest error by output errors caused by the non-ideal characteristics of the
comparing the error information. maximum error selector and the SIMO converter operation. As
The principle of the proposed EBC is illustrated with a timing mentioned, the input power switch controller is a current-mode
diagram example in Fig. 6. First, the maximum error selector controller that operates so that the total output error becomes
compares through for time duration A. During zero. This is made possible by controlling the inductor current,
this time, is the largest in this example, so the maximum because the total output error is caused by the difference be-
error selector turns on for a fixed time. For time duration tween the inductor current and total output load current. So,
B, the maximum error selector compares through the following equation is established by the input power switch
again. Since is still the largest, the maximum error se- controller:
lector maintains the on-state of for a fixed time. The max-
imum error selector compares through again for
time duration C. During this time, is the largest, so the
maximum error selector turns on . This operation cycle is
(3)
repeated by , which is the clock signal of the maximum
error selector.
By repeating these operations, the difference between the av- where is the average error caused by the non-ideal char-
erage output errors is limited by the maximum acteristics (offset and gain error) of the input power switch con-
error selector. Thus, the following inequalities are established: troller. Based on inequality (1) and (2), the following inequality
can be derived:

(1)

(2) (4)

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JUNG et al.: AN ERROR-BASED CONTROLLED SINGLE-INDUCTOR 10-OUTPUT DC-DC BUCK CONVERTER 2829

Fig. 7. Operation principle and schematic of the maximum error selector with timing diagram.

Based on (3), the following equations can be derived: ison accuracy of the selector, and the load transient performance
is related to the comparison speed of the maximum error se-
lector. However, a conventional comparator can compare only
two inputs and requires high power consumption for high com-
(5) parison speed. To overcome these disadvantages, a time-based
multi-input comparator is presented, as shown in Fig. 7. This
Based on (5) and inequality (4), the following inequality can be
comparator is composed of capacitors ( through )
derived:
and digital circuits. After all the switches ( through )
are turned off by , which operates at a constant fre-
quency, each capacitor is charged by the error signals (
(6) through ), which are transformed to currents by the error
generation block ( through ). Since all the capacitance
Based on inequalities (6), (1) and (2), the following inequalities values are the same, each charging slope is determined by each
can be derived: error current. After the first is the first to reach
the threshold voltage (Vth) of the inverter, and the rising edge of
the inverter output generates clock signal because
is the largest during this time. With the given signal,
(7)
is turned on. Immediately after this operation, all the capacitors
are discharged by the set signal . This cycle is repeated by
the reset signal .
(8)
C. Performance Improvement of EBC
As shown in the inequalities (6) through (8), all of the average
output voltages ( through converge to their re- The outputs of conventional comparator-based controlled
spective reference voltages ( through ) when the SIMO buck converters are regulated by direct comparison
difference between the output errors is zero and the average between each output voltage and each reference voltage.
error caused by the non-ideal characteristics of the input power Furthermore, the switching order of output power switches is
switch controller is zero. Otherwise, these non-ideal character- fixed, regardless of load conditions. In contrast, the outputs of
istics cause regulation errors. the proposed error-based controlled SIMO buck converter are
regulated by comparison between errors. This enables control
B. Maximum Error Selector Operation Scheme of the output switching frequencies and their switching order
The maximum error selector design is very important because based on the load conditions, which is difficult to do using
the output regulation performance is determined by the compar- conventional SIMO control methods.

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2830
Fig. 8. Output waveforms of comparator-based controlled SIMO converter (a) and error-based controlled SIMO converter (b).
1) High Efficiency under Various Load Conditions:
Figs. 8(a) and (b) show the output waveforms of the com-
parator-based controlled SIMO converter and the error-based
controlled SIMO converter, respectively. The ripples are
exaggerated in these figures. These waveforms show that
each output voltage has a different declining slope for each
output load condition. The switching frequencies of the output
switches with EBC vary according to the load conditions,
while the switching frequency is fixed with comparator-based
control. The reason is that the outputs of the proposed converter
are regulated by comparing the output errors, which imply the
load conditions. Thus, the switching operation is related to each
load condition.
In the example in Fig. 8(b), the declining slope of is
sharp because of the heavy load. Therefore, switching happens
more frequently than for other outputs. In contrast, the declining
slope of is very gradual, which means that is under
light load, so the switching frequency of is reduced. The
switching frequency of each output switch is determined ac-
cording to each load condition, which enables the error-based
controlled SIMO converter to maintain high efficiency regard-
less of outputs under light load.
2) High Regulation Stability: To achieve high regulation
stability, pulse skipping should be done under extremely light
loads, which is done automatically by the proposed EBC. An-
other requirement is robustness to switching noise. As shown
in Fig. 7, switching occurs after the error comparison operation.
By separating the error comparison time and switching time,
the proposed converter has low vulnerability to switching noise.
The capacitors used for the maximum error selector also act as
a low-pass filter during the comparison operation and increase
the regulation stability.
3) Fast Load Transient Response: Fixed output switching
order like in the conventional control methods slows down the
load transient response because the outputs have to wait for their
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015
turn in the cycle. However, since the switching order of the
EBC changes according to the load, the load transient response
is much faster because the output under transient load is con-
trolled immediately. However, this cannot overcome the limi-
tations regarding slew rate and unity-gain bandwidth caused by
the inductor. To overcome these performance barriers for good
cross regulation, a hybrid topology is presented.
However, varying the switching frequency would complicate
the EMI filter design like in the case of pulse frequency mode
operation of conventional converters. The EBC shows higher ef-
ficiency than the conventional control methods when the differ-
ences in load current among the outputs are large. If all outputs
have similar load conditions, the operation of the EBC is similar
to that of the conventional control method, and there would be
no particular advantage.
IV. HYBRID TOPOLOGY
A. System Block Diagram of the Proposed Hybrid Topology
This section introduces the hybrid topology for the input
power switch controller. Fig. 9 shows the overall system block
diagram of the proposed converter with the hybrid topology,
which consists of a linear regulator and a current mode buck
converter. All the output load currents are supplied by the hy-
brid topology based on the total error information .
A linear regulator reduces the total error to zero,
and the current-mode buck converter is controlled so that
the low-frequency component of the linear regulation current
also becomes zero. Therefore, the low-frequency output
load current is supplied by the buck converter, and the high-fre-
quency component of the output load current is supplied by
the linear regulator. In other words, all of the steady-state load
current is supplied by the buck converter, and the transient load
current is supplied by the linear regulator.
JUNG et al.: AN ERROR-BASED CONTROLLED SINGLE-INDUCTOR 10-OUTPUT DC-DC BUCK CONVERTER 2831

Fig. 9. System block diagram of the SIMO buck converter with the proposed hybrid topology.

Fig. 10. Simplified block diagram of the proposed SIMO buck converter with hybrid topology.

When a load transient happens, the linear regulator sup- the bias current of the linear regulator is not negligible when all
plies transient current based on the total error information of the load currents are under light load.
. The control voltage is then changed by the
current sensor of the linear regulator and the integrator. B. Loop Analysis of the Hybrid Topology
increases since the inductor current is controlled by the control Fig. 10 shows a simplified block diagram of the proposed
voltage , which is the output of the integrator. Then, is SIMO buck converter. The error generation block is composed
decreased to zero by the feedback loop. of operational transconductance amplifiers (OTAs) connected in
In steady-state conditions, there is no efficiency degradation parallel. The block can be represented by the transconductance
without the bias current of the linear regulator, because all the of the linear regulator , the output impedance of the par-
output currents are supplied by the buck converter. In the tran- allel OTAs, and the parasitic capacitance . The linear regu-
sient condition, the transient current is supplied by the linear lator operates based on . is the current sensor
regulator. Therefore, the cross regulation can be reduced by the gain of the linear regulator output current , and and
fast load transient response of the linear regulator. Under normal are the DC gain and the cutoff frequency of the inte-
load, the power loss caused by the linear regulator is negligible. grator, respectively. denotes the gain defined from the con-
However, it increases when load transients occur frequently be- troller voltage to the inductor current is
cause transient current is supplied by the linear regulator. Also, the output filtering capacitor, and is the output load. Based

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2832 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015

Fig. 11. Overall architecture of the 10-output SIMO buck converter.

on this simplified block diagram, the transfer function of the

overall loop gain T(s) can be derived as:

(9)

where

(10)

(11)
(12) Fig. 12. Schematic of error generation block.

(13)

As shown by the transfer function in (9), the overall loop con- converter and is generated by the parasitic capacitor and
tains two poles at and and one zero at within the output impedance of the parallel OTAs. An important point
the frequency range of interest. is the high-frequency pole of the hybrid topology is that the overall DC gain is increased
when considering the unity-gain bandwidth of the SIMO buck by a factor of , and an additional zero is generated. In

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JUNG et al.: AN ERROR-BASED CONTROLLED SINGLE-INDUCTOR 10-OUTPUT DC-DC BUCK CONVERTER 2833

Fig. 13. Operational timing diagram and detailed schematic of maximum error selector.

the EBC, the overall DC gain affects the regulation errors be- the need for nine additional inductors that would be required in
cause each output is regulated by each error, as mentioned in conventional buck converters.
Section III. Thus, high DC gain is required to reduce the regula- The error generation block consists of 10 OTAs, as shown in
tion errors and can be achieved using the hybrid topology. The Fig. 12. The error generation block generates to
proposed SIMO converter can achieve a wide unity-gain band- and using each output voltage ( through )
width through the additional zero and high DC gain from the and each reference voltage ( through ). The
topology. maximum error selector uses to , and the hybrid
Another important advantage of the hybrid topology is the topology uses .
high slew rate in transient conditions. The slew rate of a con-
ventional SIMO buck converter is limited by the inductor. To B. Maximum Error Selector
overcome this, the converter can be designed with a small in- Fig. 13 shows how the maximum error selector is used in the
ductor or high switching frequency. However, these approaches 10-output SIMO buck converter with detailed schematics and
cause large output ripple and low efficiency in steady state. The operational timing diagrams. The bottom left of Fig. 13 shows
proposed hybrid topology can overcome the slew-rate limitation each output voltage waveform ( through ) represented
by using the linear regulator in transient conditions. Therefore, by magnifying the ripple component. The declining slope dif-
cross regulation can be improved with the topology by sacri- fers for each output load condition. After all the switches (
ficing some power. through ) are turned off by the reset signal , which
operates at a constant frequency of 2.5 MHz, each capacitor
V. CIRCUIT IMPLEMENTATION ( through ) is charged by each error current source
( through ). For high comparison speed with low
A. Proposed SIMO Buck Converter Architecture power consumption, a small 50 fF capacitor is used.
The overall architecture of the proposed SIMO buck con- After the first reset signal is the first to
verter is shown in Fig. 11. It is composed of 10 output channels, reach the threshold voltage (Vth), and the rising edge of
the error generation block, the maximum error selector, and the generates a clock signal because is the largest
hybrid topology. To highlight its advantages, the proposed con- during this time. Then, only the D flip-flop output (P5) of
verter was designed with 10 buck outputs. This design negates the 5th channel becomes high, whereas the others become

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2834
Fig. 14. Monte Carlo simulation results of the maximum error selector.
Fig. 15. 10-output SIMO converter with detailed schematic of hybrid topology.
low because the input voltages of the other inverters do not
reach the threshold voltage. Immediately after this operation,
all the capacitors are discharged by set signal , which
is generated by the delay cell and clock signal . This
operation cycle is repeated by reset signal . Through
this simple procedure, the maximum error selector turns on the
output power switch with the largest error.
The protection block is designed to prevent the following
cases. The first case is when more than two errors are the same
and larger than the other errors, which would make the max-
imum error selector turn on more than the two output power
switches simultaneously. To prevent this situation, the protec-
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015
tion block turns on only one switch with priority assigned in
advance such a situation. The other case is when all the input
voltages do not reach the threshold voltage in an unpredictable
situation. To prevent all the output switches from being turned
off, the protection block turns on the switch which was previ-
ously chosen to be turned on in such a situation.
Fig. 14 shows the results of a Monte Carlo simulation of the
maximum error selector. In the simulation, the input error volt-
ages to ranged from 30 mV to mV in 5
mV intervals. Ideally, all the output results should be ,
because is the largest error. However, the Monte Carlo
simulation results show that the maximum error selector has an
JUNG et al.: AN ERROR-BASED CONTROLLED SINGLE-INDUCTOR 10-OUTPUT DC-DC BUCK CONVERTER 2835

Fig. 16. Chip microphotograph.

Fig. 17. Measured steady-state waveforms.

offset error caused by the OTAs and the threshold voltage of the
inverter mismatch and capacitor mismatch. The worst output
offset voltage was 30 mV in the simulation.
C. Hybrid Topology
The hybrid topology is composed of a current mode switching
converter and a linear regulator, as shown in Fig. 15. To ob-
tain a high rising and falling slew rate, a Class-AB amplifier is
used as the linear regulator. The current mode switching con-
verter supplies all the load current in steady-state conditions.
However, when a load transient happens, the Class-AB ampli-
fier supplies the transient current because changes
the current of the amplifier so that becomes
zero. The control voltage is then changed by integration of
the mirror current of the Class-AB amplifier output stage to in-
crease the switching converter current. This should happen as
soon as possible so that the current of the Class-AB amplifier
decreases to zero in a short time. Since the load transient re-
sponse of the amplifier is faster than that of the switching con-
verter, cross regulation is improved.
VI. FABRICATION AND EXPERIMENTAL RESULTS
The proposed 10-output SIMO buck converter was fabricated
with a 1P4M 0.35 m BCD process. The chip micrograph is

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2836 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015

Fig. 18. Measured waveforms under load transient condition.

shown in Fig. 16. to were regulated to 3.3 V, 3.3 V, performance was achieved with the SIMO converter supplying
3.3 V, 2.8 V, 2.8 V, 2.5 V, 2.5 V, 1.8 V, 1.8 V, and 1.8 V, respec- 10 buck outputs and the transient current changing from
tively. To verify how the proposed EBS works under various very light load. The output waveforms also show that the
load conditions, to were set to 5 mA, 50 mA, 75 mA, switching frequency of adaptively changes according to
17 mA, 100 mA, 25 mA, 50 mA, 20 mA, 15 mA, and 80 mA, re- the rapid load transient.
spectively. Fig. 17 shows the measured steady-state waveforms. Fig. 19 shows the measured efficiency and the switching fre-
The waveform of the switching node clearly shows that quency of the converter. Even if one output is under very light
all the outputs are properly regulated even when several outputs load ( mA), a peak efficiency of 88.7% is achieved
are under light load. The maximum output ripple is 40 mV and when the supply voltage is 5 V. When supply voltage is
the total output load current is 437 mA, which are normal load 4 V, the efficiency is degraded due to the increased conduction
conditions for our application. The output ripple is proportional loss of the power transistor. In addition to the peak efficiency,
to the total load current. the converter maintains high efficiency under varying . Since
The output waveforms of through show that the switching frequency of each output is controlled by the EBC
each output has a different declining slope and switching according to the load, the efficiency of the proposed SIMO buck
frequency depending on the load. These waveforms show that converter is improved. However, if all of the load currents are
the switching frequency of each output is properly controlled the same, the switching frequency would be the same as that of
by the EBC for high efficiency under light load. Fig. 18 shows a conventional comparator-based control method, and the EBC
the measured waveforms under load transient conditions for would have no particular advantage. In addition, the measured
values of the output between 15 mA and 200 mA and switching frequency variation of with varying shows
between 1 mA and 100 mA, which correspond to total load that the switching frequency has a very linear relationship with
current changes of 437 mA to 622 mA and 423 mA to 522 mA, the load current.
respectively. When is varied from very light load to heavy Table I compares the performance of the SIMO converter
load, the output waveforms show that each output is properly with previous reports. The previous approaches show fast load
regulated. The load transient waveform of shows 17 mV transient response and good cross regulation under normal load
overshoot for between 1 mA and 100 mA. The cross conditions. To meet the demands for high stability and high effi-
regulation values of for these ranges of are only ciency under light load, the load transient performance and the
0.1 mV/mA in the transient, respectively. This load transient efficiency were measured under a load current changing from

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JUNG et al.: AN ERROR-BASED CONTROLLED SINGLE-INDUCTOR 10-OUTPUT DC-DC BUCK CONVERTER
Fig. 19. Measured efficiency plot and switching frequency versus load current.
TABLE I
PERFORMANCE SUMMARY OF THE SIMO CONVERTER IN COMPARISON WITH THOSE OF PREVIOUS PUBLICATIONS
very light load (1 mA) in this work. Under these load transient
conditions, the measured waveforms show cross regulation of
0.1 mV/mA and a load transient of 0.17 mV/mA while main-
taining high efficiency under light load.
VII. CONCLUSION
This paper presented an error-based controlled SIMO con-
verter with high efficiency under light load and high regulation
stability. Using this method, the proposed SIMO buck converter
achieves a peak efficiency of 88.7 % and maintains high effi-
ciency in a wide load range. The converter can also supply 10
various outputs due to the high regulation stability obtained by
the EBC. The load transient responses were also improved with
the proposed hybrid topology at the cost of some power loss.
Due to the operation of the linear regulator in load transient con-
ditions, a cross regulation of 0.1 mV/mA and a load transient of
0.17 mV/mA were achieved.
Authorized licensed use limited to: Ahmed Kamal. Downloaded on October 13,2021 at 15:30:14 UTC from IEEE Xplore. Restrictions apply.
2837
REFERENCES
[1] D. Ma, W.-H. Ki, and C.-Y. Tsui, “A pseudo-CCM/DCM SIMO
switching converter with freewheel switching,” IEEE J. Solid-State
Circuits, vol. 38, no. 6, pp. 1007–1014, June 2003.
[2] H.-P. Le, C.-S. Chae, K.-C. Lee, S.-W. Wang, G.-H. Cho, and G.-H.
Cho, “A single-inductor switching DC-DC converter with five outputs
and ordered power-distributive control,” IEEE J. Solid-State Circuits,
vol. 42, no. 12, pp. 2706–2714, Dec. 2007.
[3] K.-C. Lee, C.-S. Chae, G.-H. Cho, and G.-H. Cho, “A PLL-based high-
stability single-inductor 6-channel output DC-DC buck converter,” in
IEEE ISSCC Dig. Tech. Papers, 2010, pp. 200–201.
[4] C.-W. Kuanand and H.-C. Lin, “Near-independently regulated
5-output single-inductor DC-DC buck converter delivering 1.2
W/mm in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2012,
pp. 274–276.
[5] D. Lu, Y. Qian, and Z. Hong, “An 87% peak efficiency DVS-capable
single-inductor 4-output DC-DC buck converter with ripple-based
adaptive off-time control,” in IEEE ISSCC Dig. Tech. Papers, 2014,
pp. 82–83.
[6] “On Semiconductor, Secondary Side Post Regulator (SSPR) for
Switching Power Supplies With Multiple Outputs,” Cirrus Logic,
CS5101AN/D datasheet, Apr. 2001.
[7] Y. Zhang and D. Ma, “A fast-response hybrid SIMO power converter
with adaptive current compensation and minimized cross-regulation,”
IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1242–1255, May 2014.
2838
[8] P. Riehl, P. Fowers, H.-P. Hong, and M. Ashburn, “An AC-coupled hy-
brid envelope modulator for HSUPA transmitters with 80% modulator
efficiency,” in IEEE ISSCC Dig. Tech. Papers, 2013, pp. 364–365.
[9] M.-Y. Jung, S.-H. Park, J.-S. Bang, D.-C. Park, S.-U. Shin, and G.-H.
Cho, “An error-based controlled single-inductor 10-output DC-DC
buck converter with high efficiency at light load using adaptive pulse
modulation,” in IEEE ISSCC Dig. Tech. Papers, 2015, pp. 222–223.
[10] Y.-J. Woo, H.-P. Le, G.-H. Cho, and G.-H. Cho, “Load-indepen-
dent control of switching DC-DC converters with freewheeling
current feedback,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.
2798–2808, Dec. 2008.
[11] Y.-P. Su et al., “90% peak efficiency single-inductor-multiple-output
DC-DC buck converter with output independent gate drive control,” in
IEEE ISSCC Dig. Tech. Papers, 2015, pp. 224–225.
[12] E. Siragusa and I. Galton, “A digitally enhanced 1.8 V 15 b 40 MS/s
CMOS pipelined ADC,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp.
452–453.
[13] M. Belloni et al., “A 4-output single-inductor DC-DC buck converter
with self-boosted switch drivers and 1.2 A total output current,” in
IEEE ISSCC Dig. Tech. Papers, 2008, pp. 444–445.
[14] R. Hogervorst, J. P. Tero, R. G. G. Eschauzier, and H. Huijsing, “A
compact power-efficient 3 V CMOS rail-to-rail input/output opera-
tional amplifier for VLSI cell libraries,” IEEE J. Solid-State Circuits,
vol. 29, no. 12, pp. 1505–1513, Dec. 1994.
[15] R. W. Erickson and D. Maksimovic, Fundamentals of Power Elec-
tronics. Norwell, MA, USA: Kluwer, 2001.
[16] X. Jing, P. K. T. Mok, and M. C. Lee, “A wide-load-range constant-
charge-auto-hopping control single-inductor-dual-output boost regu-
lator with minimized cross-regulation,” IEEE J. Solid-State Circuits,
vol. 46, no. 10, pp. 2350–2362, Oct. 2011.
[17] M.-H. Huang and K.-H. Chen, “Single-inductor multi-output (SIMO)
DC-DC converters with high light-load efficiency and minimized
cross-regulation for portable devices,” IEEE J. Solid-State Circuits,
vol. 44, no. 4, pp. 1099–1111, Apr. 2009.
Min-Yong Jung received the B.S. degree in electrical
engineering from Pusan national University, Pusan,
Korea, in 2010, and the M.S. degree in electrical en-
gineering from Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, Korea, in 2013.
He is currently working toward the Ph.D. degree in
electrical engineering at KAIST.
His research interests are in the field of analog inte-
grated circuit design, including the design and mod-
eling of power management IC, linear regulator, and
bandgap voltage reference.
Authorized licensed use limited to: Ahmed Kamal. Downloaded on October 13,2021 at 15:30:14 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 12, DECEMBER 2015
Sang-Hui Park (S’10) received the B.S. degree in
electrical engineering from Korea University, Seoul,
Korea, in 2010, and the M.S. degree in electrical en-
gineering from Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, Korea, in 2012.
He is currently working toward the Ph.D. degree in
electrical engineering at KAIST.
His research interests are in the field of analog
integrated circuit design, including the design and
modeling of touch screen readout circuits, switched
capacitor circuits, power management IC, and
AMOLED display drivers.
Jun-Suk Bang received the B.S. degree from
Hanyang University, Seoul, Korea, in 2011, and
the M.S. degree from Korea Advanced Institute of
Science and Technology (KAIST), Daejeon, Korea,
in 2014. He is currently working toward the Ph.D.
degree in the Department of Electrical Engineering,
KAIST.
His research interests include analog circuit
designs for AMOLED displays and sensing circuits
and biomedical CMOS ICs.
Gyu-Hyeong Cho (S’76–M’80–SM’11) received
the B.S. degree from Hanyang University, Korea,
and the M.S. and Ph.D. degrees from the Korea
Advanced Institute of Science and Technology
(KAIST) in 1975, 1977, and 1981, respectively, all
in electrical engineering.
During 1982–1983, he was with the Westinghouse
R&D Center in Pittsburgh, PA, USA. In 1984, he
joined the Department of Electrical Engineering at
KAIST where he has been a full Professor since
1991. His early research was in the area of power
electronics until the late 1990s and worked on soft switching converters and
high power converters. Later, he shifted to analog integrated circuit design,
and now he is interested in several areas including power management ICs,
Class-D amplifiers, touch sensors and drivers for AMOLED and LCD flat panel
displays, biosensors and wireless power transfer systems. He has authored one
book on advanced electronic circuits and authored or coauthored over 200
technical papers and 80 patents.
Dr. Cho received the Outstanding Teaching Award from KAIST. He served
as a member of the ISSCC international technical program committee, and is
now an associate editor of IEEE JOURNAL OF SOLID-STATE CIRCUITS. At the
ISSCC 60th Anniversary in 2013, he was awarded the ISSCC Author-Recogni-
tion Award as one of the top 16 contributors of the conference.