BIRLA VISHWAKARMA MAHAVIDYALAYA

ELECTRONICS AND COMMUNICATION DEPARTMENT

Certificate
This is to certify that Mr. with ID. No. of Electronics &
Communication has satisfactorily completed all the practicals in the
subject of 2EC08-Simulation & Design Tools.

Subject In-Charge Head of Department

(Prof. Anish Vohra) (Dr. Bhargav C. Garodia)

1
 INDEX

Sr. No. Aim Page no.

1(a). Introduction to OrCAD Capture. 3

To simulate circuits using resistive components using stimulation

1(b). 3
tool.

2. To simulate different clipping circuits and observe the waveform. 7

To simulate different clamping circuits and observe the

3. 18
waveform.

4. To simulate diode as a half-wave rectifier circuit. 25

5. To simulate diode as a full-wave rectifier circuit. 28

6. To simulate diode as a bridge-wave rectifier circuit. 31

7. To simulate diode characteristics. 34

8. To simulate transistor characteristics. 37

9. To simulate transistor as an amplifier. 40

10. To simulate op-amp circuit. 43

11. To simulate all Logic Gates. 47

12. To simulate NAND & NOR as a universal gate. 51

13. To simulate 3-bit Synchronous Up Counter. 57

14. To simulate Full Adder & Half Adder Circuit. 59

2
 EXPERIMENT-1

AIM: - To simulate circuits using resistive components using stimulation tool.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Kirchhoff’s Voltage Law:

Kirchhoff’s Voltage Law (KVL) is Kirchhoff’s second law that deals with the conservation of energy
around a closed, circuit path. Kirchhoff’s voltage law states that the algebraic sum of the potential
differences in any loop must be equal to zero as: ΣV = 0.

Since the two resistors, R1 and R2 are wired together in

a series connection, they are both part of the same loop
so the same current must flow through each resistor.
Thus, the voltage drop across resistor, R1 = I*R1 and the
voltage drop across resistor, R2 = I*R2 giving by KVL:

We can see that applying Kirchhoff’s Voltage Law to this single closed loop produces the formula for
the equivalent or total resistance in the series circuit and we can expand on this to find the values of the
voltage drops around the loop.

The theory behind Kirchhoff’s second law is also known as the law of
conservation of voltage, and this is particularly useful for us when dealing
with series circuits, as series circuits also act as voltage dividers and the
voltage divider circuit is an important application of many series circuits.

3
Kirchhoff’s Current Law

Kirchhoff’s Current Law (KCL) is Kirchhoff’s first law that deals with the conservation of charge
entering and leaving a junction.

Here in this simple single junction example, the current IT leaving

the junction is the algebraic sum of the two
currents, I1 and I2 entering the same junction. That is IT = I1 + I2.

Note that we could also write this correctly as the algebraic sum
of: IT – (I1 + I2) = 0.

So if I1 equals 3 amperes and I2 is equal to 2 amperes, then the total current, IT leaving the junction will
be 3 + 2 = 5 amperes, and we can use this basic law for any number of junctions or nodes as the sum of
the currents both entering and leaving will be the same.

Also, if we reversed the directions of the currents, the resulting equations would still hold true for I 1 or
I2. As I1 = IT – I2 = 5 – 2 = 3 amps, and I2 = IT – I1 = 5 – 3 = 2 amps. Thus, we can think of the currents
entering the junction as being positive (+), while the ones leaving the junction as being negative (-).

Then we can see that the mathematical sum of the currents either entering or leaving the junction and
in whatever direction will always be equal to zero, and this forms the basis of Kirchhoff’s Junction
Rule, more commonly known as Kirchhoff’s Current Law, or (KCL).

We used Kirchhoff’s Current Law here to show how it is possible to solve more complex circuits
when we cannot just simply apply Ohm’s Law.

PROCEDURE: -

1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

4
 Netlist:

R_R1 N00147 N00154 4k TC=0,0

R_R2 N00154 N00158 4k TC=0,0
R_R3 N00158 0 4k TC=0,0
R_R4 0 N00154 4k TC=0,0
R_R5 0 N00158 4k TC=0,0
V_V1 N00147 0 12v
R_R10 0 N00656 4k TC=0,0
R_R7 N00642 N00656 4k TC=0,0
R_R6 N00632 N00642 4k TC=0,0
R_R8 N00656 0 4k TC=0,0
R_R9 0 N00642 4k TC=0,0
V_V2 N00632 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R14 0 N01260 4k TC=0,0
R_R12 N01260 N01274 4k TC=0,0
R_R11 N01250 N01260 4k TC=0,0
R_R15 0 N01274 4k TC=0,0
R_R13 N01274 N01288 4k TC=0,0
V_V3 N01250 0 12V
V_V4 N01288 0 10V

CIRCUIT 1: Analysis type:

R1 R2 R3

12.00V 1.875mA 750.0uA 375.0uA

4k 4k 4k

4.500V 1.500V
V1
12v 1.125mA 375.0uA
R4 R5
0V
4k 4k
1.875mA

CIRCUIT 2: Analysis type:

R11 R12 R13

12.00V 1.563mA 125.0uA 1.188mA

4k 4k 4k

10.00V
5.750V 5.250V
V3 V4
12V 1.438mA 1.313mA 10V
R14 R15
4k 4k
1.563mA 1.188mA

0V
0

5
 CIRCUIT 3: Result:

R6 R7 R8

4k 4k 4k
V V V

V2
VOFF = 0v
VAMPL = 10v R9 R10
FREQ = 50hz 4k 4k
AC = 0

Analysis type:

CONCLUSION: - The conclusion of this experiment proves that Kirchhoff's laws are true.

6
 EXPERIMENT-2

AIM: - To simulate different clipping circuits and observe the waveform.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Diode Clipping Circuits

The Diode Clipper, also known as a Diode Limiter, is a wave shaping circuit that takes an input
waveform and clips or cuts off its top half, bottom half or both halves together.

Positive Diode Clipping Circuits

In this diode clipping circuit, the diode is forward biased (anode more positive than cathode) during the
positive half cycle of the sinusoidal input waveform. For the diode to become forward biased, it must
have the input voltage magnitude greater than +0.7 volts (0.3 volts for a germanium diode).

Negative Diode Clipping Circuits

Here the reverse is true. The diode is forward biased during the negative half cycle of the sinusoidal
waveform and limits or clips it to –0.7 volts while allowing the positive half cycle to pass unaltered
when reverse biased. As the diode limits the negative half cycle of the input voltage it is therefore called
a negative clipper circuit.

7
Clipping of Both Half Cycles

If we connected two diodes in inverse parallel as shown, then both the positive and negative half cycles
would be clipped as diode D1 clips the positive half cycle of the sinusoidal input waveform while
diode D2 clips the negative half cycle. Then diode clipping circuits can be used to clip the positive half
cycle, the negative half cycle or both.

Positive Bias Diode Clipping

Likewise, by reversing the diode and the battery bias voltage, when a diode conducts the negative half
cycle of the output waveform is held to a level –VBIAS – 0.7V as shown.

Negative Bias Diode Clipping

A variable diode clipping or diode limiting level can be achieved by varying the bias voltage of the
diodes. If both the positive and the negative half cycles are to be clipped, then two biased clipping
diodes are used. But for both positive and negative diode clipping, the bias voltage need not be the
same. The positive bias voltage could be at one level, for example 4 volts, and the negative bias voltage
at another, for example 6 volts as shown.

Combination Clipper
When a portion of both positive and negative of each half cycle of the input voltage is to be clipped (or
removed), combination clipper is employed. The circuit for such a clipper is given in the figure below.

8
PROCEDURE:

1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST:

V_V2 N00865 0 AC 0
+SIN 0v 10v 50hz 0 0 0
D_D1 N00865 N00972 D1N4001
R_R1 0 N00972 1k TC=0,0
R_R2 N00865 N00865 1k TC=0,0
D_D2 N01315 N01297 D1N4001
R_R4 0 N01315 1k TC=0,0
V_V3 N01297 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R3 N01297 N01297 1k TC=0,0
R_R6 0 N01685 1k TC=0,0
V_V4 N01669 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R5 N01669 N01685 1k TC=0,0
D_D3 N01685 0 D1N4001
D_D4 0 N02128 D1N4001
R_R7 N02116 N02128 1k TC=0,0
R_R8 0 N02128 1k TC=0,0
V_V5 N02116 0 AC 0
+SIN 0v 10v 50hz 0 0 0
D_D5 N02508 N02731 D1N4001
R_R10 0 N02508 1k TC=0,0
V_V6 N02496 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R9 N02496 N02508 1k TC=0,0
V_V7 N02731 0 2V
R_R12 0 N03014 1k TC=0,0
R_R11 N03002 N03014 1k TC=0,0
V_V9 0 N03110 2V
D_D6 N03014 N03110 D1N4001
V_V8 N03002 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R14 0 N03475 1k TC=0,0
V_V11 N03571 0 2V
V_V10 N03463 0 AC 0
+SIN 0v 10v 50hz 0 0 0
D_D7 N03571 N03475 D1N4001
R_R13 N03463 N03475 1k TC=0,0
D_D8 N03996 N03900 D1N4001
V_V13 0 N03996 2V

9
R_R16 0 N03900 1k TC=0,0
V_V12 N03888 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R15 N03888 N03900 1k TC=0,0
R_R18 0 N04341 1k TC=0,0
D_D9 N04337 N04341 D1N4001
V_V14 N04321 0 AC 0
+SIN 0v 10v 50hz 0 0 0
V_V15 N04337 N04321 2V
R_R19 0 N04341 1k TC=0,0
D_D10 N05021 N05027 D1N4001
V_V16 N05009 N05021 2V
R_R20 0 N05027 1k TC=0,0
R_R21 0 N05027 1k TC=0,0
V_V17 N05009 0 AC 0
+SIN 0v 10v 50hz 0 0 0
V_V19 N05473 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R22 0 N05497 1k TC=0,0
V_V18 N05473 N05485 2V
D_D11 N05497 N05485 D1N4001
R_R23 0 N05497 1k TC=0,0
V_V21 N05934 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R25 0 N05958 1k TC=0,0
D_D12 N05958 N05946 D1N4001
V_V20 N05946 N05934 2V
R_R24 0 N05958 1k TC=0,0
D_D13 N06376 N06472 D1N4001
V_V22 N06364 0 AC 0
+SIN 0v 10v 50hz 0 0 0
R_R26 N06364 N06376 1k TC=0,0
V_V23 N06472 0 2V
R_R27 0 N06376 1k TC=0,0
D_D14 N06664 N06376 D1N4001
V_2V 0 N06664 0Vdc

ANALYSIS TYPE: (same for all circuits)

10
 1. SERIES NEGATIVE CLIPPER CIRCUIT

CIRCUIT: RESULT:

R2 D1

1k D1N4001
V V

V2 R1
VOFF = 0v 1k
VAMPL = 10v
FREQ = 50hz
AC = 0

2. SERIES POSITIVE CLIPPER CIRCUIT

CIRCUIT: RESULT:

D2
R3

1k
V V
D1N4001

V3 R4
VOFF = 0v 1k
VAMPL = 10v
FREQ = 50hz
AC = 0

11
 3. PARALLEL POSITIVE CLIPPER CIRCUIT

CIRCUIT: RESULT:

R5

1k
V V

V4 R6
VOFF = 0v 1k
VAMPL = 10v D3
FREQ = 50hz D1N4001
AC = 0

4. PARALLEL NEGATIVE CLIPPER CIRCUIT

CIRCUIT: RESULT:

R7

1k
V V

V5 R8
VOFF = 0v 1k
VAMPL = 10v D4
FREQ = 50hz D1N4001
AC = 0

12
 5. POSITIVE BIASED POSITIVE PARALLEL CLIPPER CIRCUIT

CIRCUIT: RESULT:

R9

1k
V V

D5
V6 D1N4001 R10
VOFF = 0v 1k
VAMPL = 10v
FREQ = 50hz
AC = 0 V7
2V

6. NEGATIVE BIASED POSITIVE PARALLEL CLIPPER CIRCUIT

CIRCUIT: RESULT:
R11

1k
V V

D6
V8 D1N4001 R12
VOFF = 0v 1k
VAMPL = 10v
FREQ = 50hz
AC = 0 V9

2V

13
 7. POSITIVE BIASED NEGATIVE PARALLEL CLIPPING CIRCUIT

CIRCUIT: RESULT:

R13

1k
V V

D7
V10 D1N4001 R14
VOFF = 0v 1k
VAMPL = 10v
FREQ = 50hz
AC = 0 V11
2V

8. NEGATIVE BIASED NEGATIVE PARALLEL CLIPPING CIRCUIT

CIRCUIT: RESULT:

R15

1k
V V

D8
V12 D1N4001 R16
VOFF = 0v 1k
VAMPL = 10v
FREQ = 50hz
AC = 0 V13

2V

14
 9. POSITIVE BIASED NEGATIVE SERIES CLIPPER CIRCUIT

CIRCUIT: RESULT:

V15 D9

V 2V V
D1N4001

V14 R18 R19

VOFF = 0v 1k 1k
VAMPL = 10v
FREQ = 50hz
AC = 0

10. NEGATIVE BIASED NEGATIVE SERIES CLIPPER CIRCUIT

CIRCUIT: RESULT:

V16 D10

V 2V V
D1N4001

V17 R20 R21

VOFF = 0v 1k 1k
VAMPL = 10v
FREQ = 50hz
AC = 0

15
 11. NEGATIVE BIASED POSITIVE SERIES CLIPPER CIRCUIT

CIRCUIT: RESULT:

V18 D11

V 2V V
D1N4001

V19 R22 R23

VOFF = 0v 1k 1k
VAMPL = 10v
FREQ = 50hz
AC = 0

12. POSITIVE BIASED POSITIVE SERIES CLIPPER CIRCUIT

CIRCUIT: RESULT:

V20 D12

V2V V
D1N4001

V21 R24 R25

VOFF = 0v 1k 1k
VAMPL = 10v
FREQ = 50hz
AC = 0

16
 13. DOUBLE CLIPPING CIRCUIT

CIRCUIT: RESULT:

R26

1k
V

V
D13 D14
V22 D1N4001 D1N4001 R27
VOFF = 0v 1k
VAMPL = 10v 2V
FREQ = 50hz
AC = 0 2V
V23
0Vdc

CONCLUSION:

Diodes can be used to clip the top, or bottom, or both of a waveform at a particular dc level and pass it
to the output without distortion. Diode Clipping Circuits are used to eliminate amplitude noise or
voltage spikes, voltage regulation or to produce new waveforms from an existing signal such as squaring
off the peaks of a sinusoidal waveform to obtain a rectangular waveform as seen above.

17
 EXPERIMENT-3
AIM: - To simulate different clamping circuits and observe the waveform.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Clamper Circuit
A Clamper Circuit is a circuit that adds a DC level to an AC signal. Actually, the positive and negative
peaks of the signals can be placed at desired levels using the clamping circuits. As the DC level gets
shifted, a clamper circuit is called as a Level Shifter.

Types of Clampers
There are few types of clamper circuits, such as

 Positive Clamper
 Positive clamper with positive VrVr
 Positive clamper with negative VrVr
 Negative Clamper
 Negative clamper with positive VrVr
 Negative clamper with negative Vr

Positive Clamper Circuit

A Clamping circuit restores the DC level. When a negative peak of the signal is raised above to the
zero level, then the signal is said to be positively clamped.
A Positive Clamper circuit is one that consists of a diode, a resistor and a capacitor and that shifts the
output signal to the positive portion of the input signal. The figure below explains the construction of
a positive clamper circuit.

18
Positive Clamper with Positive V r
A Positive clamper circuit if biased with some positive reference voltage, that voltage will be added
to the output to raise the clamped level. Using this, the circuit of the positive clamper with positive
reference voltage is constructed as below.

Positive Clamper with Negative VrVr

A Positive clamper circuit if biased with some negative reference voltage, that voltage will be added

to the output to raise the clamped level. Using this, the circuit of the positive clamper with positive
reference voltage is constructed as below.

Positive Clamper with Negative VrVr

A Positive clamper circuit if biased with some negative reference voltage, that voltage will be added
to the output to raise the clamped level. Using this, the circuit of the positive clamper with positive
reference voltage is constructed as below.

19
Negative clamper with positive Vr
A Negative clamper circuit if biased with some positive reference voltage, that voltage will be added
to the output to raise the clamped level. Using this, the circuit of the negative clamper with positive
reference voltage is constructed as below.

Negative Clamper with Negative V r

A Negative clamper circuit if biased with some negative reference voltage, that voltage will be added
to the output to raise the clamped level. Using this, the circuit of the negative clamper with negative
reference voltage is constructed as below.

There are many applications of Clampers:

 Used as direct current restorers

 Used to remove distortions
 Used as voltage multipliers
 Used for the protection of amplifiers
 Used as test equipment
 Used as base-line stabilizer

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

20
 NETLIST:

R_R1 0 N00168 1k TC=0,0

D_D1 N00168 0 D1N4001
C_C1 N00131 N00168 0.01mf TC=0,0
V_V1 N00131 0 AC 0
+SIN 0 10v 100HZ 0 0 0
D_D2 0 N00881 D1N4001
R_R2 0 N00881 1k TC=0,0
V_V2 N00871 0 AC 0
+SIN 0 10v 100HZ 0 0 0
C_C2 N00871 N00881 0.01mf TC=0,0
C_C3 N01247 N01257 0.01mf TC=0,0
V_V3 N01247 0 AC 0
+SIN 0 10v 100HZ 0 0 0
D_D3 N01257 N01452 D1N4001
R_R3 0 N01257 1K TC=0,0
V_V4 N01452 0 12V
V_V6 N01815 0 12V
D_D4 N01815 N01775 D1N4001
R_R4 0 N01775 1K TC=0,0
V_V5 N01765 0 AC 0
+SIN 0 10V 100HZ 0 0 0
C_C4 N01765 N01775 0.01mf TC=0,0
D_D5 N02538 N02578 D1N4001
V_V7 N02528 0 AC 0
+SIN 0 10v 100HZ 0 0 0
R_R5 0 N02538 1K TC=0,0
V_V8 0 N02578 12V
C_C5 N02528 N02538 0.01mf TC=0,0
D_D6 N02957 N02997 D1N4001
C_C6 N02947 N02957 0.01mf TC=0,0
V_V10 N02997 0 12V
V_V9 N02947 0 AC 0
+SIN 0 10V 100HZ 0 0 0
R_R6 0 N02957 1K TC=0,0

ANALYSIS TYPE: (same for all circuits)

21
 1. Parallel negative clamper circuit

CIRCUIT: RESULT:

C1

0.01mf
V V

V1 D1 R1
VOFF = 0 D1N4001 1k
VAMPL = 10v
FREQ = 100HZ
AC = 0

2. Parallel positive clamper circuit

CIRCUIT: RESULT:

C2

0.01mf
V V

V2 D2 R2
VOFF = 0 D1N4001 1k
VAMPL = 10v
FREQ = 100HZ
AC = 0

22
3. Negative clamper with positive biasing
CIRCUIT: RESULT:

C3

0.01mf
V V

D3
D1N4001

V3 R3
VOFF = 0 V4 1K
VAMPL = 10v 12V
FREQ = 100HZ
AC = 0

4. Positive clamper with positive bias

CIRCUIT: RESULT:

C4

0.01mf
V V

D4
D1N4001

V5 R4
VOFF = 0 V6 1K
VAMPL = 10V 12V
FREQ = 100HZ
AC = 0

23
 5. Negative clamper with negative biasing
CIRCUIT: RESULT:

C5

0.01mf
V V

D5
D1N4001

V7 R5
VOFF = 0 V8 1K
VAMPL = 10v
FREQ = 100HZ
AC = 0
12V

6. Positive clamper with negative biasing

CIRCUIT: RESULT:

C6

0.01mf
V V

D6
D1N4001

V9 R6
VOFF = 0 V10 1K
VAMPL = 10V 12V
FREQ = 100HZ
AC = 0

EXPERIMENT-4

24
AIM: - To simulate diode as a halfwave rectifier circuit using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Half Wave Rectification

A rectifier is a circuit which converts the Alternating Current (AC) input power into a Direct
Current (DC) output power. The input power supply may be either a single-phase or a multi-phase
supply with the simplest of all the rectifier circuits being that of the Half Wave Rectifier.

Half Wave Rectifier Circuit

During each “positive” half cycle of the AC sine wave, the diode is forward biased as the anode is
positive with respect to the cathode resulting in current flowing through the diode.
Since the DC load is resistive (resistor, R), the current flowing in the load resistor is therefore
proportional to the voltage (Ohm´s Law), and the voltage across the load resistor will therefore be the
same as the supply voltage, Vs (minus Vƒ), that is the “DC” voltage across the load is sinusoidal for
the first half cycle only so Vout = Vs.
During each “negative” half cycle of the AC sinusoidal input waveform, the diode is reverse biased as
the anode is negative with respect to the cathode. Therefore, NO current flows through the diode or
circuit. Then in the negative half cycle of the supply, no current flows in the load resistor as no voltage
appears across it so therefore, Vout = 0.
The current on the DC side of the circuit flows in one direction only making the circuit Unidirectional.

PROCEDURE: -

25
 1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

V_V1 N00112 0 AC 0
+SIN 0 220 50 0 0 0
R_R1 N00112 N00119 1 TC=0,0
X_TX1 N00119 0 N00194 0 SCHEMATIC1_TX1
D_D1 N00194 N00201 D1N4001
R_R2 0 N00201 100 TC=0,0
.subckt SCHEMATIC1_TX1 1 2 3 4
K_TX1 L1_TX1 L2_TX1 1
L1_TX1 1 2 10mH
L2_TX1 3 4 1mH

ANALYSIS TYPE:

26
CIRCUIT:
R1 D1

1 D1N4001
V V

TX1
V1
VOFF = 0
VAMPL = 220 R2
FREQ = 50 100
AC = 0

0 0

RESULT:

CONCLUSION:

A half wave rectifier is not as effective as a full wave rectifier. With a 1/2 wave, you are throwing away
one hump of the sine wave...either positive or negative portion. With a full wave rectifier you get both
humps...either positive or negative.

27
 EXPERIMENT-5
AIM: - To simulate diode as a full-wave rectifier circuit using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

In a Full Wave Rectifier circuit two diodes are now used, one for each half of the cycle. A multiple
winding transformer is used whose secondary winding is split equally into two halves with a common
centre tapped connection, (C). This configuration results in each diode conducting in turn when its
anode terminal is positive with respect to the transformer centre point C producing an output during
both half-cycles, twice that for the half wave rectifier so it is 100% efficient as shown below.

Full Wave Rectifier Circuit

The full wave rectifier circuit consists of two power diodes connected to a single load resistance (RL)
with each diode taking it in turn to supply current to the load. When point A of the transformer is
positive with respect to point C, diode D1 conducts in the forward direction as indicated by the arrows.

28
PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

R_R1 N00423 N00431 1 TC=0,0

D_D1 N00439 N00447 D1N4001
V_V1 N00423 0 AC 0
+SIN 0 220 50 0 0 0
X_TX1 N00431 0 N00439 0 N00527 XFRM_LIN/CT-SEC PARAMS: LP_VALUE=10mH
+ LS1_VALUE=0.5mH LS2_VALUE=0.5mH COUPLING=.99 RP_VALUE=0.1 RS_VALUE=0.1
R_R3 0 N00447 1k TC=0,0
D_D2 N00527 N00447 D1N4001

ANALYSIS TYPE: -

29
CIRCUIT:
R1 D1

1 D1N4001
V

V1 TX1
VOFF = 0
VAMPL = 220 R3
FREQ = 50
AC = 0
0 1k
V

XFRM_LIN/CT-SEC
D2

0 D1N4001

RESULT:

CONCLUSION: -

Full-wave rectifier allows us to convert almost all the incoming AC power to DC.

30
 EXPERIMENT-6
AIM: - To simulate diode as a bridge-wave rectifier circuit using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -
The only difference in the analysis between full wave and centre tap rectifier is that

1. In a bridge rectifier circuit, two diodes conduct during each half cycle and the forward
resistance becomes double (2RF).
2. In a bridge rectifier circuit, Vsmax is the maximum voltage across the transformer
secondary winding whereas in a centre tap rectifier Vsmax represents that maximum
voltage across each half of the secondary winding.

Advantages

 The efficiency of the bridge rectifier is higher than the efficiency of a half-wave rectifier.
However, the rectifier efficiency of the bridge rectifier and the center-tapped full-wave rectifier
is the same.
 The DC output signal of the bridge rectifier is smoother than the output DC signal of a half-
wave rectifier.
 In a half-wave rectifier, only half of the input AC signal is used and the other half is blocked.
Half of the input signal is wasted in a half-wave rectifier. However, in a bridge rectifier, the
electric current is allowed during both positive and negative half cycles of the input AC signal.
Hence, the output DC signal is almost equal to the input AC signal.

Disadvantages

 The circuit of a bridge rectifier is complex when compared to a half-wave rectifier and center-
tapped full-wave rectifier. Bridge rectifiers use 4 diodes while half-wave rectifiers and center
tapped full wave rectifiers use only two diodes.
 When more diodes are used more power loss occurs. In a center-tapped full-wave rectifier,
only one diode conducts during each half cycle. But in a bridge rectifier, two diodes
connected in series conduct during each half cycle. Hence, the voltage drop is higher in a
bridge rectifier.

31
PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

X_TX1 N00479 0 N00489 N00599 SCHEMATIC1_TX1

R_R1 N00469 N00479 1 TC=0,0
V_V1 N00469 0 AC 0
+SIN 0 220 50 0 0 0
D_D2 0 N00489 D1N4001
D_D3 N00489 N00778 D1N4001
D_D4 0 N00599 D1N4001
D_D5 N00599 N00778 D1N4001
R_R2 0 N00778 1k TC=0,0

.subckt SCHEMATIC1_TX1 1 2 3 4
K_TX1 L1_TX1 L2_TX1 1
L1_TX1 1 2 10mH
L2_TX1 3 4 1Mh

ANALYSIS TYPE: -

32
CIRCUIT: -
R1

1
V

D2 D3
TX1
V1
VOFF = 0
D1N4001 D1N4001
VAMPL = 220
FREQ = 50
AC = 0
D4 D5 V
R2
D1N4001 D1N4001 1k

RESULT: -

CONCLUSION:

In bridge wave rectifier four diodes are used to convert A.C voltage in to the D.C voltage. The
practical value of ripple factor is different than the theoretical value.

33
 EXPERIMENT-7
AIM: - To simulate diode characteristics circuit using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Diode Characteristics

A diode is simply a PN junction, but its applications are extensive in electronic circuits. Three
important characteristics of a diode are, first of all, the forward voltage drop. Under a forward bias
condition, this should be about .7 volts. Then there is the reverse voltage drop. In the reverse, when
we reverse bias the diode the depletion layer widens and usually, the applied voltages are felt across the
diode. Then there is the reverse breakdown voltage. Reverse voltage drop that will reverse current
flow and in most cases destroy the diode.

Diode Elements

A diode has two leads connected to the external circuit. Here we have a little diode here and this would
be the two leads. Since the diode behaves differently depending upon forward or reverse bias it is critical
to be able to distinguish the leads. The anode connects to the p-type material, this would be the anode
right here, this connects to the p material. The cathode connects to the n-type material right here. When
you see a diode there is usually a colored band on the diode and the color band indicates the end that is
the cathode. One way to remember the designation here is that the arrow always points to the end
material. The p material would be here and the arrow was pointing at the end material, which would
be the cathode.

A PN Junction Diode is one of the simplest semiconductor devices around, and which has the
characteristic of passing current in only one direction only. However, unlike a resistor, a diode does not
behave linearly with respect to the applied voltage as the diode has an exponential current-voltage ( I-
V ) relationship and therefore we can not described its operation by simply using an equation such as
Ohm’s law.
If a suitable positive voltage (forward bias) is applied between the two ends of the PN junction, it can
supply free electrons and holes with the extra energy they require to cross the junction as the width of
the depletion layer around the PN junction is decreased.

34
PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

V_V1 N00477 0 12v

D_D1 N00477 N00470 D1N4001
R_R1 0 N00470 1k TC=0,0

ANALYSIS TYPE: -

CIRCUIT:
D1

D1N4001
I
V1
12v R1
1k

35
RESULT:

CONCLUSION:

During forward bias, the diode conducts current with increase in voltage. During reverse bias,
the diode does not conduct with increase in voltage (break down usually results in damage of diode).

36
 EXPERIMENT-8
AIM: - To simulate transistor characteristics using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Transistor Characteristics

In physics, the graph representing the relationships between the current and the voltage of any transistor
of any configuration is called Transistor Characteristics. Any two-port network which is analogous to
transistor configuration circuits can be analyzed using three types of characteristic curves. They are

 Input Characteristics: The curve describes the changes in the values of input current with
respect to the values of input voltage keeping the output voltage constant.
 Output Characteristics: The curve is got by plotting the output current against output voltage
keeping the input current constant.
 Current Transfer Characteristics: This characteristic curve describes the variation of output
current in accordance with the input current, keeping the output voltage constant.
Transistors are three terminal active devices made from different semiconductor materials that can act
as either an insulator or a conductor by the application of a small signal voltage. The transistor’s ability
to change between these two states enables it to have two basic functions: “switching” (digital
electronics) or “amplification” (analogue electronics). Then bipolar transistors have the ability to
operate within three different regions:
 Active Region – the transistor operates as an amplifier and Ic = β*Ib
 Saturation – the transistor is “Fully-ON” operating as a switch and Ic = I(saturation)
 Cut-off – the transistor is “Fully-OFF” operating as a switch and Ic = 0

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

37
Q_Q1 N00208 N00071 0 Q2N2222
R_R1 N00114 N00071 1 TC=0,0
V_V1 N00114 0 15v
V_V2 N00208 0 15v

ANALYSIS TYPE: -

CIRCUIT:

Q1
R1
I
1
Q2N2222
V2
15v
V1
15v

38
RESULT: -

CONCLUSION: -
The transistor operates in the active region if and only if the base emitter junction id forward biased
and the base collector junction is reversed biased, if satisfied, it will serve as amplifier.

39
 EXPERIMENT-9
AIM: - To simulate transistor as an amplifier using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Transistor Amplifier
A transistor acts as an amplifier by raising the strength of a weak signal. The DC bias voltage applied
to the emitter base junction, makes it remain in forward biased condition. This forward bias is
maintained regardless of the polarity of the signal. The below figure shows how a transistor looks like
when connected as an amplifier.

The low resistance in input circuit, lets any small change in input signal to result in an appreciable
change in the output. The emitter current caused by the input signal contributes the collector current,
which when flows through the load resistor RL, results in a large voltage drop across it. Thus a small
input voltage results in a large output voltage, which shows that the transistor works as an amplifier.

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

40
NETLIST: -

R_R2 N00352 N00317 10k TC=0,0

R_R3 N00348 N00317 47k TC=0,0
R_R4 N00517 N00356 60 TC=0,0
C_C1 N00356 N00360 1n TC=0,0
R_R5 0 N00348 2k TC=0,0
Q_Q1 N00352 N00360 N00387 Q2N2222
R_R6 0 N00387 5k TC=0,0
C_C2 N00352 N00405 1n TC=0,0
C_C3 0 N00387 1n TC=0,0
R_R7 0 N00405 20k TC=0,0
V_V1 N00317 0 15v
V_V3 N00517 0 DC 0Vdc AC 1mv
V_V5 N01642 0
+SIN 0 1 50 0 0 0
R_R11 N01642 N01604 1k TC=0,0
E_U2 NON 0 VALUE {LIMIT(V(N01604,0)*1E6,-15V,+15V)}
R_R10 N01604 NON 1k TC=0,0

ANALYSIS TYPE: -

41
CIRCUIT: -

R3 R2
47k 10k

Q1
R4 C1 C2
V1
60 1n 1n
Q2N2222 V 15v

V3
1mv
0Vdc
R7
R5 R6 C3 20k
2k 5k 1n

RESULT: -

CONCLUSION:
The transistor is good component to get amplified current using a very small current. Dc current gain
increases as Voltage is increases. But Dc current gain for the same voltage with the different base
current is same.

42
 EXPERIMENT-10
AIM: - To simulate OP-AMP circuit using ORCAD Capture 16.3.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

An Operational Amplifier or op-amp is a voltage amplifying device designed to be used with external
feedback components such as resistors and capacitors between its output and input terminals. It is a
high-gain electronic voltage amplifier with a differential input and usually a single-ended output. Op-
amps are among the most widely used electronic devices today as they are used in a vast array of
consumer, industrial, and scientific devices.

In an inverting amplifier circuit, the operational amplifier inverting input receives feedback from the
output of the amplifier.

As the non-inverting input of the operational amplifier is held at ground potential this means that the
inverting input must be virtually at earth potential.

The non-inverting amplifier is one in which the output is in phase with respect to the input. The feedback
is applied at the inverting input. However, the input is now applied at the non-inverting input.

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

43
E_U1 NON 0 VALUE {LIMIT(V(N00144,N00101)*1E6,-15V,+15V)}
R_R1 N00101 NON 1k TC=0,0
R_R2 0 N00101 1k TC=0,0
V_V1 N00144 0
+SIN 0v 1v 50hz 0 0 0
Q_Q1 N00352 N00360 N00387 Q2N2222
R_R6 0 N00387 5k TC=0,0
C_C2 N00352 N00405 1n TC=0,0
C_C3 0 N00387 1n TC=0,0
R_R7 0 N00405 20k TC=0,0
V_V1 N00317 0 15v

ANALYSIS TYPE: -

CIRCUIT: - 1. NON- INVERTING

R1

1k

R2
OPAMP
-
1k
OUT non
V
0 +
V1 V
U1
VOFF = 0v
VAMPL = 1v
FREQ = 50hz
AC =
0

44
RESULT: -

45
 2. INVERTING
R10

1k

R11

U2
1k
V
+

OUT non
V5
VOFF = 0 V
VAMPL = 1 - OPAMP
FREQ = 50
AC =
0

RESULT:

CONCLUSION: -
Using an op-amp rather than a voltage divider configuration with resistors is a much better design.
That is the op-amp has a very high input resistance so almost any small load will not be affected by
the op-amp.

46
 EXPERIMENT-11
AIM: - To simulate all Logic Gates.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT,
NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth
tables.

AND GATE

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot
(.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

OR GATE

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A
plus (+) is used to show the OR operation.

NOT GATE

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is
also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two
ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using
NOR logic gates in the same way

47
NAND GATE

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion.

NOR GATE

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR
gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output.
The small circle represents inversion.

EX-OR GATE

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs
are high. An encircled plus sign is used to show the EOR operation.

EX-NOR GATE

48
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either,
but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output.
The small circle represents inversion.

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

.EXTERNAL OUTPUT nand

.EXTERNAL OUTPUT nor
X_U1A N14597 NOT $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A N14597 N14688 AND $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3A N14597 N14688 OR $G_DPWR $G_DGND 7432 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U4A N14597 N14688 NAND $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U5A N14597 N14688 NOR $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_A STIM(1,1)
+ $G_DPWR $G_DGND
+ N14597
+ IO_STM
+ IO_LEVEL=0
+ 0s 0
+ 1ms 0
+ 2ms 0
+ 3ms 1
+ 4ms 1
U_B STIM(1,1)
+ $G_DPWR $G_DGND
+ N14688
+ IO_STM
+ IO_LEVEL=1
+ 0s 0
+ 1ms 0
+ 2ms 1
+ 3ms 0
+ 4ms 1

49
 ANALYSIS TYPE: -

CIRCUIT: - RESULT: -
U1A
1
3
2 not
A
S1 V
7400
V

U1B U2A
B 4 1
S1 6 3
5 2 and
V
V
7400 7400

U1C
9
8
C 10
S1
7400 U2B
V
4
6
5 or
U1D
V
12 7400
11
13

7400

CONCLUSION: All the logic gates have different output waveform.

50
 EXPERIMENT-12
AIM: - To simulate NAND & NOR as universal gates.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

A universal gate is a logic gate which can implement any Boolean function without the need to use any
other type of logic gate. The NOR gate and NAND gate are universal gates. This means that you can
create any logical Boolean expression using only NOR gates or only NAND gates.

NAND GATE AS UNIVERSAL GATE

Implementing an Inverter Using only NAND Gate.

The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).

1. All NAND input pins connect to the input signal A gives an output A’

2. One NAND input pin is connected to the input signal A while all other input pins are connected to
logic 1. The output will be A’.

Implementing AND Using only NAND Gates.

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND
gate with its output complemented by a NAND gate inverter).

Implementing OR Using only NAND Gates.

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a
NAND gate with all its inputs complemented by NAND gate inverters).

Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions.

51
PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

.EXTERNAL OUTPUT NOT

.EXTERNAL OUTPUT AND
.EXTERNAL OUTPUT OR
U_DSTM1 STIM(1,1)
+ $G_DPWR $G_DGND
+ N00450
+ IO_STM
+ IO_LEVEL=0
+ 0s 0
+ 1ms 0
+ 2ms 0
+ 3ms 0
+ 4ms 1
+ 5ms 1
+ 6ms 1
+ 7ms 1
U_DSTM2 STIM(1,1)
+ $G_DPWR $G_DGND
+ N00462
+ IO_STM
+ IO_LEVEL=0
+ 0s 0
+ 1ms 0
+ 2ms 1
+ 3ms 1
+ 4ms 0
+ 5ms 0
+ 6ms 1
+ 7ms 1
X_U1A N00450 N00450 NOT $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U1B N00462 N00506 N00570 $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U1C N00450 N00450 N00582 $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U1D N00506 N00506 N00594 $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A N00570 N00570 AND $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2B N00582 N00594 OR $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM3 STIM(1,1)

52
+ $G_DPWR $G_DGND
+ N00506
+ IO_STM
+ IO_LEVEL=0
+ 0s 0
+ 1ms 1
+ 2ms 0
+ 3ms 1
+ 4ms 0
+ 5ms 1
+ 6ms 0
+ 7ms 1

ANALYSIS TYPE: -

CIRCUIT: - RESULT: -
U1A
1
3
DSTM1 2 NOT
S1
V
7400 U2A
1
3
2 AND
V
U1B 7400
4
6
V
5
DSTM2
S1 7400

U1C
9
8
10
U2B
7400 4
DSTM3 6
S1 5 OR
V V
U1D 7400
12
11
13

7400

53
NOR GATE AS UNIVERSAL GATE

Implementing an Inverter Using only NOR Gate.

The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

1. All NOR input pins connect to the input signal A gives an output A’.

2. One NOR input pin is connected to the input signal A while all other input pins are connected to
logic 0. The output will be A’.

Implementing OR Using only NOR Gates.

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate
with its output complemented by a NOR gate inverter)

Implementing AND Using only NOR Gates.

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a
NOR gate with all its inputs complemented by NOR gate inverters) Thus, the NOR gate is a universal
gate since it can implement the AND, OR and NOT functions.

Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions.

PROCEDURE: -
7. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
8. Create new project and add new schematic file.
9. Add the components according to the requirement.
10. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
11. Again, go to PSpice select VIEW NETLIST and copy the list.
12. Save the design and print schematic view when required.

54
NETLIST: -

X_U1A N00450 N00450 NOT $G_DPWR $G_DGND 7400 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0
X_U1B N00462 N00506 N00570 $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U1C N00450 N00450 N00582 $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U1D N00506 N00506 N00594 $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A N00570 N00570 AND $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2B N00582 N00594 OR $G_DPWR $G_DGND 7400 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM3 STIM(1,1)
+ $G_DPWR $G_DGND
+ N00506
+ IO_STM
+ IO_LEVEL=0
+ 0s 0
+ 1ms 1
+ 2ms 0
+ 3ms 1
+ 4ms 0
+ 5ms 1
+ 6ms 0
+ 7ms 1
X_U3A N01796 N01796 NOT $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3B N01783 N01820 N01910 $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3C N01796 N01796 N01922 $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3D N01820 N01820 N01942 $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U4A N01910 N01910 OR $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U4B N01922 N01942 AND $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM4 STIM(1,1)
+ $G_DPWR $G_DGND
+ N01783
+ IO_STM
+ IO_LEVEL=0
+ 0ms 0
+ 1ms 0
+ 2ms 1
+ 3ms 1
U_DSTM5 STIM(1,1)
+ $G_DPWR $G_DGND
+ N01820
+ IO_STM
+ IO_LEVEL=0
+ 0ms 0
+ 1ms 1
+ 2ms 0
+ 3ms 1

55
 ANALYSIS TYPE: -

CIRCUIT: - RESULT: -
U3A
2
1
DSTM4 3 not
S1
V
7402

U3B U4A
5 2
4 1
6 3 OR
V
7402 7402

U3C
8
10 U4B
9 5
DSTM5 4
S1 6 AND
7402
V V
7402

U3D
11
13
12

7402

CONCLUSION: NAND & NOR as universal gates studied by simulating.

56
 EXPERIMENT-13
AIM: - To simulate 3-bit synchronous Up counter.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock. The most common
type is a sequential digital logic circuit with an input line called the clock and multiple output lines. The
values on the output lines represent a number in the binary or BCD number system. Each pulse applied
to the clock input increments or decrements the number in the counter. A counter circuit is usually
constructed of a number of flip-flops connected in cascade. For example, the circuit shown below is an
ascending (up-counting) 3-bit synchronous counter implemented with JK flip-flops. Each bit of this
counter is allowed to toggle when all of the less significant bits are at a logic high state. Upon clock
rising edge, bit 1 toggles if bit 0 is logic high; bit 2 toggles if bits 0 and 1 are both high.

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

source COUNTER
X_U1 $D_HI N00272 $D_HI N00279 M_UN0001 $G_DPWR $G_DGND JKFF
X_U2 N00279 N00272 N00279 N00309 M_UN0002 $G_DPWR $G_DGND JKFF
X_U3 N00372 N00272 N00372 M_UN0003 M_UN0004 $G_DPWR $G_DGND JKFF
X_U4A N00279 N00309 N00372 $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_CLK STIM(1,1) $G_DPWR $G_DGND N00272 IO_STM IO_LEVEL=0
+00

57
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT

ANALYSIS TYPE: -

CIRCUIT: -

CONCLUSION: 3-bit Synchronous up counter studied.

58
 EXPERIMENT-14
AIM: - To simulate Full-adder and Half-adder circuits.

SOFTWARE USED: - ORCAD CAPTURE

THEORY: -

FULL ADDER

A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called
because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1
It therefore has three inputs and two outputs.

Using the Karnaugh maps to obtain minimized expressions for S and Cout, we notice the chequerboard
pattern of an XOR gate in the sum term to give:
S=X ⊕ Y ⊕ Cin whilst Cout = XY + X Cin + Y Cin

PROCEDURE: -
1. Open Capture CIS from the start menu, and select ORCAD_CAPTURE_CIS option with PSpice
Designer.
2. Create new project and add new schematic file.
3. Add the components according to the requirement.
4. Now, go to PSpice then select NEW SIMULATION PROFILE, select BIAS POINT and OK.
5. Again, go to PSpice select VIEW NETLIST and copy the list.
6. Save the design and print schematic view when required.

NETLIST: -

X_U1A N00345 N00349 N00306 $G_DPWR $G_DGND 7486 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0
X_U1B N00306 N00318 N00379 $G_DPWR $G_DGND 7486 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A N00318 N00306 N00275 $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2B N00345 N00349 N00287 $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3A N00275 N00287 N00383 $G_DPWR $G_DGND 7432 PARAMS:

59
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM2 STIM(1,1) $G_DPWR $G_DGND N00345 IO_STM IO_LEVEL=0
+00
+ +2 1
+REPEAT FOREVER
+ +2 0
+ +2 1
+ ENDREPEAT
U_DSTM3 STIM(1,1) $G_DPWR $G_DGND N00349 IO_STM IO_LEVEL=0
+00
+ +1 1
+REPEAT FOREVER
+ +1 0
+ +1 1
+ ENDREPEAT
U_DSTM4 STIM(1,1) $G_DPWR $G_DGND N00318 IO_STM IO_LEVEL=0
+00
+ +4 1
+REPEAT FOREVER
+ +4 0
+ +4 1
+ ENDREPEAT

ANALYSIS TYPE: -

60
CIRCUIT: -
DSTM3
DSTM4 DSTM2

CLK
CLK

CLK

OFFTIME = 1
OFFTIME = 4 OFFTIME = 2 ONTIME = 1 U1A U1B
ONTIME = 4 ONTIME = 2 DELAY = 1 4
DELAY = DELAY = 3 6
STARTVAL = 0 2 5
STARTVAL = 0 STARTVAL = 0 V
OPPVAL = 1
V
OPPVAL = 1 OPPVAL = 1 7486 7486
V

U2A
1
3
2

7408
U3A
1
3
2
V
U2B 7432
4
6
5

7408

RESULT: -

61
HALF ADDER
Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and
carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and
the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily
constructed using one X-OR gate and one AND gate.
The half adder can add only two input bits (A and B) and has nothing to do with the carry if there is
any in the input. So, if the input to a half adder have a carry, then it will be neglected it and adds only
the A and B bits. That means the binary addition process is not complete and that’s why it is called a
half adder.
The truth table, schematic representation and XOR//AND realization of a half adder are shown in the
figure below.

NETLIST: -

U_DSTM5 STIM(1,1) $G_DPWR $G_DGND N01410 IO_STM IO_LEVEL=0

+00
+ +2m 1
+REPEAT FOREVER
+ +2m 0
+ +2m 1
+ ENDREPEAT
U_DSTM6 STIM(1,1) $G_DPWR $G_DGND N01422 IO_STM IO_LEVEL=0
+00
+ +1m 1
+REPEAT FOREVER
+ +1m 0
+ +1m 1
+ ENDREPEAT
X_U4A N01410 N01422 N01468 $G_DPWR $G_DGND 7486 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U5A N01410 N01422 N01464 $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0

62
 ANALYSIS TYPE: -

U4A

1
OFFTIME = 2m DSTM5
ONTIME = 2m CLK 3

2
DELAY =
STARTVAL = 0 V V
OPPVAL = 1 7486

U5A
OFFTIME = 1m DSTM6 1
ONTIME = 1m CLK 3
DELAY = 2
STARTVAL = 0 V
OPPVAL = 1 V 7408

CIRCUIT: -

RESULT: -

CONCLUSION: Half adder and full adder circuit studied.

63