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The main intention of sanity checks in Physical Design is that they are mainly done for
checking the design for further acceptance at each stages of the physical implementation. It
qualifies the netlist in terms of timing, checks the issues related to library files, constraints
files etc.
Following are the sanity checks carried out in physical design flow:
check_library
check_timing
check_design
check_legality
report_timing
report_qor
report_constraint
check_library: It performs consistency checks between logical and physical libraries. That
means each cells that are described in the netlist has its corresponding physical, timing and
logical information defined in the libraries.
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check_timing: PNR tool won't optimize the paths which are not constrained. So we have to
check any unconstrained paths are exist in the design. The check_timing command will
report the unconstrained paths. If there are any unconstrained paths in the design, run the
report_timing command to verify whether the unconstrained paths are false paths.
check_design: This check is to report problems like undriven input ports, unloaded output
ports, nets/ports with multiple drivers, unloaded nets, pins mismatch, cells or instances
with out I/O pins/ports etc.
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report_timing: The report_timing command provides a report of timing information for the
current design. By default, the report_timing command reports the single worst setup path
in each clock group.
report_qor: It reports the statistics/QoR of the current design includes its timing
information, cell count, details like combinational and sequential cells, total area of the
current design. This will also reports any DRV s present.
report_constraint: It reports the following parameters in the current design such as WNS,
total negative slacks, DRC violations etc. The report includes whether the constraints are
violated or not, by how much it is violated and the worst violating object.
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Static Timing
Analysis
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