PAVAN KUMAR.

R
Pavanrandy619@gmailcom | +91-8142150715
EXPERIENCE SUMMARY
 Having 2 years of work experience in --- through --- as a Hardware Engineer [PD]
 Experience in Physical Design & STA.
 Experience of working in the latest technology nodes like 8nm, 16nm, and 28nm.
 Experience in block-level Physical Design. Well-known about ASIC design flow
from Specifications to GDSII. Good knowledge of Timing and Congestion fixes.
 Experience in STA sanity checks & manual ECO flow and STA Sign-Off closure.
 Basic Knowledge of writing scripts using TCL & Linux shell.
 Basic Electronics and Debugging Techniques Fundamentals of Digital, CMOS
Theory and Low Power Design,

TECHNICAL SKILLS:

TOOLS: ICC, ICC2, PRIMETIME, FUSION COMPILER & INNOVUS (CADENCE)

Scripting: Basics of TCL, vim, grep, sed, awk.
Technology node: 8nm, 16nm, 28nm,

PROFESSIONAL EXPERIENCE:

PROJECT DETAILS

PROJECT 1: (Client: AMD )

• Title : Block-Level PNR Implementation

• Technology : 8 nm
• Frequency : 525MHz / TP: 1.9 ns
• No of Clocks : 7
• Macro : 8
• Instance Count : 0.4 M
• Metal Layer :11
Responsibilities:
• Responsible for block-level PNR Implementation.
• Performed sanity checks and did various iterations of Floorplanning.
• Reduced congestion by using blockages.
• Created path groups and defined routing layers for routing.
• Fixed timing and DRC, DRV, LVS violations, and sanity checks are performed.
• Analyzed the logs after optimization techniques were utilized.
• Clock tree analysis and meeting skew and latency.
 PROJECT 2: (Client: AMD )
• Title : Block-Level PNR Implementation
• Technology : 16 nm
• Frequency : 465MHz / TP: 2.1ns
• No of Clocks :9
• Macro : 80
• Instance Count :2M
• Metal Layer : 13
Responsibilities:
• Responsible for block-level PNR Implementation.
• Did placement and applied various strategies to control congestion.
• Fixed timing violations after placement and clock tree synthesis (CTS).
• Fixed trans and timing violations across various corners.
• Sanity checks are also performed.
• Analyze the logs before & after iterations.

PROJECT 3: ( Client: AMD)

• Title : Block-Level PNR Implementation

• Technology/Metal Layer : 28 nm / 11 Metal Layers
• Instant Count : 0.5 M
• Macros : 20
• Clocks :5
• Frequency : 565 MHz/ 1.7 ns
Responsibilities:
• Place and Route and timing closure
• Performed sanity checks and did various iterations of Floor planning.
• Pin placement was done with the help of guidelines provided by top-level
• Multiple iterations of floor plan to achieve acceptable congestion.
• Congestion fixing, Timing fixing DRV Fixing.
• Clock tree analysis and meeting skew and latency
• Performed signoff for RC extraction and closed the timing using primetime
• DRCs (Shorts and opens) and LVS.