Objectives

1. Describe the general trends and design constraints of

assembly and packaging.
Solid State Engineering
2. State and discuss the traditional assembly methods.
Chapter 20
Assembly and Packaging

3. Describe the different traditional packaging options.

Assembly and Packaging
4. Discuss the benefits and limitations of seven
advanced assembly and packaging techniques.
7

NCHU / EE / Prof. Fang-Hsing Wang 1 NCHU / EE / Prof. Fang-Hsing Wang 2

Four Important Functions of IC Packaging Traditional Assembly and Packaging

1. Protection from the environment and handling

damage.
2. Interconnections for signals into and out of the
chip. Wafer Test and Sort Die Separation Die Attach

3. Physical support of the chip.

4. Heat dissipation.

Wire Bond Plastic Package Final Package and Test

NCHU / EE / Prof. Fang-Hsing Wang 3 Figure 20.1 NCHU / EE / Prof. Fang-Hsing Wang 4
 Typical IC Packages Design Constraints for IC Packaging
RC Time delay
Number of signal I/Os
Wirebond vs. bump attachment
Performance Package impedance
Signal rise time
Switching transients
Thermal
Chip size
Package size
Dual in-line package Single in-line package Thin small outline package Bond pads size and pitch
(DIP) (SIP) (TSOP) Size/weight/form
Package leads size and pitch
Substrate carrier pads size and pitch
Design of heat sink
Chip substrate (plastic, ceramic, metal)
Carrier (organic, ceramic)
Materials
Thermal expansion mismatch
Lead metallurgy
Integration into existing process
Cost Package materials
Yield
Quad flat pack Plastic leaded chip carrier Leadless chip carrier Method of die attach
(QFP) (PLCC) (LCC) Package attach (through hole, surface
Assembly mount, bumped)
Heat sink assembly
Encapsulation
Figure 20.2 NCHU / EE / Prof. Fang-Hsing Wang 5 NCHU / EE / Prof. Fang-Hsing Wang 6

Levels of IC Packaging Traditional Assembly

First level packaging: Metal leads for mounting
onto printed circuit board
IC packaging
Leads Pins
Wafer preparation (backgrind)
Surface-
mount chips
Pins are
inserted
into holes
Die separation
are
soldered on then
top of tinned soldered on
2nd level packaging:
Printed circuit board
pads on the
PCB.
rear of
PCB. Die attach
assembly
Edge connector plugs into main system.
Wire bonding
PCB subassembly

Final product assembly:

Final assembly of circuit
boards into system
Main electronics
assembly board

Figure 20.3 NCHU / EE / Prof. Fang-Hsing Wang 7 NCHU / EE / Prof. Fang-Hsing Wang 8
 Schematic of the Backgrind Process Wafer Saw and Sliced Wafer
775 um 200~500 um Die singulation
Downforce
Easier to dice Using diamond-blade dicing saw Wafer

Improved thermal dissipation 25 um thick saw blade Stage

Rotating and
Reducing weight oscillating spindle
20,000 RPM
Reducing size 90%~100% saw-through

Wafer on
rotating chuck

Table rotates only during

Blade
indexing of wafers

Figure 20.4 NCHU / EE / Prof. Fang-Hsing Wang 9 Figure 20.5 NCHU / EE / Prof. Fang-Hsing Wang 10

Typical Leadframe for Die Attach Epoxy die attach( )

Chip Bonding
Leadframe
Lead Die Fan out Eutectic attach( )

Die Glass frit attach( )

Epoxy

Epoxy die attach Leadframe

Plastic DIP

1. Dispensing epoxy
2. Placing chip backside down
3. Epoxy curing (125 C/1h)
4. Adding Ag flakes for heat dissipation
Good dies are selected through the ink mark or wafer mapping data from wafer sort.

Figure 20.6 NCHU / EE / Prof. Fang-Hsing Wang 11 Figure 20.7 NCHU / EE / Prof. Fang-Hsing Wang 12
 Au-Si Eutectic Attach Wires Bonded from Chip Bonding Pads to
- Gold/silicon Leadframe
eutectic alloy
Die
Moulding compound
Bond wire
Silicon
Bonding pad Leadframe
Gold or Silver film
Inner lead
(post)
Al2O3 Substrate
Pin tip
1. Au film is deposited on backside of the wafer after backgrind.
2. Alloying to the substrate ( a metal leadframe or Al2O3 substrate)
3. The substrate has an Au or Ag coated surface.
10 wire bonds/second
4. Heating 420 C for 6s
Accuracy : +5 um
5. Forming a eutectic alloy interconnection Au or Al wire with =25 um.
6. More common for bipolar ICs. Die bonding pad pitch ~ 70 um
Figure 20.8 NCHU / EE / Prof. Fang-Hsing Wang 13 Figure 20.9 NCHU / EE / Prof. Fang-Hsing Wang 14

Wirebonding Chip to Leadframe Three Wirebonding Methods

1. Thermocompression Bonds
Thermal energy and pressure are used to form an Au wirebond.

Post

Device bond pad

Photo 20.1 NCHU / EE / Prof. Fang-Hsing Wang 15 Figure 20.10 NCHU / EE / Prof. Fang-Hsing Wang 16
 2. Ultrasonic Wirebonding Sequence 3. Thermosonic Ball Bond Tool moves
up and more
Ultrasonic energy Tool moves upward. wire is fed.
Gold wire
Wedge tool Capillary Pressure and
Pressure More wire is tool ultrasonic energy
Al fed to tool.
Wire bonding Bonding ball
pad Die H2 torch on pad
Ball Die Die
(1)
(2) (3)
(1) (2) (3) (4)

Ultrasonic energy
Tool moves upward.

Pressure Wire breaks Pressure and Tool moves upward.

at the bond. heat form bond.
Wire breaks at
Lead frame Lead frame
the bond.

(4) (5) (6)

(5)

Figure 20.11 NCHU / EE / Prof. Fang-Hsing Wang 17 Figure 20.12 NCHU / EE / Prof. Fang-Hsing Wang 18

Wirebond Pull Test Traditional Packaging

DIP
SIP

Hook
Plastic Packaging TSOP
QFP
PLCC
Ceramic Packaging CERDIP
PGA
LCC

Post
Device

Chip under test

TO-Style Metal Package
Specimen clamp

Figure 20.13 NCHU / EE / Prof. Fang-Hsing Wang 19 NCHU / EE / Prof. Fang-Hsing Wang 20
 Plastic Dual In-Line Package (DIP) for Single In-Line Package (SIP)
Pin-In-Hole (PIH)

DIP
1 PCB( )
2
4004 8008 8086 8088 CPU DIP

Figure 20.16A NCHU / EE / Prof. Fang-Hsing Wang 21 Figure 20.16B NCHU / EE / Prof. Fang-Hsing Wang 22

Thin Small Outline Package (TSOP) with Single In-Line Memory Module (SIMM)
Gull wing Surface Mount Leads

Figure 20.16C NCHU / EE / Prof. Fang-Hsing Wang 23 Figure 20.16D NCHU / EE / Prof. Fang-Hsing Wang 24
Quad Flatpack (QFP) with Gull Wing Plastic Leaded Chip Carrier (PLCC) with
Surface Mount Leads J-Leads for Surface Mount

CPU 80286
100 CPU

SMT PCB

Figure 20.16E NCHU / EE / Prof. Fang-Hsing Wang 25 Figure 20.16F NCHU / EE / Prof. Fang-Hsing Wang 26

Leadless Chip Carrier (LCC) Ceramic Packaging: Laminated Refractory

Ceramic Process Sequence

Ceramic interconnect layers For high reliability and high power IC

Al2O3 powder+ glass powder+ organic vehicle
1 mil thick HTCC: 1600 C
LTCC: 850 C~1050 C

4-layer laminate

Figure 20.16G NCHU / EE / Prof. Fang-Hsing Wang 27 Figure 20.17 NCHU / EE / Prof. Fang-Hsing Wang 28
 Ceramic with Pin Grid Array CERDIP Package

100 mil (0.1 inch) pitch Plane of cross-section

Chip on Cross-section
Indexing epoxy and
notch leadframe
Ceramic lid

Glass seal

Ceramic
base
Courtesy of Advanced Micro Devices Metal lead

2 5 PGA CPU
80486 Pentium ZIF CPU
PGA CPU

Photo 20.2 NCHU / EE / Prof. Fang-Hsing Wang 29 Figure 20.18 NCHU / EE / Prof. Fang-Hsing Wang 30

Test Socket for IC Package Advanced Packaging

Flip chip ( )
Ball grid array (BGA)( )
Chip on board (COB)( )
Tape automated bonding (TAB)( )
Multichip modules (MCM) ( )
Chip scale packaging (CSP) ( )
Wafer-level packaging( )
IC
Figure 20.19 NCHU / EE / Prof. Fang-Hsing Wang 31 NCHU / EE / Prof. Fang-Hsing Wang 32
 Flip Chip Package Flip Chip Package

Connecting pin

Substrate

1.
Via
Metal interconnection 2.
Solder bump
Silicon chip on bonding pad 3. pad
4.
bump
substrate Flip Chip 1960 IBM 5.
BGA; Ball grid array
6.
7.
Figure 20.20 NCHU / EE / Prof. Fang-Hsing Wang 33 NCHU / EE / Prof. Fang-Hsing Wang 34

C4 Solder Bump on Wafer Bonding Pad Epoxy Underfill for Flip chip
3-layer metal stack
Bonding pad Cu-Sn
Cr+Cu Solder bump
Cr
Metal
Nitride Al Deposition Chip
and Etch
Oxide

Epoxy
(1) (2)
2-layer metal deposition Solder bumps form
Sn
during reflow Substrate
Pb Reflow
Process

(3) (4)

Figure 20.21 NCHU / EE / Prof. Fang-Hsing Wang 35 Figure 20.22 NCHU / EE / Prof. Fang-Hsing Wang 36
 Flip Chip Area Array Solder Bumps Chip with Ball Grid Array (BGA)
Versus Wirebond BGA Ball Grid Array
CPU
Flip chip bump Bonding pad
area array perimeter array BGA
I/O
QFP

CPU

BGA
1 I/O
QFP
2 BGA

3
4

Figure 20.23 NCHU / EE / Prof. Fang-Hsing Wang 37 Photo 20.3 NCHU / EE / Prof. Fang-Hsing Wang 38

OPGA Organic pin grid Array

Ball Grid Array (BGA)

Bonding pad

Molded cover Chip

Wire Epoxy

Substrate

Metal via

Solder ball Thermal via

OPGA
AMD AthlonXP CPU

Figure 20.24 NCHU / EE / Prof. Fang-Hsing Wang 39 NCHU / EE / Prof. Fang-Hsing Wang 40
 CuPGA Chip on Board (COB)
IC chip Printed circuit board
CuPGA Lidded Ceramic Package Grid Array

CPU
AMD64 CPU

NCHU / EE / Prof. Fang-Hsing Wang 41 Figure 20.25 NCHU / EE / Prof. Fang-Hsing Wang 42

Tape Automated Bonding (TAB) Multichip Module (MCM)

Individual die MCM substrate

Poyimide tape

Copper leads

MCM substrate are ceramic or advanced PCB.

Reducing size and weight.
Improving parasitic resistance and capacitance.

Figure 20.26 NCHU / EE / Prof. Fang-Hsing Wang 43 Figure 20.27 NCHU / EE / Prof. Fang-Hsing Wang 44
 Chip scale package (CSP) Trends for Advanced Packaging

Since 1990
Low cost, low weight, thin thickness with 1800

enhanced electrical performance. 1500

CSP is an IC package that has a footprint that is 1200

<1.2 times the footprint of the die. 900

Main CSP technology is flip chip and BGA due 600

Direct Chip Attach

to using bump. 300 Flip Chip on Board

NCHU / EE / Prof. Fang-Hsing Wang
Tape Auto. Bonding
0 Other
1996 1997 1998 1999 2000 2001
Years
Flip chip is the fastest growing technolohy.
Solid
45 State Technology, (June 1998): p. 63. Figure 20.28 NCHU / EE / Prof. Fang-Hsing Wang 46

Diversity of Chip Scale Packages18 Wafer-Level Packaging

General CSP Approach CSP Package Name Company
Area array, bumped CSP Amkor/Anam Since latter 1990s
Small outline no-lead/C-lead (SON/SOC) Fujitsu
Bump chip carrier (BCC) Fujitsu WLP is formation of the 1st level interconnections and the
Micro-stud-array (MSA) Hitachi
Custom Leadframe
Bottom leaded plastic (BLP) LG Semicon package I/O terminals on the wafer before it is diced.
Quad flat no-lead (QFN) Matsushita
Memory CSP TI Japan Single chip with C4 bumps
Quad outline non-leaded Toshiba
Enhanced flex CSP 3M
FleXBGA Amkor/Anam
FBGA Fujitsu
Chip-on-flex CSP GE
Interposer (flexible material Multi chip scale package (MCSP) Hightec MC AG
with interconnects) between CSP for memory devices Hitachi
die and substrate IZM flexPAC Fraunhofer Institute
Molded Ball Grid Array Mitsubishi Electric
Chip-on-flex Chip Size Package Motorola Singapore
Fine-pitch BGA (FPBGA) NEC
MicroBGA Tessera
Chip Array Package (CABGA) Amkor/Anam
CSP Cypress Semiconductor
Ceramic mini-BGA IBM
Molded array process CSP Motorola
Rigid Substrate
Plastic chip carrier National
CSP Oki Electric
Transformed grid array package Sony
Ceramic/plastic fine-pitch BGA Toshiba

Table 20.2 NCHU / EE / Prof. Fang-Hsing Wang 47 Figure 20.29 NCHU / EE / Prof. Fang-Hsing Wang 48
 C4 Bumped Wafer Design Concept for Wafer-Level
Packaging
BGA Solder bump
Bonded wire

No leadframe

1mm thick or less. Adhesive

Bonding pad

Chip

-level
Chip Scale Review, (May/June 1999).
Photograph provided courtesy of Advanced Micro Devices

Photo 20.4 NCHU / EE / Prof. Fang-Hsing Wang 49 Figure 20.30 NCHU / EE / Prof. Fang-Hsing Wang 50

Comparison of Standard Test Flow with

Wafer-Level Packaging Features and Benefits
Wafer-Level Package Test Flow
Parameter Benefits
Standard Test Flow WLP Test Flow The package is equal to the chip size in x and y dimensions. It is the
Package size
smallest possible IC package and minimizes the package weight.
Wafer probe WLP fabrication
It is extremely thin with a total height < 1.0 mm as measured from the
Mounted package height
circuit board surface after 2nd level assembly.
Test results indicate that wafer-level packaging components pass
In-situ WLBI
Component reliability
Dice wafer existing reliability tests for passivated components.
Test results indicated solder joint reliability meets standard thermal
Solder joint reliability
cycle (-65 to 125 C) reliability tests.
Package Wafer-level Electrical simulation tests indicates that the die face-down (flip chip)
individual ICs functional test
configuration of wafer-level packaging with its short circuit traces
Electrical performance
results in very good electrical performance for minimizing inductance
and parasitic capacitance losses.
Socket/burn-in
Dicing Integration with existing The wafer-level package is compatible with existing surface mount
at package level
SMT infrastructure technology and uses standard solder balls and ball pitches.
Radioactive elements occurring naturally in packaging materials emit
Functional test at Wafer-level pick at alpha-particles that can cause voltage loss in memory cells. The use of
package level board assembly Alpha-particle protection
polyimide tape and film adhesive provides alpha-particle protection for
memory chips.
Load into tape
The use of existing materials with wafer integration to reduce handling
and reel Burn in Low system cost and a wafer test strategy to minimize duplicate testing provides for a
low overall system cost.

Figure 20.31 NCHU / EE / Prof. Fang-Hsing Wang 51 Table 20.3 NCHU / EE / Prof. Fang-Hsing Wang 52
 Advanced packaging technologies
Advanced packaging technologies refer to the innovative methods and techniques used in the semiconductor industry to package
integrated circuits (ICs) and other electronic components. These packaging technologies play a crucial role in improving the performance,
power efficiency, size, and overall functionality of electronic devices, ranging from smartphones and laptops to high-performance
computing systems.
Traditional packaging involves encapsulating a semiconductor chip in a protective casing, connecting it to external pins or pads, and often
placing it on a printed circuit board (PCB). Advanced packaging technologies, on the other hand, push the boundaries of packaging to
achieve better performance, lower power consumption, and smaller form factors. Some of these advanced packaging techniques include:
1. System-in-Package (SiP): SiP involves integrating multiple ICs and components, such as processors, memory, sensors, and more, into a
single package. This allows for better communication between components, reduced latency, and improved overall performance.
2. 3D Packaging: This involves stacking multiple semiconductor dies vertically, either using through-silicon vias (TSVs) or other interconnect
technologies. 3D packaging reduces the footprint of the device while enabling higher integration and potentially shorter interconnect
distances for better performance.
3. Wafer-Level Packaging (WLP): WLP involves packaging multiple chips directly on a semiconductor wafer before they are diced. This
reduces the need for individual packaging steps and can result in smaller, thinner, and more cost-effective devices.
4. Fan-Out Wafer-Level Packaging (FO-WLP): FO-WLP extends the concept of WLP by redistributing the connections of a chip beyond its
original footprint, allowing for additional components or larger dies to be integrated.
5. Flip-Chip Packaging: In flip-chip packaging, the semiconductor die is flipped over and attached to the package substrate, allowing for
shorter interconnects and improved heat dissipation. This is particularly useful for high-performance and high-power applications.
6. Organic Substrate Packaging: This involves using organic materials for packaging substrates, which can provide better electrical
performance and thermal characteristics compared to traditional ceramic substrates.
7. Embedded Die Packaging: In this approach, semiconductor dies are embedded directly into the substrate material, eliminating the need
for separate packaging. This can lead to thinner and more lightweight devices.
8. Advanced Interconnect Technologies: These include technologies like through-silicon vias (TSVs), micro-bumps, and micro-pillars that
enable high-density and high-bandwidth connections between different components within a package.
9. Heterogeneous Integration: This refers to integrating different types of chips, such as CPUs, GPUs, FPGAs, and more, from various
technology nodes into a single package, optimizing performance and power consumption for specific tasks.
Advanced packaging technologies are crucial for addressing the limitations of Moore's law, which predicts that the number of transistors
on a chip doubles approximately every two years. As transistors become smaller and more densely packed, heat dissipation, signal
integrity, and power consumption become more challenging. Advanced packaging techniques help overcome these challenges and enable
the continued advancement of electronic devices.
NCHU / EE / Prof. Fang-Hsing Wang 53 NCHU / EE / Prof. Fang-Hsing Wang 54

NCHU / EE / Prof. Fang-Hsing Wang 55 NCHU / EE / Prof. Fang-Hsing Wang 56

NCHU / EE / Prof. Fang-Hsing Wang 57 NCHU / EE / Prof. Fang-Hsing Wang 58

Date: 112.1.4( ) 9:10am~11:10am

Range: Chapter 12~20
Open-book test (
, )

NCHU / EE / Prof. Fang-Hsing Wang 60

NCHU / EE / Prof. Fang-Hsing Wang 59