Analog IC Design

類比積體電路設計

Dr. Tai-Haur Kuo

郭泰豪教授
Component Matching Issues

Department of Electrical Engineering

National Cheng Kung University
Tainan City 70101, Taiwan

September, 2020
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-1 郭泰豪, Analog IC Design, 2023
 Component Matching Issues
⚫ Effective component sizes differ from mask sizes
SiO2 protection
⚫ Examples
Well
◆ Lateral diffusion due to
➢ Ion implantation Lateral diffusion under SiO2 mask

➢ Annealing
SiO2 protection Polysilicon gate

◆ Overetching
Overetching

◆ Narrow channel effect

Polysilicon gate
➢ High doping density at the sides of transistors
Transistor channel
○ Due to channel stop implantation
➢ Decrease channel charge density at edges
➢ Decrease effective channel width
P+ field implants
Channel width narrowing

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-2 郭泰豪, Analog IC Design, 2023
 Component Matching Issues (Cont.)
⚫ Absolute component sizes can seldom be accurately determined. The
inaccuracies also affect the ratio of sizes (with a lesser degree) when
the ratio is not unity.

⚫ Matching second-order size error effects is done mainly by making

larger objects out of several unit-sized components connected together.
Also, for best ratio accuracy, the boundary conditions around all objects
should be matched, even when this means adding extra unused
components. (Examples given later)

⚫ Mismatch profile
◆ Random mismatch
◆ Gradient mismatch

→ Mismatch

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-3 郭泰豪, Analog IC Design, 2023
 Component Matching Issues (Cont.)
⚫ Random mismatch: Larger capacitance area → Smaller mismatch (%)

C=19fF
0.6
0.4
y=2.2x
0.2
(
0 0.1 0.2
⚫ Gradient mismatch: Larger capacitance spacing → Larger mismatch (%)
1st order 2nd order 1st + 2nd order
Gradient mismatch model Gradient mismatch model Gradient mismatch model

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-4 郭泰豪, Analog IC Design, 2023
 Transistor Layouts
⚫ Common-centroid layout for better matching accuracy
⚫ Example: A differential source-coupled pair
𝑆𝑀 ,𝑀2
𝐷𝑀

𝐺𝑀2
M3 M4

M1 M2
M1

M1
M2
M1

M2

M2

M1

M2
M2
M1

𝐺𝑀
MBias
𝐷𝑀2

◆ The layout for M1 and M2 is symmetric in both the X and Y axes, and
any gradients would affect both M1 and M2 in the same way
◆ This layout technique greatly minimize nonidealities such as
OPAMP input-offset voltage errors when using a differential pair
(M1/M2, M3/M4) in the input stage of an OPAMP
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-5 郭泰豪, Analog IC Design, 2023
 Capacitor Matching
⚫ Two major sources of match errors are due to
◆ Oxide-thickness gradient
➢ Common-centroid layout can be used to minimize this error
◆ Over-etching
➢ Capacitor area is smaller than mask area

X − 2Δe

Y − 2Δe Y

Δe

Ideal capacitor size True capacitor size

Δe

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-6 郭泰豪, Analog IC Design, 2023
 Capacitor Matching (Cont.)
⚫ Error can be minimized
◆ Use unit-sized capacitor
◆ Perimeter-to-area ratios are kept the same, even where the
capacitors are different sizes (Refer to p.104~106 of textbook).
10𝜇𝑚 6.72𝜇𝑚
e.g. A capacitor layout with equal 10𝜇𝑚
10𝜇𝑚
perimeter-to-area ratios of 4 units 10𝜇𝑚
and 2.314units 19.6𝜇𝑚

⚫ To minimize 2nd-order effect (Refer to p.106~107 of textbook)

Well contacts

c1 c2 Polysilicon bottom plate

Polysilicon top plates

c2 c1 Polysilicon edge matching

Well region

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-7 郭泰豪, Analog IC Design, 2023
 Resistor Matching
⚫ The structure below might result in about 0.1% matching accuracy of
identical resistors if the finger widths are relatively wide (say, 3μm in a
28nm technology)

𝑅 𝑅2 𝑅 𝑅2

Dummy resistor Dummy resistor

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-8 郭泰豪, Analog IC Design, 2023
 Noise Considerations in Analog Layout
⚫ Minimize noise in analog circuits
◆ Minimize noise from digital circuits coupling into substrate or analog
power supplies
◆ Minimize substrate noise that affects analog circuits

⚫ Example of noise reduction technique (Refer to p.109~112 of textbook)

◆ Use separate nets for analog and digital power supplies

I/O pad
Analog power-supply net Digital power-supply net

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-9 郭泰豪, Analog IC Design, 2023
 Noise Considerations in Analog Layout (Cont.)
⚫ Examples of noise reduction technique (Cont.)
◆ Separating analog and digital areas with guard rings and wells in an
attempt to minimize the injection of noise from digital circuits into the
substrate under the analog circuit.
VDD

Analog region Digital region

+ n+ P+
P N well
- Depletion region acts as
p substrate bypass capacitor

◆ Using shields helps keep noise from being capacitively coupled into
and out of the substrate. Analog interconnection
Digital
Ground line used interconnection
for shielding
𝑛+ 𝑛+ 𝑛+
N-well
-
p substrate
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-10 郭泰豪, Analog IC Design, 2023
 Noise Considerations in Analog Layout (Cont.)
Any unused space should be filled with additional contacts to both
◆
the substrate and to the wells, which are used as bypass capacitors.
⚫ A possible floorplan for an analog section containing switched-capacitor
circuits. 𝑉𝐷𝐷

Opamp1 Opamp2 Opamp3 OPAMPs

contact to substrate
𝐺𝑛𝑑
𝐺𝑛𝑑

N-well under capacitor region Capacitor

Region for n-channel switch

Switches
N well under p-channel switch region n well shield and
𝑉𝐷𝐷 bypass capacitor
𝐺𝑛𝑑
𝜑

𝜑
𝜑2 Clock lines
𝜑2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-11 郭泰豪, Analog IC Design, 2023
 Mismatch Effects in MOSFET Current Mirrors
⚫ Mismatch between M1 and M2: W/L ratio & Threshold voltage
⚫ Mathematical expression VDD
◆ Drain currents of M1 and M2
ID1 ID2
1 W 2
1 W 2
ID = μn Cox VGS − Vt , ID2 = μn Cox VGS − Vt2
2 L 2 L 2

◆ Define average and mismatch quantities

ID + ID2 Vt + Vt2 MN M1 M2
ID = , ΔID = ID − ID2 Vt = , ΔVt = Vt − Vt2
2 2
W 1 W W W W W
= + ,Δ = −
L 2 L L 2 L L L 2

◆ Substitute these expressions into ID1, ID2 (Neglect high-order terms)

2 2
1 W 1 W 1 W 1 W 1 W
ΔID μn Cox [ + Δ VGS − Vt − ΔVt − − Δ VGS − Vt + ΔVt ] Δ 2
= 2 L 2 L 2 L 2 L 2 ≅ L − ΔVt
ID 1 1 W 1 W 1 2
W 1 W 1 2 W (VGS − Vt
× μ C [ + Δ VGS − Vt − ΔVt + − Δ VGS − Vt + ΔVt ] L
2 2 n ox L 2 L 2 L 2 L 2
➢ Two mismatch components
○ Geometry dependent mismatch & Threshold voltage mismatch
➢ ID mismatch increases as (VGS-Vt) is reduced
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-12 郭泰豪, Analog IC Design, 2023
 Mismatch Effects in BJT Current Mirrors

𝑔𝑚 𝑅
Δ𝐼𝐶 1 Δ𝐼𝑆 𝛼𝐹 Δ𝑅 Δ𝛼𝐹 IREF
=( + (− +
𝐼𝐶 𝑔𝑚 𝑅 𝐼𝑆 𝑔𝑚 𝑅 𝑅 𝛼𝐹
1+ 𝛼 1+ 𝛼 IC1 IC2
𝐹 𝐹

⚫ gmR>>1 => 2nd term dominates

⚫ gmR<<1 => 1st term dominates R R R

Δ𝐼𝑠 Δ𝑅 Δ𝛼𝐹
⚫ gmR>>1 is preferred because > &
𝐼𝑠 𝑅 𝛼𝐹

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-13 郭泰豪, Analog IC Design, 2023
 Input Offset Voltage of Source-Coupled MOS Pair
⚫ Vos : Differential voltage → Make differential output voltage exactly zero
⚫ Define difference and average quantities
ID + ID2 R L + R L2
ID = , ΔID = ID − ID2 RL = , ΔR L = R L − R L2
2 2
W 1 W W W W W
Vt + Vt2 = + ,Δ = −
Vt = , ΔVt = Vt − Vt2 L 2 L L 2 L L L 2
2
ΔID −ΔR L
⚫ Let ID1RL1= ID2RL2 → = VDD
ID RL
VOS = VGS − VGS2 = (Vt + Vov − (Vt2 + Vov2 RL1 RL2
- out +
1 1
2 ID + ΔID ID − ΔID
2 2 M1
= ΔVt + ( W 1 W − W 1 W M2
un Cox + Δ − Δ
L 2 L L 2 L
Vin+ Vin-
(VGS − Vt −ΔR L Δ(W/L
≅ ΔVt + −
2 RL (W/L
(Neglect higher order terms)
◆ Mismatch components
➢ Threshold voltage mismatch
➢ Geometry dependent mismatch → Increase as (VGS-Vt) is increased
⚫ For same level of geometric mismatch or process gradient: Vos(MOSFET) > Vos(BJT)
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-14 郭泰豪, Analog IC Design, 2023
 Input Offset Voltage of Emitter-Couple BJT Pair
⚫ Offset voltage with resistor load

Δ𝑅𝑐 Δ𝐼𝑠 𝑑𝑉𝑜𝑠 𝑉𝑜𝑠

𝑉𝑜𝑠 ≈ 𝑉𝑇 (− − ; = RC RC
𝑅𝑐 𝐼𝑠 𝑑𝑇 𝑇

⚫ Offset current with resistor load Vin+ Vin-

𝐼𝑐 Δ𝑅𝑐 𝐼𝑐 Δ𝛽𝐹
𝐼𝑜𝑠 ≈− −
𝛽𝐹 𝑅𝑐 𝛽𝐹 𝛽𝐹
2IC

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-15 郭泰豪, Analog IC Design, 2023
 Common-Centroid Layout of BJT Pair
C1 C2

Q1 Q2
B2

B1
C1 C2

B1 B2
E
E

Q4 Q3

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-16 郭泰豪, Analog IC Design, 2023
 Input Offset Voltage of MOS OPAMP
⚫ Assume that the matching is perfect with inputs grounded
VOUT = VDD − VGS3 … (1
⚫ Differential input required to drive the output to the value given by (1) is the input-
referred offset voltage. With device mismatch, offset is usually nonzero.
VID = VGS − VGS2 = Vt + Vov − Vt2 − Vov2 … (2

⚫ Assume that λ of M1 & M2 are identical (VDS1 = VDS2 = VDSN when VID = VOS)
2I1 2I2
VOS = Vt − Vt2 + +λN VDSN k′(W/L 1
− k′(W/L 2
…(3)
VDD
⚫ Assume that the mismatches are small
VovN ΔIN Δ(W/L N M3 M4
VOS ≈ Vt − Vt2 + 2 IN
− (W/L N
…(4)
Vout
where I1 I2
Vin+ Vin-
2IN
VovN = k′(W/L N ( +λN VDSN
…(5)
M1 M2
I1 +I2
ΔIN = I − I2 …(6) IN = …(7)
2
(W/L 1 +(W/L 2
Δ(W/L N = (W/L − (W/L 2…(8) (W/L N = …(9)
2
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-17 郭泰豪, Analog IC Design, 2023
 Input Offset Voltage of MOS OPAMP (Cont.)
⚫ Since I1 = -I3 & I2= -I4 ,where
ΔIN ΔIP I3 +I4
IN
= IP
…(10) ΔIP = I3 − I4 …(11) IP = …(12)
2

⚫ Use KVL in the gate-source loop in the load to find ΔIp /Ip

0 = VGS3 − VGS4 = Vt3 + VOV3 − Vt4 − VOV4…(13)

⚫ Since M3 and M4 are p-channel transistors, their overdrives are negative. Assume
that the Early voltages of M3 and M4 are identical. Since VDS3=VDS4=VDSP when
VID=VOS , (13) can be rewritten as
VDD

2 I3 2 I4 M3 M4
0 = Vt3 − Vt4 − − …(14)
+ λP VDSP k′(W/L 3 k′(W/L 4
Vout
⚫ In (14), absolute value functions have been used I1 I2
Vin+ Vin-
◆ The arguments of the square-root functions are positive
M1 M2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-18 郭泰豪, Analog IC Design, 2023
 Input Offset Voltage of MOS OPAMP (Cont.)
⚫ If the mismatches are small, (14) can be approximated as
ΔIP Vt3 −Vt4 Δ(W/L P
≈ + …(15)
IP VovP /2 (W/L P

where 2 IP
VOVP = …(16)
k′(W/L P ( + λP VDSP

Δ(W/L P = (W/L 3 − (W/L 4 …(17)

(W/L 3 +(W/L 4
(W/L P = …(18)
2
VDD

M3 M4
⚫ Substitute (15) and (10) into (4) gives
VovN Vt3 −Vt4 Δ(W/L Δ(W/L N Vout
VOS ≈ Vt − Vt2 + 2 VovP
+ (W/L P − (W/L N
…(19) I1 I2
2
P Vin+ Vin-

M1 M2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-19 郭泰豪, Analog IC Design, 2023
 Parameter Relevant for Transistor Performance
⚫ T-like 0.18μm process

Parameter Symbol Typical value Absolute accuracy Matching accuracy

Threshold 𝑉𝑡ℎ 0.45 V ± 0.15 𝑉 5 mV
Gamma 𝛾 0.3 ~ 0.6 - -
Mobility (n) 𝜇𝑛 250𝑐𝑚2 /𝑉𝑠𝑒𝑐 ± 10% -
Mobility (p) 𝜇𝑝 80𝑐𝑚2 /𝑉𝑠𝑒𝑐 ± 15% -
Oxide
𝐶𝑜𝑥 9𝑓𝐹/𝜇𝑚2 - -
capacitance
Length L - 0.015 𝜇𝑚 -
Width W - 0.02 𝜇𝑚 -

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-20 郭泰豪, Analog IC Design, 2023
 Parameter Relevant for Capacitor Performance
⚫ T-like 0.18μm process

Parameter Symbol Typical value Absolute accuracy Matching accuracy

Dielectric 𝜀𝑅(𝑆𝑖𝑂2 3.9 - -
Oxide
𝑡𝑜𝑥 4.2 ± 0.2 nm ± 5% -
thickness
Poly-oxide
𝑡𝑝,𝑜𝑥 25 nm - -
thick
MIM 0.4% on p-well
𝐶𝑢𝑛𝑖𝑡 6.1 𝑓𝐹/𝜇𝑚2 -
capacitor 0.07% on n-well
VCC(PIP) VCC < 150 ppm - -
TCC(PIP) TCC < 50 ppm - -

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-21 郭泰豪, Analog IC Design, 2023
 Parameter Relevant for Resistor Performance
⚫ T-like 0.18μm process

Parameter Symbol Typical value Absolute accuracy Matching accuracy

Diff.
𝜌𝑑𝑖𝑓𝑓 200 Ω/sq 25 % 2%
resistivity
Poly
𝜌𝑝𝑜𝑙𝑦 150 Ω/sq 20 % 4%
resistivity
Diff.
𝑥𝑗,𝑑𝑖𝑓𝑓 80 nm 15 % 0.5 %
thickness
Poly
𝑥𝑗,𝑝𝑜𝑙𝑦 80~100 nm 15 % 1%
thickness

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 3-22 郭泰豪, Analog IC Design, 2023