IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 13, NO.

3, SEPTEMBER 1990 545

Dynamic Behavior of SMT Chip Capacitors During

Solder Reflow

Abstmct- A dynamic model of a surface mount packaging technology
(SMT) type 1206 chip capacitor is developed in this paper. The model
is used to determine the effects of pad geometry, chip metallization
and dimensions, solder volume, and chip displacement on the ability
of the chip to lift (tombstone) and to self-align during solder reflow.
Both static and dynamic characterizations are shown. The model simu-
lations show that the chip capacitor will begin to lift initially for some
geometries but tombstoning does not appear to be a problem. Thus to
help the self-alignment capabilities, the simulations show that system
configurations with smaller pad lengths, smaller pad gaps, larger sol-
der volume, and smaller metallization are best. These conclusions are
supported by existing recommendations based upon experimental tests.
The model is a powerful tool that can be used to optimize these system
parameters.
NOMENCLATURE
81 Contact angle of the lower solder fillet with respect to
the bottom chip edge (degrees).
192 Contact angle of the upper solder fillet with respect to
the end chip edge (degrees).
(Y Angle of inclination of the chip with respect to the
horizontal (degrees).
q5 Angle of inclination of line joining the chip pivot point
and the center of mass from the horizontal (degrees).
APo Change in pressure across the fillet surface at the bot-
tom of the fillet, or Psolder - Patmosphere (Pascals).
y Surface tension of the liquid solder (Newtons per mil-
limeters).
b Viscous friction coefficient between the solder and chip
metallization (Newtons-seconds).

Height of the chip component (millimeters). I. INTRODUCTION

Length of the chip component (millimeters).
Width of the chip component (millimeters).
Moment due to surface tension acting on the bottom S URFACE
electronics
conventional
mount packaging
manufacturers
through-hole
technology (SMT) provides
with numerous advantages over
technology. These advantages in-
of the chip component (Newtons-millimeters) .
Moment due to the hydrostatic pressure force clude increased functional density, smaller packages, increased
acting on the bottom of the chip component lead count, smaller circuit boards, and potential use of both
(Newtons-millimeters) . sides of the circuit board. The smaller packages and larger
Moment due to surface tension acting on the end of lead counts require accurate component placement, and vision
the chip component (Newtons-millimeters). assisted placement machines are now common. SMT com-
Moment due to the hydrostatic pressure force acting on ponents displaced from their circuit board pads during the
the end of the chip component (Newtons-millimeters). placement step reduce solder joint attachment reliability and
Moment due to the weight of the chip may cause electrical open or short circuits. A study of the
(Newtons-millimeters) . relationships between component placement offsets and solder
Mass of the chip component (grams). joint reliability would provide manufacturers with guidelines
Metallization width (millimeters). on the placement accuracy needed to ensure reliable solder
Center of pressure for the lower fillet (millimeters). joints.
Height of the upper solder fillet (millimeters). This paper describes an initial study to establish such re-
Center of pressure for the upper fillet (millimeters). lationships for SMT-type 1206 chip capacitors. The motiva-
Hydrostatic pressure force acting below the chip tion for focusing on these type capacitors is the following:
(Newtons). 1) these components are light weight and have a tendency to
Hydrostatic pressure force acting on the end of the move during solder reflow; 2) “drawbridging” or “tombston-
chip (Newtons). ing” defects occur during the reflow process; 3) experimental
Normal force acting on the chip at the contact point and analytical studies on chip capacitors can be found in the
(Newtons). literature for comparative purposes; and 4) the geometry of
the capacitor is simpler than for leaded components. The most
compelling reason for the study is that it has been reported by
Manuscript received July 1989; revised February 20, 1990. This paper was
presented at the Seventh International Electronic Manufacturing Technology Some that chip component placement accuracy is
Symposium, San Francisco, CA, September 25-27, 1989. not too critical since the surface tension forces of the solder
J. R. Ellis is with Sandia National Laboratories, Albuquerque, NM 87185. will tend to align the chip during reflow. Although
G . Y. Masada is with the Department of Mechanical Engineering, Univer-
sity of Texas, Austin, TX 78712. infcrred by many, few have actually studied this phenomenon
IEEE Log Number 9036643. in detail. Several variables are thought to influence the extent

0148-641 1/90/0900-0545$01 .OO O 1990 IEEE

546 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 13, NO. 3, SEPTEMBER 1990
U
w s
Fig. 1. Schematic of the Wassink and Verguld model.
to which SMT chips move during reflow. They include:
1) preheating the board assembly;
2) the direction that the component is placed on the board
(i.e., parallel/perpendicular to the direction of travel
through the reflow machine);
3) properties of the solder;
4) wetting characteristics of the chip;
5 ) dimensions and mass of the chip, including the amount
of metallization;
6) dimensions of the solder pads;
7) amount of solder paste applied:
8) placement offsets.
The focus of this paper is to develop a dynamic model of
a type 1206 chip capacitor during reflow. The parameters of
the model include: 1) chip wetting and solder properties, 2)
chip dimensions, 3) chip mass, 4) pad dimensions, 5) amount
of metallization, 6) solder volume, and 7) placement offsets.
This paper identifies the forces acting on the chip capacitor
during reflow and shows the effects of those parameters on
the ability of the chip to tombstone and to self-align.
11. PRIOR WORK
Although SMT is a rather new packaging technology, there
is an abundance of papers written on the subject. Surprisingly
enough, little has been written about the static forces acting
on the chip, and no literature focuses on the dynamics of the
chip motion. The following discussion summarizes work to
date on this topic.
A . Analytical Work
Perhaps the best chip model to date is one developed by
Wassink and Verguld [I]. The purpose of this static model was
to determine the magnitude of the torques acting on the chip
which tend to lift the chip and produce the tombstone defect.
The model, shown in Fig. 1, is a simple two-dimensional
model, but it provides some insight into some of the forces
acting on the chip. The forces that are included in the model
are identified as:
1) the gravity force acting on the mass of the chip (acts to
pull chip down);
2) the surface tension force of the liquid solder underneath
the chip (acts to pull chip down);
3) the surface tension force of the liquid solder of the solder
fillet at the right end of the chip (acts to lift chip up).
The model assumes that the solder on the left side pad of
the chip component has no effect and that the meniscus of
the solder forms a straight line (fillet profile) from the top
of the chip to the end of the pad in all positions of the tilting
component. Also, it assumes that the end of metallization lines
up with the inner end of the solder pad when the chip is
horizontal.
By computing the magnitudes of the static forces and the
moments at different angles of inclination of the chip, Wassink
and Verguld were able to determine whether or not the chip
would tombstone (depending upon the sign of the net mo-
ment). Angles of inclination varying from 0 to 90 deg were
used for both type 1206 and 0805 resistors, with variations in
the amount of metallization on the chip and in the solder pad
length. The results show that a delicate balance exists between
the moments acting to lift the chip and those which act to pull
it back down. Their conclusions are that by increasing the
amount of metallization on the chip and decreasing the length
of the solder pad, the tombstone effect on chip resistors can
be eliminated.
The authors admit that the model is simple, yet it provides
a very good qualitative feel for the effects of forces acting
on the chip. However, it does have several shortcomings. It
neglects the hydrostatic pressure forces acting on the chip
(both underneath and on the end of the chip), makes invalid
assumptions concerning the liquid solder interface contact with
the solder pad and the chip, and violates the conservation of
mass of the liquid solder as the angle of inclination changes
by assuming a straight line solder fillet.
B . Experimental Work
The dimensions for the SMT type 1206 capacitor are given
below [2]
Length, L 3.20 f 0.20 mm (126 f 8 mil)
Width, d 1.60 k 0.20 mm (63 f 8 mil)
Height, H 1.27 mm (max) (50 mil)
Metallization, W 0.5 f 0.25 mm (20 f 10 mil)
Mass, m 0.029 gm
Many experiments have been performed on SMT chip com-
ponents to determine optimal pad dimensions. Table I shows
a comparison of recommended pad sizes offered by individ-
uals for type 1206 chip capacitors using the chip dimensions
given above. In particular, the following individuals provide
the following equations (in millimeters):
Capillo [3]: W, = d + 0.254
Gap = L,,, - 2 W,,,- 0.254
Prasad [4]: L, =H + W +- 0.254 W,, = d f 0.254
Gap = L - 2 w - 0.254
Clements [ 5 ] : L , = W + 0.254 L , = L + 0.508.
Both Clements [5] and Vest [7] recommended that the pad
extend 0.254 mm (10 mil) beyond the end of the chip. No
recommendations on the solder paste thickness were given
in any of the prior works. Capillo and Clements both stated
their recommended results without any detailed background
information on how these results were obtained, but it was
assumed that they were based upon experimental tests. Kress
ELLIS AND MASADA: BEHAVIOR OF SMT CHIP CAPACITORS 547

TABLE I B. Moment Balance

COMPARISON
OF RECOMMENDEDPAD SIZES
IN MILLIMETERS
DIMENSIONS The moment balance is taken about the pivoting end of the
chip to determine its tendency to lift and tombstone. A coun-
terclockwise moment is considered positive. The net moment
h-7
Lt
I about the pivoting point, P, of the chip is

p P =Mt1 +Mpl +Mt2 +Mp2 + M , (1)

where the individual moments are defined as
Mtl =yWsin81 (2)

M p , = -.-F P 1 (3)
d wc

(6)

The change in angular momentum, using reference point P,

is

P s 4 Rp = M p- i=pcxm?p. (7)
Fig. 2. Free-body diagram of the chip component.
The hydrostatic pressure forces, Fpl and Fp2, and their dis-
tances, w c and hc, respectively, from the point P are com-
performed extensive tests, reported 4 pad widths, 5 gaps, and puted using a model of a flat plate submerged in a liquid [8].
1 pad length. She also provided a regression analysis that cor- The force and distance for the upper fillet are then given by
related the defects with the amount of overlap/extension (pad
extending beyond both sides of the metallization and sepa-
ration). Prasad's recommendations were based upon experi-
ments using 1 gap and 2 pad lengths. Vest's recommendations
were also based upon extensive tests whose details were not h --
h -
pgcosah3d (9)
discussed. Despite these experimental results, however, the c-2 12Fp2
wide range of recommended pad dimensions showed that ad-
where APo is Psol~er-Patmosp~ere at the end of the solder pad.
ditional work was necessary.
The hydrostatic force and displacement for the lower fillet are
found in a similar manner [8].
111. MODELDESCRIPTION
C . Force Balance
In this paper, a two-dimensional, dynamic model of the
forces acting on the chip component is developed. A free- From the free-body diagram of Fig. 2, the force balances
body diagram is shown in Fig. 2. The model includes many on the chip in the x and y directions are
of the specific details unaccounted for in the Wassink work.
Specifically, the meniscus of the solder is not considered to CF" y(sin (e2
= - CY) - COS (e, - Q))
be a straight line and the hydrostatic pressure forces are in- + F 1 s i n a - F 2 ~ 0 ~ ~ - b =xm~ x c (10)
cluded. Additionally, the constraint that the volume of solder
on the board is constant is always satisfied as the angle of C F=~-mg - COS (e, - a) + sin (e, - a))
inclination of the chip changes. Finally, the chip is allowed +F1cosa+F2sina++=mmj;,. (11)
to be displaced along its pad length to illustrate the effects of
chip displacement. Assuming that the position of the point P , the chip corner,
is always touching the board surface, the geometric relation
A . Assumptions between point P and the center of mass is
The following assumptions are made in the development of xc = x p f r c o s 4 yc =rsin$. (12)
this model: 1) the model focuses on the effects of only one Differentiating (12) with respect to time to obtain the kine-
solder joint, 2) the edges of the chip are perfectly straight matic velocity and acceleration equations and solving for the
and the corners are perfectly square, 3) the center of mass is acceleration of xp :
assumed to be at the geometric center of the chip, and 4) the
lower solder fillet is assumed to completely wet to the end of
the metallization.
.. = -
xp C F x
m
+
r ( i 2 cos 4 +4
sin 4). (13)
548 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 13, NO. 3 , SEPTEMBER 1990

Using the bottom of the fillet as a datum, and APo at the

bottom of the fillet as the reference point for calculation of
the pressure, A P can be written as

PreSSUre2 = Pm+ AP2+ pgh2 A P = APo - pgy (18)

since an increase in height decreases the pressure across the
solder fillet.
Qual pressures along
homntal line Substituting (16) and (18) into (17) and solving for
Fig. 3. Pressures in the solder fillet. (d2y / d x 2 ):

Substituting this term in the momentum equation (7) and solv-

ing for the angular acceleration: edx2
= -(pgy
y1
- (+
APo) 1 ($)2)3’2. (19)

4: +
XiMP E F x r sin4 + rn(r$)2s i n 4 c o s 4 Equation (19) is the second-order nonlinear differential equa-
(14)
(I, + rnr2(1 - sin2 4)) tions whose solution defines the fillet profile. Once the correct
fillet profile is known, the points at which the surface tension
Equations (13) and (14) describe the two-degree-of-freedom
forces and the pressure forces act can be computed. Note that
dynamic motion of the chip. All parameter values required
two boundary conditions are needed and that APo is an un-
in the above equations can be found except for the pressure
known.
change ( A P o )across the fillet, the height ( h ) of the upper
fillet, and the contact angles (0, and 02) which the surface ten- C . Upper Fillet
sion forces create with respect to the chip component. These
One boundary condition for the upper fillet profile is that
values are determined in the following section by finding the
the solder fillet must end at the edge of the solder pad:
profile of the solder fillet.
IV. FILLET
PROFILE xend = s u (20)
A . Pressure Continuity where S , is the amount of solder pad extending beyond the
In a static solder fillet, no pressure gradients exist horizon- end of the chip.
tally and the pressure in the vertical direction varies propor- Another condition is that the contact angle between the sol-
tionally to the distance from the fillet surface. Consequently, der fillet and the chip component at x = 0, under ideal con-
since the fillet profile decreases in height as one moves fur- ditions, is equal to the equilibrium contact angle of approxi-
ther away from the chip, a continuously changing pressure mately 12 deg [IO]:
differential must exist across the profile as shown in Fig. 3.

B. Laplace’s Equation
To find the pressure drop across the fillet, A P , Laplace’s A third condition, necessary to find APo, is that the total vol-
equation [9] is used to relate the pressure drop and the fillet ume of solder on the solder pad is known. The value for APo
surface geometry. In its most general form the equation is is iterated until the volume of the fillet matches the amount
AP =y (A + i) of solder known to be on the board. It was assumed that the
solder paste is 40% solder by volume [4].
where rl and r2 are the radii of curvature of the fillet measured D.Lower Fillet
normal to the surface in mutually orthogonal planes. For the
The differential equation describing the lower fillet profile
two-dimensional case of this study, this equation is assumed
is the same as for the upper fillet profile, but the boundary
to be approximately valid using only rl and setting Ilr2 equal
conditions differ. It is assumed that the standoff height (SOH)
to zero. This is equivalent to setting r2 equal to infinity (no
between the chip and the solder pad is very small, approxi-
curvature). Therefore
mately 0.01 mm; therefore, the initial height of the fillet must
A P = 1. (16) be
rl
The definition of curvature for a two-dimensional curve y = yi = Wsincu +SOH. (22)
Y ( X > is The other boundary condition required is that the solder fillet
dZy ends at the edge of the solder pad beneath the chip:

K =
dx2
-
1 -
--
1 xend = -s1 (23)
312 -r - radius of curvature’ where SI is the amount of pad beneath the chip.
The molten solder is assumed to have no horizontal pressure
(1 ($)2)
gradients; therefore, the APo used for the upper fillet is the
+

(17) same as for the lower fillet. The only parameter varied is
ELLIS AND MASADA: BEHAVIOR OF SMT CHIP CAPACITORS 549

0.8

8
Read important parameters
(chip type, amount of solder, Initialize boundary z
.- Od
pad geome!xy) and h i t i a h conditions for both
fillets. $ 0.4
pressure change, APo a
a
0.2

Iterate upper fillet height

by an incrementalsearch 0.0
profile for the given and shoot routine to fmd
pressure change. the upper fillet profile.
1 L o w a Fillet Indinatiap
I
* &

Iterate lower fillet angle

by an incremental search
0.15

0.10
and shoot routine to find
the lower Met profile.
Compare met volume 0.05
to known solder volume
and iterate the pressure
until the volumes math. calculate the total fillet
volume using 0.00
Simpson'sintegration 0.00 0.05 0.10 0.15 0.20 0.25 0.30
technique.
xDistance, mm
Volumes are equal,
the correa met Fig. 5 . Fillet profiles for a typical configuration.

Fig. 4. Algorithm for finding the fillet profile.

1) variation in metallization width: widths of 0.4, 0.5, 0.6,
and 0.65 mm (16, 20, 24, and 26 mil);
the lower fillet contact angle (with respect to the horizontal 2) variation in solder volume: stencil heights of 0.203,
x-axis). The angle is iterated until the profile matches the 0.254, 0.3084, and 0.3556 mm (8, 10, 12, and 14 mil);
3) variation in pad size: lengths of 1.27, 1.524, and 1.78
necessary end condition.
mm (50, 60, and 70 mil);
4) variation in gap between the solder pads: gaps of 1.27,
E . Overall Flowchart 1.524, and 1.78 mm (50, 60, and 70 mil);
An overall flowchart for finding the correct fillet profile(s) 5) variation in displacement from ideal placement in the x-
is shown in Fig. 4. direction: displacements of -0.2,0.0, and 0.2 mm (-8,
0, and 8 mil).
F. Example Profile
The analysis procedure consisted of displacing the chip from
The upper and lower fillet profiles were calculated for a chip its ideal placement and perturbing each of the parameters in-
capacitor with the following system parameters: 1.27 mm (50 dividually. Three displacements were tested: 1) ideal place-
mil) solder pads, 1.524 mm (60 mil) gaps between the solder ment, 2) maximum negative displacement from ideal, and 3)
pads, 0.6 mm (24 mil) of metallization, and 0.305 rmn (12 maximum positive displacement from ideal. The maximum
mil) stencil height. These profiles are shown in Fig. 5 for negative displacement is determined to be when the edge of
various angles of inclination. the metallization on the chip extends beyond the edge of the
Using the computation for the fillet profiles, the correct solder pad. The maximum positive displacement occurs when
contact angles, fillet height, and hydrostatic pressure required the solder flows over the top of the chip. Both of these cases
for the model can be found. Then both the static and dynamic reflect the limits of the model equations.
analyses can be performed.
B . Results
V. STATIC
ANALYSIS Fig. 6 shows a representative result from the static analysis.
The static analysis presented here examines the net moment The net torque and aligning force from one pad on the chip
and net force on the chip, which provides an indication of its are shown as functions of inclination angle and metallization
tendency to tombstone and to self-align, respectively. widths for a system with a solder pad length of 1.27 mm (50
mil), solder pad gap of 1.524 mm (60 mil), stencil height of
A . Analysis Procedure 0.3048 mm (12 mil), and an initial displacement of -0.2 mm.
Since a wide range of chip metallization widths and pad di- Notice that for a large amount of metallization, the restoring
mensions exist, parameter values near the average were chosen moment increases and the net force on the chip is positive.
and perturbed to determine sensitivities. The average config-
uration was chosen to have a 1.27 mm (50 mil) pad length, C . Discussion
1.524 mm (60 mil) pad gap, 0.6 mm (24 mil) metallization 1) Static Moment Balance: A positive moment, in the
width, and 0.3048 mm (12 mil) stencil height. The following counterclockwise direction, is desired to pull the chip down
five different sets of parameter variations were analyzed: from its inclined position. In all of the system configurations
550 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 13, NO. 3 , SEPTEMBER 1990

However, when the metallization does cross over the end of

the pad, the geometry of the lower solder fillet is such that
the other solder surface tension (of the other pad) will act to
pull the chip back toward center. A positive force is accept-
able when the chip is subject to a negative displacement, but
is unacceptable for a positive displacement because it accen-
tuates the misalignment. In general, the following trends were
apparent in the analysis and are listed in the order of greatest
0 5 10 15 20 effect on the system.
0.35 1) Shorter solder pad lengths increase the negative forces
0’30 0.4 m m on the chip (aid self-alignment).
2) Shorter solder pad gaps increase the negative forces on
the chip.
,w 0.15 3) Larger amounts of solder (larger stencil height) in-
creases the negative forces on the chip.
4) Smaller chip metallization increases the negative forces
0.00
on the chip.
-0.05
10 15 20 A decrease in solder pad length, a decrease in the pad gap, or
Angle of Inclination, deg an increase in the amount of solder applied will generally all
Fig. 6 . Sensitivity of torque (N*mm* 10-4/mm) and force (N* 10W’imm) increase the height and internal pressure of the upper solder
to variations in metallization (-0.2-mm initial displacement). fillet. An increase in fillet height increases the wetted area,
and hence, the negative pressure force on the chip. The in-
analyzed, the net moments imposed on the chip were positive, creased pressure also increases the negative force applied. In
indicating that no tombstoning will occur. The static moment addition, decreasing the pad gap increases the distance be-
analysis showed the following trends. tween the metallization and the end of the pad. The distance
1) The larger the metallization, the larger the positive mo- decreases the angle of the fillet underneath the chip with re-
ment on the chip. spect to the x-axis, and in turn, increases the negative force
2) A decrease in stencil height increases the positive mo- applied.
ment on the chip. The main effect of a decreased metallization width is a de-
3) The solder pad length has little effect on the net moment crease in the angle of the fillet underneath the chip. Also, at
at low angles of inclination, but as the angle increases, large angles of inclination, smaller metallization increases the
the smallest pad length gives the best results. amount of solder in the upper fillet. The effect of this is sim-
ilar to increasing the amount of solder placed on the board.
4) The larger the gap between the solder pads, the larger
Both of these effects cause an increase in the force applied on
the positive moment on the chip.
the chip in the negative x-direction.
The results can be explained as follows. An increase in the Notice that some of the static force results conflict with the
amount of metallization increases the moment the arm through trends reported above for the static moment balance. How-
which the lower surface tension acts and increases the angle ever, because the analysis shows that for the configurations
of the fillet underneath the chip with respect to the lower chip used, the type 1206 chip capacitors will not tombstone, em-
edge. Both effects increase the positive moment applied. An phasis should be placed on the trends which cause negative
increase in the pad gap or a decrease in the amount of solder forces on the chip.
applied will generally decrease the height of the upper solder
fillet which decreases the moment through which the upper VI. DYNAMIC ANALYSIS
surface tension acts, thus increasing the positive moment ap- A series of dynamic simulations were performed to analyze
plied. One of the major components of the positive torque is the effects of the imposed forces on the movement of the chip.
the torque due to the weight of the chip. Therefore, a lighter Assumptions made in this analysis are: 1) the solder melts
chip component, such as a type 1206 chip resistor (typically instantaneously, 2) the metallization is wetted completely, and
0.010 g) will have a much greater tendency to tombstone than 3) the solder fillet rises to its equilibrium position at all times,
the type 1206 chip capacitor (typically 0.030 g). hence, a quasi-equilibrium condition exists. As in the static
2) Static Force Balance: In addition to the lifting of the analysis, solder effects on only one side of the chip component
chip, the static analysis can be used to compute the forces act- are considered. Results of these analyses were compared with
ing on the chip that will move the chip in the x-direction. In observations from high-speed videos of the melting process
general, for the displacements analyzed, a negative alignment [ 1 11. The videos compare different system configurations and
force is desired (see positive x-direction convention) which chip offsets for type 1206 capacitors.
will push the chip toward the other solder pad where it will
eventually be wetted by the molten solder. Note that, due to A . Method
the limitations in the fillet model, none of the systems ana- The motion of the chip is found by integrating the dynam-
lyzed allowed the metallization to extend over the solder pad. ical equations using a fourth-order Runge-Kutta integration
ELLIS AND MASADA: BEHAVIOR OF SMT CHIP CAPACITORS 55 1

mm displacement. One configuration has a small pad length

(1.016 mm) and large solder volume (0.35-mm stencil height)
Set initial conditions while the other has a large pad length (2.032 mm) and small
cm dynamic equations:
position, angle, solder volume (0.203-mm stencil height). Though these sys-
tems were not included in the static analysis, they represent
two configurations which appeared to provide significant dif-
Profile Flowchm.
ferences in dynamic behavior.
The plots shows that the chip with the smaller pad initially
and fora on the chip lifts up but quickly drops back down, and more importantly,
it self-aligns by moving in the negative-x direction. The chip
. . L end of the solderpad on
with the larger pad quickly drops back down to the horizontal;
?&laUmurn
does not cross. the next time step. however, it moves to accentuate the misalignment.
continue
simulation
C. Discussion
crosses, end
the simularion As reported in the static analysis, it was apparent from
the simulated chip motion that tombstoning is not a problem
Fig. I . Algorithm for dynamic simulations.
for the configurations chosen for the type 1206 chip capac-
itors. Although none of the chips tombstoned, some lifting
was apparent. In the simulations, the configurations which had
d greater tendencies to lift were ones with small metallization,
large solder volume, small pad length, and small pad gap. By
comparison, the lifting and dropping response of the chip as
it slides inward was a characteristic of the chip motion shown
1.016. .35 in the high-speed videos. One problem with lifting is that an
inclined chip is somewhat less stable than one that is horizon-
0.m 0.w2 0.004 0.006 0.m 0.010 tal and may be subject to twisting if not centered along the

-
2.032.,203
4.3
0.m 0.m2 0.m om 0.m
Time, sec
Fig. 8. Dynamic responses of two configurations (initial inclination of 5
deg, 0.1-mm displacement).
algorithm. The procedure used in the dynamic simulations is
flowcharted in Fig. 7. Using a 0.001-s time step, a typical sim-
ulation on an IBM 3081 computer required approximately 250
s of CPU time. Therefore, only a limited number of dynamic
comparisons were made on systems which would appear to
provide large motion differences as implied by the static mo-
ment and force analyses.
In each set of comparisons, the initial conditions assume that
the chip is initially misplaced with an angle of inclination due
to uneven melting of the solder paste. Based upon a possible
configuration of the chip initially starting with one of its ends
on unmelted solder paste and the other end touching the pad
surrounded by melted solder, initial inclinations of 0 and 5
deg were used [8].
B . Results
Fig. 8 shows a representative plot from the dynamic analy-
sis. Both linear and angular displacements are shown as func-
tions of time. This simulation compares system two configu-
rations having 1.778-mm gap, 0.5-mm metallization, and 0.1-
width of the pad.
As implied in the static analysis, self-alignment is an impor-
tant consideration when choosing pad geometries for chip ca-
pacitors. In the simulations, differences in metallization widths
did not have a great effect on the tendency to realign; however,
changing the pad size, pad gap, and stencil height had large
0.010
effects. Additionally, the simulations show that the trends dis-
cussed in the static analysis are also valid for the dynamic
simulation. Specifically systems which contain large pad size,
large pad gap, and small solder volume tended not to self-
align. In fact, for these configurations at an initial inclination
of 5 deg, the chips moved in a manner which increased the
misalignment.
A partial explanation for the tilting of the chip and the out-
ward motion of the chip comes from the dynamical equations.
From (13), it is apparent that angular acceleration and veloc-
ity influence the acceleration in the x-direction. The outward
motion of the chip in some simulations is partially caused by
the initial angular acceleration and velocity induced when the
chip drops from its initial inclination. Likewise, from (14),
it is apparent that the force in the x-direction influences the
angular acceleration. The tilting of the chip is partially due
to the large realignment force present. Because the torque on
the chip generally increases as the end of the metallization
approaches the end of the pad, the chip is pulled down as it
moves inward.
Finally, varying the contact angle between the edge of the
chip and the solder meniscus gave a measure of the sensitivity
of the results to conditions which may cause a different angle
than the assumed 12-deg equilibrium angle. The simulation
results are sensitive to the contact angle, particularly with re-
spect to the amount of angular displacement seen. Therefore,
552 IEEE TRANSACTIONS ON COMPONENTS. HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 13, NO. 3, SEPTEMBER 1990

oxidized or rough metallization, which would tend to increase As this study concluded, longer pad lengths cause the chips
the contact angle due to poor wetting and contact angle hys- to lift and to decrease the self-aligning forces acting on the
teresis, may promote further lifting of the chip. displaced chip. The shorter gap ( ~ 1 . 7 7 8mm) recommended
In all of the simulations, the total time required for the chip
in this paper is smaller than those recommended by others
to move was very short compared to the times seen in the high- ( 1.626-2.184 mm). The shorter gap increases the restoring
speed videos. One of the largest factors in the time difference force from the fillet at the bottom of the chip. This effect
is that the melting and wetting process is not instantaneous of shorter gaps was found to be second only to the length
as is assumed in the simulation; in fact, this process usually of the pad in aiding in the self-alignment characteristics of
takes a few seconds. Another factor is the amount of friction inthe displaced chip. The total length of the pad configuration
the system. In this model, only viscous friction was assumed, is approximately 3.962 mm, which compares well with data
however, some form of static friction and dynamic friction is from Kress, Clements, and Vest. It should be stressed that the
probably present due to uneven parts of the metallization slid- values referred to in this paper are not optimal values but re-
ing on the solder pad. This would suggest that more friction flect the trends that short pad lengths, short gaps, and smaller
is required in the model, which would slow down all of the metallization ( ~ 0 . 3 5mm) will tend to self-align chip capac-
responses. However, in general, the qualitative trends shown itors. Finally, the smaller metallization length is helpful but
in the simulations were similar to the trends observed in the is of secondary consequence. However, initial studies show
high-speed videos. that smaller metallization makes the lighter resistor more
VII. CONCLUSION prone to tombstoning .
In summary, the trends reported from this model agree quite
Because the tendency toward tombstoning for type 1206 well with those of Kress, Clements, and Vest. It is particu-
chip capacitors is small, the emphasis in parameter selection larly encouraging since the Kress work appears to be the most
should be placed on the self-alignment characteristic of the extensive experimental tests reported to date.
component. Thus a configuration with small pad size, small
pad gap, large solder volume, and smaller metallization pro-
vide the best alignment results. Based upon this study, a sat-
isfactory configuration within the range tested in this project REFERENCES
would be a configuration with a 1.016 mm (40 mil) pad length, R. Wassink and M. Verguld, “Drawbridging of leadless components,”
1.778 mm (70 mil) pad gap, 0.4 mm (16 mil) metallization, Hybrid Circuits, no. 9, pp. 18-24, Jan. 1986.
Ceramic Chip Capacitors Catalog, Coming Glass Works, Coming,
and 0.35 mm (14 mil) stencil height. NY, 1986.
Some aspects of this work are difficult to compare with C. Capillo, “How to design reliability into surface-mount assemblies,”
the prior work. Obviously, the static model presented is much in Proc. Nepcon West, vol. 2, Anaheim, CA, Feb. 25-27, 1986, pp.
857-863.
more detailed than any analysis to date. Also, no other dynamic R. Prasad, “Surface mount land patterns and design rules-The key to
model has been reported to date. Experimental test results SMT reliability,” in Proc. Nepcon West, vol. 2, Anaheim, CA, E b .
listed previously do provide some basis for comparison. 25-27, 1986, pp. 829-834.
J. Clements, “Tombstoning prevention and surface-mount production,”
The model developed in this study is two-dimensional, so Electron. Pack. Product., vol. 4, pp. 82-83, Apr. 1987.
the effect of the pad width is not a model parameter. How- E. Kress, “Solder pad geometry studies for surface mount of chip ca-
ever, comparisons of the recommended pad width show the pacitors,” in Proc. 35th Electronic Component Conf . Washington,
D.C., May 1985, pp. 206-212.
least variability in the experimental results reported previ- R. Vest, personal conversation, Texas Instruments Inc., Austin, TX,
ously, which may indicate that it is not as important as other Sept. 1988.
parameters. Also, the amount of solder used in the experi- J. Ellis, “Dynamic behavior of surface mounted chip components during
solder reflow,” M.S. thesis, Dep. Mech. Eng., Univ. Texas at Austin,
mental work was not specified, and therefore, cannot be com- May 1988.
pared. However, the pad sizes and gaps were reported but P. S. Laplace, Mecanique Celeste, Suppl. 10th Vol., 1806.
showed a wide range of recommended values. T. Chu, “A hydrostatic model of solder fillets,” Western Elec. Eng.,
Vol. 19. NO. 2. DD. 31-42. Am. 1975.
The shorter pad lengths
- ( ~ 1 . 0 1 6mm) inferred in this pa- [ I l l “High-speed video: Reflow of type 1206 chip capacitors,” Dep. Mech.
~
L 1

per compare well with those of Kress, Clements, and Vest. Eng., University of Texas, July 1986.