CVR COLLEGE OF ENGINEERING

UGC Autonomous Institution - Affiliated to JNTUH

Vastunagar, Mangalpalli(V), Ibrahimpatan (M), R.R.Dist–501 510.

M.Tech. I Year II Semester Main Examinations Sept -2022

Subject Name: Low Power VLSI Design
Branch Name: VLSI System Design
Time: 3 hours Max. Marks: 70

(Answer Any 5 Questions) (5 X 14 = 70 Marks)

1.a) Analyze how the transistor sizing and gate oxide thickness will Bloom’s Level [4]CO1 7M
affect the power dissipation.

b) Explain the effects of VDD and Vth on speed of the MOS Bloom’s Level [2]CO1 7M
transistor.

2.a) Analyze how the high capacitance nodes will occur in CMOS Bloom’s Level [4]CO2 7M
circuits. What are the mechanisms to reduce the power
consumption due to high capacitance nodes?

b) Discuss about the retractile and reversible pipeline logics Bloom’s Level [5]CO2 7M

3.a) Construct and derive the expression for tolerable clock skew Bloom’s Level [3]CO3 7M

b) Discuss in detail about two level clock distribution scheme. Bloom’s Level [5]CO3 7M

4.a) Explain different power minimization techniques. Bloom’s Level [2]CO4 7M

b) Construct the differential voltage switch logic based full adder Bloom’s Level [4]CO4 7M
and explain its operation.

5.a) Explain about data retention power sources in DRAM Bloom’s Level [2]CO5 7M

b) Explain various active power reduction techniques in SRAM. Bloom’s Level [2]CO5 7M

6.a) Construct and derive the expression for switching power Bloom’s Level [3]CO1 7M
 dissipation of MOS transistor.

b) Explain the impact of technology scaling on MOS transistor Bloom’s Level [2]CO1 7M
operation.

7.a) Develop an 8-bit Wallace tree multiplier and explain its Bloom’s Level[3]CO4 7M
operation.

b) Develop the 8-bit conditional sum adder using 1-bit full adders Bloom’s Level [3]CO4 7M

8.a) Analyze the chip and package Co-design of clock network in Bloom’s Level [4]CO3 7M
terms of low power consumption.

b) Explain about data retention power reduction techniques in Bloom’s Level [2]CO5 7M
SRAM.

END OF THE QUESTION PAPER