1

2 Company :
3 Engineer :
4
5 Create Date : 14:13:04 05/06/2022
6 Design Name:
7 Project Name: Display_7_segmentos
8
9 LIBRARY ieee;
10 USE ieee .std_logic_1164.ALL;
11
12 ENTITY disp_hex_mux_TEST IS
13 END
disp_hex_mux_TEST; 14
15 -ARCHITECTURE behavior OF disp_hex_mux_TEST IS
16
17 -- Component Declaration for the Unit Under Test
(UUT) 18
19 COMPONENT disp_hex_mux
20 PORT (
21 sel : IN std_logic_vector (l downto O );
22 hex in : IN std_logic_vector (3 downto O );
23 an : OUT std_logic_vector (3 downto O );
24 sseg : OUT std_logic_vector (6 downto 0)
25 );
26 END COMPONENT ;
27
28 --Inputs
29 signal sel : std_logic_vector (l downto 0) .- (others
=> 'O ');
30 signal hex_in std_logic_vector (3 downto 0) .- (others
=> 'O '); 31
32 --outputs
33 signal an : std_logic_vector (3 downto O );
34 signal std_logic_vector (6 downto O );
sseg 35
36 BEGIN
37
38 Instantiate the Unit Under Test (UUT)
39 uut : disp_hex_mux PORT MAP
40 sel => sel,
41 hex_in => hex_in ,
42 an => an ,
43 sseg => sseg
44 );