SECTION A-(10X1=10 Marks)

1. b) AS-TTL
2. d) All of the Mentioned
3. b) false
4. b) 7ft
5. a) Dis high, clock changes from low to high
6. d) ECL
7. d) CMOS circuits
8. a) The higher value
9. a) ii-i-iii-iv
10. a) True

SECTION B-(5X3=15 Marks)

11. a) To reduce static current during sleep mode is to turn off the power supply to the
sleeping blocks, such technique is called power gating. Explanation-2mark,
Diagram-1mark
or
b) Transistor size optimization is one method to reduce the power dissipation of
CMOS very large scale integration (VLSI) circuits. (2 mark)
Effects-1 mark

12. a) The shape of a transistor gate is rectangular and the width and length of the gate
determine its capacitance (3 mark)
or
b) It is a measure of its spectral power distribution. The concept is based on the
Shannon entropy, or information entropy, in information theory. (3mark)
13. a) Pre-computation logic explanation-2 mark, Diagram-1mark
or
Low power digital cell library definition-1mark, explanation-2 mark.

14. 14.a) Switching activity reduction in low power architecture explanation-2 mark,
diagram-1 mark
or
b) Switching activity reduction explanation-3 mark
Diagram-2 mark

15. a) Design flow process explanation-3 mark, flow chart-2 mark

or
Power optimization methods -1 mark, explanation-3 mark, diagram-1 mark

SECTION C-(5X5=25 Marks)

16. 16.a) Dynamic dissipation definition-2 mark, explanation 3 mark

or
b) Low power approaches explanation-3 mark, diagram-2 mark
17. a) Capacitive power estimation explanation-3 mark, derivation-2 mark
or
b) Probabilistic power analysis techniques explanation-4 mark, Derivation-2 mark

18. a) Flip flop explanation-2 mark, latches-2 marks, diagram-1mark

or
b) Logic level power designs types-1 mark, explanation-3 mark, diagram-1 mark

19. a) power dissipation explanation-3 mark, derivation-2 mark

or
 b) power dissipation explanation-5 mark

20. a) Low power architecture-explanation-2 mark, architecture diagram-2 mark

or
b) Chip and package co-design of clock network explanation-5 mark