Revised Regulation- 2008

Reg. No:
(A)

SRI RAMAKRISHNA ENGINEERING COLLEGE, COIMBATORE

(Autonomous Institution, Approved by AICTE and Affiliated to Anna University, Chennai)
AUTONOMOUS EXAMINATIONS – MAY 2014
THIRD SEMESTER - B.E ELECTRONICS AND COMMUNICATION
ENGINEERING
08AC304 - DIGITAL ELECTRONICS
Answer ALL questions
Duration: 3 Hours Maximum: 100 Marks
PART - A (10 x 1 = 10 Marks)

1. The decimal equivalent of the given number is B2F16

a) 286310 b) 123410 c) 158410 d) 587410

2. What is the total range of decimal values represent in eight bits?

a)255 b)187 c)222 d)357

3. How many AND gates are required to realize Y = CD+EF+G?

a)2 b)3 c)4 d)5

4. An n variable k map can have

a) n2 cells b) 2n cells c) n2n cells d) nn cells

5. How is a J-K flip-flop made to toggle?

a) J=1,K=1 b) J=0 K=1 c) J=0 K – = 0 d) J=1 K=0

6. A…….. Counter is a type of counter composed of a circular shift register

a) ring b) Johnson c) shift d) both (a) & (b)

7. When the change of internal state occurs in asynchronous sequential circuits

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 a)When there is a change in input variable b) When there is a change in output
variable
c) When there is a change in intermediate variable
d) When there is a change in state variable
8. Unwanted switching transients that appear at the output of a circuit because different
paths exhibit different propagation delays are
a)Noise b)Hazards c)Interference d)Disturbance

9. EEPROM is
a)Electrically Erasable PROM b)Electronically Erasable PROM
c)Electro magnetically Erasable PROM d)Magnetically Erasable PROM

10. PLA is
a)Projected logic array b)Programmable Logic array
c)Product logic array d)Programmable logic addition

PART - B (5 x 2 = 10 Marks)
11. List the advantages and limitation of analog and digital systems?
12. Reduce the expression A[B+C(AB+AC)]
13. Mention the different shift registers.
14 What do you meant by state diagram?
15. What is EEPROM?
PART - C (5 x 16 = 80 Marks)
16. a) Design the logic circuit for 4 Bit GRAY to BCD Conversion using (16)
map method.
(OR)
b) Expand the following to minterm and maxterm.
i) ACD + ABC′ + ACD′ + ABCD (8)
ii) A (A′+BC) (A′+ BA + C′) (8)

17. a) Reduce the following to SOP and POS using map method. (16)
F (a,b,c,d,e) = π M (1,2,3,13,15,16,18,21,24) π d(25,26,27,30,31)
(OR)
b) Reduce the following using tabular method and draw the logic (16)

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 diagram
F(w,x,y,z) = Σ m(1,2,3 6,7,9,10,13) + d (1,4,5,11,12)

18. a) Convert S-R FF to J-K FF and D FF to S-R FF (16)

(OR)
b) Design the circuit to eliminate various types of hazards with example (16)

Compulsory Question:
19. Design the counter that goes through states 1, 2,4,5,7,8,10,11,1… (16)
using JK flip flop.

20. a) Compare and contrast programmable logic array and programmable (16)
array logic.
(OR)
b) Write the classification of memories. Explain. (16)
*****

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