369
INTRODUCING DIGITAL SIMULATION INTO AN ANALOGUE REAL-TIME POWER SYSTEM
SIMULATOR
B Giick I), T Gallenkamp 'I, T Wess
') FGH Mannheim, Germamy 2, Technische Hochschule Darmstadt, Germany
ABSTRACT
A new digital real-time simulator (DRTS) with a high-
resadution, high-speed interface to an analogue simu-
lator (ARTS) is presented. The ability of the DRTS is
shown at an experimental setup, using the ARTS for
modelling a point-to-point HVDC transmission system.
The multiprocessor DRTS simulates a synchronous
generator with a 50 ps calculation time step.
1. INTRODUCTION
Power system simulators are indispensable tools for
testing control and protection equipment in HVDC and
FACTS applications and for investigating the overall
dynamic system performance, With the advent of
powerfid and fast digital :signal processors (DSP) it is
possible to supplement or replace the commonly used
physical or analogue simu1:ators.
The proved analogue parity simulator (Joetten et a1 (1))
of FGH is presently upgiraded by introducing digital
simulation components. The digital real-time simulator
(DRTS) described in this paper was developed origi-
nally at the Technical University of Darmstadt,
Germany (Gallenkamp (2)). At the FGH, basically only
the iinterface to the analogue world had to be added.
At the experimental setup described in this paper, the
DRTS reproduces the dyiximic behaviour of a synchro-
nous generator (SG) with machine transformer. The
DRTS is coupled with the analogue real-time simulator
(ARTS), where a benchmark model for HVDC control
studies is simulated (Fig. 61).
2. THE DIGITAL REAL-TIME SIMULATOR
Entry and compilation of the model
To simulate a subsystem of a power system, the mathe-
mat ical representation is first entered graphically by
using a schematic editor. ;For example, Figure 1 shows
the graphical description !of the q-axis of the synchro-
nous generator. This block. diagram is the graphical re-
presentation of the diffcxential equations (standard
space form). Under the block names (here GAI and
INT), the block parameters are printed. The blocks are
accessed from a picture library (of the schcmatic
editor), such as integrators, amplifiers, adders etc. By
'AC and DC Power Transm,ission',29 April-3 May 1996. Conference Publication No. 423'0 IEE, 1996
the name of a block, each block is assigned one or more
code sequences from a code library.
Figure 2 shows the general data flow from entering the
system's model graphicallly (using an off-the-shelf sche-
matic capture program) to the assembly code for the
DSPs. A netlist formatter being part of the schematic
capture program generates a netlist, which contains the
interconnection information of the model in a specific
textual format. Later on, the compiler - being part of
this work - parses the netlist and outputs the assembly
code. For a more detailed1 description of the compilation
process see (2). In this paper only the basic features of
the DRTS are described.
As some blocks require one or more parameters, these
can optionally be represented by symbolic names. The
values of the symbolic parameters are defined in a text
file (called parameter ilk). Furthermore, mathematical
expressions of numerical constants and symbolic para-
meters are equally allowed at both, the graphical and
the parameter file input. To support a hierarchical
description of the model (which is provided by the
schematic editor), local and global symbolic parameters
are distinguished. These features improve the readabi-
lity of the model representation and support multiple
simulation runs with difkrent parameter sets.
One major task of the compiler is to partition the model
automatically, to make use of multiple parallel pro-
cessors. This makes it possible to simulate complex
power systems, even though the calculation speed of the
single DSP is limited. In order to get efficient perfor-
I
4omega m
INT
0
Figure 1: Graphical dlita entry, example
 370

Simulation The hardware structure

model
Interactive
graphical
The prototype setup of the DKTS consists basically of
input Simulation three parts (see Fig. 2 and 3):
code
(Assembler)
I
- multiple DSP boards per ,,computing rack"
- one General Purpose Card (GPC) per ,,computing
rack
- analogue input and output (separate rack)

Basically only the GPC had to be newly developed, the

other components are commercially available or
existing proved cards of the parity simulator.

DSP Boards. The processor boards are based on the

To
Analogue I / 0 - Rack
Figure 2: Model design and interaction
m n c e from a multiprocessor system, the following two
main topics should be treated: Firstly, the compu-
tational load has to be equally distributed on the proces-
sors. Secondly, the interfaces between the processors -
running the simulation of the model's subparts - are to
be minimized. Unfortunately these topics are closely
related and cannot be optimized separately. In addition,
some systems are not suitable for parallelization at all.
It is difficult to find a nearly optimum solution to this
partition problem by hand, that is entering into the
simulator which block to run on which system. Also,
the optimum solution changes with an update o f the
model.
digital signal processor TI TMS320C30 with local
RAM.In order to get an effective realization of the
multiprocessing ability, a low cost processor board was
chosen, where only few changes of the hardware were
necessary.
Computing Rack
General Purpose Card (GPC). The main functions of
this card are:
- bus arbitration
- sharedRAM
- transient recorder (4 Mbytes)
- remote interface to a standard PC
- interface to 6 D/A converters and 6 A/Dconverters
The transient recorder uses FIFO (First In, First Out)
buEers between its RAM and the shared bus, so the
Computing Rack
r - - - - - - - - 1
I DSP cards I

The implemented parallelization algorithm finds an

nearly optimal solution by exploiting the time-delaying
effect of some blocks such as integrators (explicit
integration methods are used).

Interactions during a running simulation

To observe the current simulation mn, an on-line

graphical visualization routine is implemented (see
Fig. 2). This function is similar to the roll mode of a
digital storage oscilloscope. The simulation data can be
read graphically and numerically without influencing
A

1
the simulation run. Furthermore, the parameters of a
block can be edited on-line, without reloading the
execution code. The on-line access to the simulation
data is made possible by the specialized hardware
structure of the General Purpose Card (GPC) of the
DRTS, see below. The recording of the simulation
Analogue 110 Rack
results at the GPS can be stopped (without stopping the L - - - - i
simulation), so that these data can be stored to the hard
disk of the connected PC. Figure 3: Hardware overview
 371

above-mentioned on-line data access is possible. + 5.0

r
Anialogue UO. A separate ,,analogue I/O rack' contains
basically :

- 6 D/A converters (16/1.8 Bit, 5OOkHz) with filters

- 6 A D converters (16/18 Bit, 200kHz) with filters
- 6 voltage amplifiers or
- 6 voltage controlled current sources
The: ,,analogue VO rack" is serially connected to the
,,co mputing rack, using high speed optocouplers for
galvanic decoupling. For the A/D and D/A conversion
including filters, commer'cial boards were used, where
the voltage controlled current sources (or the voltage
amplifiers) were realized with standard cards of the
existing parity simulator.
Future expansions
The actual prototype setup uses only one computing
rack with two processor cards. The speedup when using
more processor cards is limited due to communication
time (among other things) between the processors (see
Alniasi (3)), since all the communication data is
transferred through the single shared external bus. If
complex power systems are to be calculated, the
computing task has to be divided onto several racks.
Then high speed connec! ions between the computing
racks are necessary.
When simulating power electronics digitally, it is
supposed that additional hardware is necessary to get
results with sufficient accuracy. For example, if the
firing pulses for a rectifier or inverter are fed into the
DR'TS, they should be registered with a high resolution
in time (see Rebhan (4)).
3. THE SYNCHRONOUS GENERATOR
Since the focus of this work is the Digital Real-Time
Simulator and the achieved experimental results, the
mal hematical model of the synchronous generator is
not presented in detail. Tlhe generator is modelled as a
salient-pole synchronous machine, with one damper
winding in the direct-(d) and quadrature-(q) axis each.
The machine is represented in rotor-fixed dq-coordi-
nates with Park's transformation to and from the three-
phase system (Bonfert (5)). However, the state variable
normal form is strictly used, with the fluxes as main
variiables and the currenls as auxiliary variables (see
(1)). Mutschler (6) found this the most time-eflficient
way to simulate a synchronous machine.
To consider the magnetic saturation of the d a i s it is
Figure 4: Excitation system model
VT = Generator terminal voltage
Em = Generator field voltage
KA =400 TA=O.SS
KF ~ 0 . 0 3 TF = 1.0 s
variables, but taking the calculated air gap flux linkage
of the last calculation step to get the degree of
saturation.
In this paper, the machine transformer is modelled
considering only its stray reactances. For this reason,
the transformer stray reactances are first added to the
stator stray reactances of the synchronous machine. In a
second step, the real flux linkages and terminal
voltages of the generator are calculated.
An IEEE model of a static excitation system (10) is
assumed (see Fig. 4), allowing negative field voltage.
As described in (7), the model of the system to be
studied is adequate for short-term transient studies (up
to some hundred milliseconds time scale). Therefore, in
this work the turbine dynamics are ignored.
Interface method
The choice of the interface between the digital and the
analogue simulator depends on which system is model-
led and which interfacing points are defined. In the
present case, a synchronous generator plus transformer
has to be modelled at the DRTS, the interfacing point is
the HVDC busbar. Since the state equations yield the
stator currents (or transformer currents, respectively),
these currents are fed into the terminals of the ARTS,
see Figure 5. The terminal voltages have to be
measured. Since the rated voltage and current of the
ARTS (parity simu1ator)i are low, i.e. 5 V and 10 mA,
the bandwidth of the voltage controlled current source
is no limiting factor. It should be noted, that with the
,,analogue I/O rack" other interfacing methods (see
Kuffel (8)) can be realized as well, when other com-
I
"I
Analogue
Digital ",
A , Real-Time
Real-Time 3 Simulator:

cy 1 I 1
Simulator:
assumed that the magnetizing current is a non-linear Two-Terminal
function of the air gap flux linkage (which is an Synchronous HVDC
auxiliary variable). In order to avoid arithmetic loops, Generator I 1 System
I Y I I I
the individual linear parts of the magnetizing current
are calculated by using the actual values of the main Figure 5: Interface coilfiguration DRTS/ARTS
 372

ponents of a power system are modelled. Measuring I TABLE 1: Parameters of the SG

currents of the ARTS can be done with standard ARTS
equipment.
s, =300MVA COSq,, =0.85
TA = 8 . 8 s
Before modelling the generator, simpler configurations xa, = 0.109 p.u. ra 0
= 0.003 18 p.u.
such as filters or an a.c. system equivalent were run at
the DRTS to test the interface between DRTS and d-axis q-axis
ARTS. With the available high-speed and high-reso- Xd = 1.150 p.u. xs = 0.858 p.u.
lution D/A and A/D converters very good results were X& = 0.270 p.u.
attained. The parameters of the analogue interface lead
to no limits when running the generator at zero-load X: = 0.165 p.u. xi = 0.169 p.u.
conditions or when applying faults at the HVDC Ti = 2.238s
busbar.
T; =0.026 s T; = 0.033 s
Since the DRTS is working with discrete time steps and
the D/A and A/D conversion including filtering add including a contribution from the generator-
further time delays, a systematic phase error is caused. transformer unit of 1132MVA. The resulting short
With a calculation time step of 50 ps and a nominal circuit power corresponds to a short circuit ratio
frequency fN= 50 Hz, a total time delay of 150 ps or (SCR=SkPm) of 2.5 and an effective short circuit ratio
(pen = 2.7 O was measured. In order to compensate this (ESCR = (Sk-QF)Pm)of 1.9, with QF the power of the
phase error for steady state conditions, the rotor angle reactive compensation equipment. According to (9) the
is subtracted by (pen when transforming the three-phase latter includes two identical filters with 250 Mvar each
stator voltages into dq-coordinates. and a capacitor bank of 125 Mvar. At the inverter side
the benchmark equivalent was used, with the same
4. THE SYSTEM TO BE STUDIED SCR- and ESCR-values as on the rectifier side.

The HVDC benchmark model from the former CIGRE
WG 14.02, Control in HVDC Systems (7), was adopted
for testing the dynamic interaction between the
analogue and digital simulator, the latter being
represented by a synchronous generator with trans-
former, sec Figure 6 and Table 1.
The benchmark system with a high capacitance in the
d.c. circuit is representative of a ca. 100km cable
system. The benchmark parameters had been chosen
such that resonance conditions are created both on the
a.c. side (second harmonic parallel resonance) and on
the d.c. side (fundamental frequency series resonance).

For this purpose, the parameters of the a.c. system equi-
valent of the rectifier side were changed in such a way
that the total short circuit power resulting from the a s .
system equivalent and the generator-transformer unit
based on the generator subtransient reactance was
maintained at the benchmark level of 2500 MVA (7),
For the short-term tests, as presented in the next chap-
ter, the synchronous generator was operated with
constant torque. The generator terminal voltage (V,) is
controlled using an IEEE model of a static excitation
system (10) as shown in Figure 4. For the HVDC
system, digital controls were used, the concept and the

EMF
e'L AC
System
- 745m
345kV, 50Hz
lOO0Mw
230kV, 50Hz

I SCR = 2.5184"
I--- EMF
SCR = 2.5184'1 c
Filters +
ISG- - - - G5L-l Cap. Bank, {I1

,
Digital Real-Time Simulator Analogue Real-Time Simulator
I_ _ _ _ _ _ _ _ _ _ _ I
Figure 6: Extended benchmark system
R = 2.5 R; L = 597 mH; C = 26 pF
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Figure 7: Simulation results for a 5-cycle 3-phase rectifier fault (Legend: see Fig. 8)

parameters being essentially the same as those de- The more difficult case is the fault in the a.c. system of
scribed by Joetten et al (1l). the inverter (Fig. S), since this causes a commutation
failure. After initializing the fault, the rectifier side
5. ]EXPERIMENTALRESULTS busbar voltage fluctuates only slightly, causing a
corresponding fluctuation of the field voltage and
Figwe 7 shows a three-phase solid fault near the recti- current. The generator speed increases faster than in
fier bus, in Figure 8 the fault was applied to the inverter the first case, since in the second case the ax. system
bur;. Due to the saturation of the converter transformers equivalent can temporarily feed active power into the
a voltage and current in the d.c. circuit with fundamen- synchronous generator. The peak d.c. current of the
tal frequency is created. Via the conversion function, a rectifier is limited to 2.0 p.u. by the fast current control.
second harmonic current on the a.c. side is produced. Since no VDCOL is activated at the rectifier side, the
d.c. current is not reduced below 1 p.u. by the control
As expected, the extended benchmark model behaves during the fault.
very similar to the original system without synchronous
generator (1 1). For all cases, system recovery is stable 6. CONCLUSIONS
and smooth, without large a.c. voltage fluctuations.
A new digital real-time simulator (DRTS) has been
During the fault at the rectifier side (Fig. 7), the field presented. The user-friendly graphical interface conse-
current IFDof the generalor has the typical course of a quently supports a hierarchical representation of the
thr1:e-phase short circuit condition. Due to the d.c. model. The simulation model is partitioned automati-
cornponent of the armature current (not shown in the cally, making it possible to calculate complex power
oscillograms), a large 50 Hz component is created in systems in real time. Sophisticated hard- and software
the field current. Since the generator runs with constant allow an on-line visualization and control of the
mechanical torque, the generator speed is increased. simulation process.
The minimal alpha order of the inverter is below 90°,
so the d.c. current is determined by the inverter A flexible high-resolution, high-speed analogue inter-
VCCOL (voltage depe tident current order limit) face connects the DRTl3 to the analogue parity simu-
chalracteristic to ca. 0.5 p.u. About one cycle after lator of FGH, resulting in a high simulation accuracy.
iniliating the fault, the maximum field voltage is This is shown for a co’mbined digital/analogue simu-
reached due to the high gain of the static excitation lation of a point-to-point HVDC transmission system.
system. The generator speed swings with a hunting
frequency of ca. 1.2 Hz.
 ____

37 4

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. .A.. . . . . . . . . . . . ..:...................... c ....................
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1
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Figure 8:
Phase ,,a" voltage at the rectifier commutation bus
Phase ,,a" voltage at the inverter commutation bus
Mid-line d.c. voltage
D.C. current through the d.c. reactor at the recitifier
D.C. current through the d.c. reactor at the inverter
Generator field voltage
Generator field current
Omega Generator speed

7. REFERENCES Gleichstrom-Verbundsystemen", Dissertation, Techni-

1. Joetten R., Wess T., Wolters J. et al., 1985, ,,A
new real-time simulator for power system studies",
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5 . Bonfert K., 1962, ,,Betriebsverhalten der Syn-
chronmaschine", Springer-Verlag, Berlin, Germany
6. Mutschler P., 1975, ,,Berechilung von Ausgleichs-
vorgangen in Drehstromsystemen und Drehstrom-
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,,First benchmark model for HVDC control studies",
ELECTRA, 135,55-73
8. K d e l R., DuchCn H., Wang X. et al., 1995,
,,Expanding an analogue HVDC simulator's modelling
capability using a real-time digital simulator (RTDS)",
First Intemat. Conf. on Digital Power System Simu-
lators, College Station, Texas, USA, 199-204
9. CIGRE WG14.02, 1994, "The CIGRE HVDC
benchniark model - A new prbposal with revised para-
meters, Electra, 157, 61-66
10. IEEE Committee Report, 1981, "Excitation
system models for power system stability studies",
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