Scribd Logo
Upload

Welcome to Scribd!

  • TimersandConditionals Handout

    Uploaded by

    Rhona Liza Cruz
    7 views2 pages
    The document provides guidelines for using timers and conditionals in Visilogic programs. It recommends good practices like adding a system bit for start up, mapping inputs and outputs properly, using comments, and building before downloading. It also outlines how to implement set and reset coils, basic latches, timers, interlock conditionals, on release conditionals, and disable conditionals for timers.

    Original Description:

    Original Title

    TimersandConditionals_Handout

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document provides guidelines for using timers and conditionals in Visilogic programs. It recommends good practices like adding a system bit for start up, mapping inputs and outputs properly, using comments, and building before downloading. It also outlines how to implement set and reset coils, basic latches, timers, interlock conditionals, on release conditionals, and disable conditionals for timers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    7 views2 pages

    TimersandConditionals Handout

    Uploaded by

    Rhona Liza Cruz
    The document provides guidelines for using timers and conditionals in Visilogic programs. It recommends good practices like adding a system bit for start up, mapping inputs and outputs properly, using comments, and building before downloading. It also outlines how to implement set and reset coils, basic latches, timers, interlock conditionals, on release conditionals, and disable conditionals for timers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    UNIVERSITY OF THE PHILIPPINES

    College of Engineering
    Electrical and Electronics Engineering Institute

    TIMERS AND CONDITIONALS


    HANDOUT
    nd
    2 Semester AY 2019-2020

    Good Practices in Visilogic:


    • Add System Bit (SB) 02 – Start up bit because Memory Bits (MB) for the PLC model
    we are using are retentive (i.e. retain values between power ON/OFF cycles)
    • Map all pushbutton inputs and relays output at the start and end nets, respectively.
    • Use comments to explain each net.
    • Use a single rung for every net.
    • Build before downloading.
    • Download with Stop-Download-Reset.
    • Register your Visilogic.

    SET AND RESET COILS


    Basic Latch Implementation through Set and Reset Coil

    Timers
    Conditional Statements Implementations

    Interlock Conditional On Release Conditional

    Disable Conditional for Timers.

    You might also like