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August 2007
FDP8443 tm
®
N-Channel PowerTrench MOSFET
40V, 80A, 3.5mΩ
Features Applications
Typ rDS(on) = 2.7mΩ at VGS = 10V, ID = 80A Automotive Engine Control
UIS Capability (Single Pulse and Repetitive Pulse) Integrated Starter / Alternator
Thermal Characteristics
RθJC o
Thermal Resistance Junction to Case 0.8 C/W
o
RθJA Thermal Resistance Junction to Ambient (Note 2) 62 C/W
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V 40 - - V
VDS = 32V, - - 1
IDSS Zero Gate Voltage Drain Current μA
VGS = 0V TC = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250μA 2 2.8 4 V
ID = 80A, VGS= 10V - 2.7 3.5
rDS(on) Drain to Source On Resistance ID = 80A, VGS= 10V, mΩ
- 4.7 6.1
TJ = 175oC
Dynamic Characteristics
Ciss Input Capacitance - 9310 - pF
VDS = 25V, VGS = 0V,
Coss Output Capacitance - 800 - pF
f = 1MHz
Crss Reverse Transfer Capacitance - 510 - pF
RG Gate Resistance VGS = 0.5V, f = 1MHz - 0.9 - Ω
Qg(TOT) Total Gate Charge at 10V VGS = 0 to 10V - 142 185 nC
Qg(TH) Threshold Gate Charge VGS = 0 to 2V VDD = 20V - 17.5 23 nC
Qgs Gate to Source Gate Charge ID = 35A - 36 - nC
Qgs2 Gate Charge Threshold to Plateau Ig = 1mA - 18.8 - nC
Qgd Gate to Drain “Miller“ Charge - 32 - nC
Notes:
1: Starting TJ = 25oC, L = 0.26mH, IAS = 64A.
2: Pulse width = 100s.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For
a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
1.2 200
CURRENT LIMITED VGS = 10V
POWER DISSIPATION MULIPLIER
BY PACKAGE
1.0 160
40
0.2
0.0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC, CASE TEMPERATURE(oC) TC, CASE TEMPERATURE(oC)
Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs
Temperature Case Temperature
2
1 DUTY CYCLE - DESCENDING ORDER
D = 0.50
NORMALIZED THERMAL
0.20
IMPEDANCE, ZθJC
0.10
PDM
0.1 0.05
0.02
0.01
t1
t2
0.01 NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
1E-3
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t, RECTANGULAR PULSE DURATION(s)
Figure 3. Normalized Maximum Transient Thermal Impedance
5000
VGS = 10V TRANSCONDUCTANCE TC = 25oC
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION ABOVE 25oC DERATE PEAK
1000
IDM, PEAK CURRENT (A)
CURRENT AS FOLLOWS:
I = I2 175 - TC
150
100
SINGLE PULSE
10
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t, RECTANGULAR PULSE DURATION(s)
1000 500
If R = 0
10us tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
STARTING TJ = 25oC
10
LIMITED 10
BY PACKAGE
1ms STARTING TJ = 150oC
1
OPERATION IN THIS SINGLE PULSE 10ms
AREA MAY BE TJ = MAX RATED
LIMITED BY rDS(on) o DC
TC = 25 C
1
0.1 0.01 0.1 1 10 100 1000 5000
1 10 100 tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching
Capability
160 200
PULSE DURATION = 80μs PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX VGS = 10V
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VDD = 5V 160
120
VGS = 5V
TJ = 175oC VGS = 4.5V
120
80
TJ = 25oC 80
TJ = -55oC
40
40
VGS = 4V
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 4 5
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
80 1.8
DRAIN TO SOURCE ON-RESISTANCE
1.6
ON-RESISTANCE (mΩ)
60
TJ = 25oC 1.4
NORMALIZED
o
40 TJ = 175 C 1.2
1.0
20
0.8 ID = 80A
VGS = 10V
0 0.6
3 4 5 6 7 8 9 10 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE(oC)
1.2 1.15
VGS = VDS ID = 1mA
BREAKDOWN VOLTAGE
1.0
NORMALIZED GATE
1.05
0.8
1.00
0.6
0.95
0.4 0.90
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE(oC) TJ, JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
20000 10
VGS, GATE TO SOURCE VOLTAGE(V) ID = 35A
Ciss
10000
8 VDD = 15V
CAPACITANCE (pF)
VDD = 20V
Coss 6 VDD = 25V
1000
4
Crss
f = 1MHz 2
VGS = 0V
100 0
0.1 1 10 50 0 20 40 60 80 100 120 140 160
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC)
Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge vs Gate to Source Voltage
Voltage
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF
FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE
PRODUCTS.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or device, or system whose failure to perform can be
(b) support or sustain life, and (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
Rev. I31