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    i222200 Muhammad Ahmed
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    This document is a laboratory manual for a Digital Logic Design course covering an introductory lab on basic logic gates. The lab manual provides instructions for two tasks: the first task has students implement an XNOR gate using NAND gates, and the second has them implement an XOR gate using NOR gates. It also includes sections for the student to document their name, date, and lab engineer signature to record completion of the tasks using the Proteus simulation software.

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    This document is a laboratory manual for a Digital Logic Design course covering an introductory lab on basic logic gates. The lab manual provides instructions for two tasks: the first task has students implement an XNOR gate using NAND gates, and the second has them implement an XOR gate using NOR gates. It also includes sections for the student to document their name, date, and lab engineer signature to record completion of the tasks using the Proteus simulation software.

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    6 views5 pages

    Digital Logic Design

    Uploaded by

    i222200 Muhammad Ahmed
    This document is a laboratory manual for a Digital Logic Design course covering an introductory lab on basic logic gates. The lab manual provides instructions for two tasks: the first task has students implement an XNOR gate using NAND gates, and the second has them implement an XOR gate using NOR gates. It also includes sections for the student to document their name, date, and lab engineer signature to record completion of the tasks using the Proteus simulation software.

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    © All Rights Reserved
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    Digital Logic Design

    (EL-227)
    LABORATORY MANUAL
    Spring 2024

    (LAB # 2)
    Introduction to Lab Equipment and Basic Gates

    Dr. Aamer Hafeez, Engr. Shehzad Ahmed, Engr. Sana Ehsan

    Student Name: ___Muhammad Ahmed Khan____

    Roll No: __22I-2200___ Section: ____A____

    Date performed: ___29 / 01__, 2024

    Report Submission Date: ___30 / 01___, 2024

    _______________________________

    LAB ENGINEER SIGNATURE & DATE

    NATIONAL UNIVERSITY OF COMPUTER AND EMERGING SCIENCES, ISLAMABAD


    LAB REPORT
    NOR gates as NAND gate:
    NAND gates as NOR gate:
    TASK # 1: Implement XNOR using NAND gates.

    ON PROTEUS:
    TASK # 2: Implement XOR using NOR gates:

    ON PROTEUS:

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