LOGOSOL

Two-Axis Sinusoidal Brushless

Servo Controller With Built-In
Power Amplifiers

LS-221-BL
Technical Reference

Document No 710220125 / Rev. 1.1 - April, 1999

T h e in fo rm a tio n in th is d a ta b o o k h a s b e e n c a re fu lly c h e c k e d a n d is b e lie v e d to b e re lia b le ,
h o w e v e r, n o re s p o n s ib ility c a n b e a s s u m e d fo r in a c c u ra c ie s . A ll in fo rm a tio n in th is m a n u a l is
s u b je c t to c h a n g e w ith o u t n o tic e a n d d o e s n o t re p re s e n t a c o m m itm e n t o n th e p a rt o f th e
v e n d o r.
F le x W a re  is tra d e m a rk o f L o g o s o l, In c .
T ra d e m a rk s a re u s e d th ro u g h o u t th e m a n u a l o n ly a s re fe re n c e to e x is tin g c o m m o n p ro d u c ts . If
a re g is te re d tra d e m a rk is u s e d w ith o u t b e in g in d ic a te d a s s u c h , th is d o e s n o t im p ly th a t th e
n a m e is fre e .
© C o p yrig h t L o g o s o l, In c . 1 9 9 1 - 1 9 9 9 .
A ll rig h ts re s e rv e d . N o p a rt o f th is p u b lic a tio n m a y b e re p ro d u c e d , p h o to c o p ie d , s to re d o n
re trie v a l s ys te m , o r tra n s m itte d w ith o u t th e e x p re s s w ritte n c o n s e n t o f th e p u b lis h e r.

L S -2 2 1 -B L T e c h n ic a l R e fe re n c e
D o c u m e n t N o 7 1 0 2 2 0 1 1 2 5 / R e v . 1 .1 - A p ril, 1 9 9 9

L o g o s o l, In c .
1 1 5 5 T a s m a n D riv e , S u n n yv a le , C A 9 4 0 8 9
T e l: (4 0 8 ) 7 4 4 -0 9 7 4
F a x : (4 0 8 ) 7 4 4 -0 9 7 7
H ttp ://w w w .lo g o s o lin c .c o m
 C o n te n ts
1. OVERVIEW ............................................................................................................................................2
2. REQUIREMENTS...................................................................................................................................4
3. INSTALLATION ......................................................................................................................................5
4. BOARD DESCRIPTION..........................................................................................................................6
4.1. Memory Map ....................................................................................................................................8
4.2. Base Module.....................................................................................................................................8
4.2.1. Servo Channels..........................................................................................................................9
4.2.2. Built-in Power Amplifiers........................................................................................................... 10
4.2.3. Digital Outputs and Outbound Power ........................................................................................ 12
4.2.4. Servo Control and Diagnostic ................................................................................................... 14
4.2.4.1. Motion Processor Reset ...................................................................................................... 14
4.2.4.2. Servo Loop ......................................................................................................................... 14
4.2.4.3. Amplifiers Current Control................................................................................................... 17
4.2.4.4. Interrupt Processing............................................................................................................ 17
4.2.5. Board Identifier ......................................................................................................................... 18
4.2.6. Interface Connectors ................................................................................................................ 18
4.2.6.1. CN3 Connector (External Power) ........................................................................................ 20
4.2.6.2. CN2 Connector (Outputs & Outbound Power) ..................................................................... 21
4.3. Input Board..................................................................................................................................... 22
4.3.1. Digital Optoisolated Inputs........................................................................................................ 24
4.3.1.1. General Purpose Inputs ...................................................................................................... 24
4.3.1.2. Hall-sensor Inputs ............................................................................................................... 26
4.3.1.3. High Speed Position Capture Inputs.................................................................................... 26
4.3.1.4. Emergency Stop Inputs (optional) ....................................................................................... 27
4.3.2. Incremental Encoder Interface.................................................................................................. 27
4.3.3. Multi-turn Absolute Encoder Receiver....................................................................................... 28
4.4. Interface Wiring .............................................................................................................................. 30
4.5. Power Supply ................................................................................................................................. 31
5. BOARD SETUP.................................................................................................................................... 32
5.1. Base I/O Address............................................................................................................................ 32
5.2. Interrupt Line .................................................................................................................................. 32
5.3. Current Limit Mode ......................................................................................................................... 33
5.4. Servo Off Mode .............................................................................................................................. 33
6. APPLICATION NOTES......................................................................................................................... 34
7. BASIC CONTROL PROCEDURES....................................................................................................... 35
7.1. Board identification ......................................................................................................................... 35
7 .2 .B o a rd In itia liz a tio n a n d P o w e r O n ............................................................................................... 36
7.3. Enable Amplifiers ........................................................................................................................... 37
7.4. Disable amplifier............................................................................................................................. 38
7.5. Diagnostic – Finding Out the Reason Caused Amplifier Disable...................................................... 39
 LS-221-BL Technical Reference

1. OVERVIEW
L o g o s o l L S -2 2 1 -B L is a p re c is io n h ig h ly in te g ra te d 2 -a x is d ig ita l s e rv o c o n tro lle r w ith b u ilt-in
p o w e r a m p lifie rs . L S -2 2 1 -B L is s p e c ia lly d e s ig n e d to c o n tro l 3 -p h a s e b ru s h le s s m o to rs w ith
in te g ra te d H a ll-s e n s o rs a n d q u a d ra tu re in c re m e n ta l e n c o d e rs . T h e u n iq u e F le x W a re ™ d e s ig n
a llo w s fle x ib le w irin g a n d a s s ig n m e n t o f a ll in p u ts a n d o u tp u ts to m e e t s p e c ific re q u ire m e n ts .

F E AT UR E S
• 2 -a x is
• M o d u la r d e s ig n
• IS A b u s p lu g -in b o a rd
• D S P te c h n o lo g y. P M D M C 1 2 3 1 A b a s e d
• S in u s o id a l c o m m u ta tio n
• S -c u rv e p ro file
• P ro g ra m m a b le o u tp u t c u rre n t lim it/s h u t d o w n
• Q u a d ra tu re in c re m e n ta l e n c o d e r in te rfa c e (e n c o d e r p o w e r s u p p ly p ro v id e d )
• M u lti-tu rn a b s o lu te p o s itio n e n c o d e r in te rfa c e (p o w e r a n d b a c k u p s u p p ly p ro v id e d )
• A d d itio n a l g e n e ra l p u rp o s e o p to is o la te d in p u ts a n d o u tp u ts
• F le x ib le w irin g
• E m e rg e n c y s to p in p u t

T E C HNIC AL S P E C IF IC AT IO NS
M o tio n C o n tro l
Output
commutation waveform sinusoidal
PWM phases 3 per axis
PWM resolution 10 bit @ 25KHz
min load inductance 200µH
typical motor power supply voltage range 24÷80 VDC
undervoltage shutdown 18 VDC
overvoltage shutdown 100 VDC
max continuous current per channel 8.5A
max short term current per channel (t < 10 sec) 10A
max continuous current per board 16A
programmable current limit for each channel 2-10A
Encoder
type incremental A, B, Z
max pulse frequency 1 MHz
optoisolated encoder inputs 5V/20mA

Hall-sensors
type 120 degrees
optoisolated Hall-sensor inputs 5V/20mA

D ig ita l I/O lin e s

16 general-purpose optoisolated digital inputs 24V/10mA
6 of the inputs may serve as high speed position capture strobes
8 open collector outputs with short circuit protection
max output voltage 48V

2 Doc. #710220125
 LS-221-BL Technical Reference

max current per output 1A

max current per board 5A
3 relay controlled 24 V power supplies
relay type OMRON G6B
max current 5A/30V DC
contact resistance 30mΩ
mechanical contact reliability 20 x 106

P o w e r R e q u ire m e n ts
computer power supply +5V ± 5% / 1A
+12V ± 5% /1A
external operating power 24V DC ± 20%
external motor power 24÷80V DC

3 Doc. #710220125
 LS-221-BL Technical Reference

2. REQUIREMENTS

Logosol LS-221-BL is a plug-in board for a standard ISA bus system. To operate LS-221-BL, the
following requirements must be fulfilled.

• IS A b u s s ys te m .
• O n e fre e 8 -b it o r 1 6 -b it b u s s lo t. L S -2 2 1 -B L its e lf re q u ire s s p a c e fo r tw o s in g le P C -b o a rd s ,
th o u g h o n ly o n e b u s s lo t c o n n e c to r is o c c u p ie d
• A m in im u m o f 5 1 2 K b yte s c o n v e n tio n a l R A M in s ta lle d
• A fre e I/O a d d re s s ra n g e x 2 8 0 ÷x 2 8 F o r x 2 A 0 ÷x 2 A F , w h e re x m a y b e 0 , 1 , 2 , 3
• P o w e r s u p p ly: + 5 V ± 5 % / 1 A , + 1 2 V ± 5 % /1 A
• A n e x te rn a l o p e ra tin g p o w e r: 2 4 V D C ± 2 0 %
• A n e x te rn a l m o to r p o w e r in th e ra n g e : 2 4 ÷8 0 V D C (s e e n o te )

N o te : M o to r p o w e r s u p p ly m u st b e e le c tric a lly is o la te d
fro m c o m p u te r g ro u n d a n d fro m o p e ra tin g p o w e r
s u p p ly (flo a tin g p o w e r s u p p ly).

• A fa n is re q u ire d w h e n d riv in g h ig h p o w e r m o to rs (g re a te r th a n 4 8 V @ 3 A )

4 Doc. #710220125
 LS-221-BL Technical Reference

3. INSTALLATION

Note: LOGOSOL assumes no responsibility for any damage

occurred to your system or your health, due to improper
installation. LS-221-BL is a professional industry application
product and is designed to be operated by electronic engineers
only. Installation of any hardware in your system requires you to
be familiar with the service and maintenance of the personal
computer.
Ask a computer service engineer to assist you if you are
not familiar with electronics.

In sta lla tio n C h e c k list

• D is c o n n e c t th e p o w e r fro m ta rg e t s ys te m . N e v e r to u c h th e e le c tro n ic s w h ile th e p o w e r is

o n . T h is p ro te c ts yo u a n d yo u r e le c tro n ic s .
• T o u c h th e g ro u n d . T o u c h e le c tric a l g ro u n d to e v e n tu a lly u n lo a d yo u r b o d y fro m s ta tic
e le c tric ity.
• S e tu p th e b o a rd . S e le c t th e I/O a d d re s s w ith J 1 ju m p e r b lo c k . O p tio n a lly s e le c t IR Q lin e w ith
J 2 ju m p e r b lo c k . S e tu p S e rv o o ff M o d e (J 4 ) a n d C u rre n t L im it M o d e (J 3 ).
• P lu g in th e m a in p o w e r c o n n e c to r C N 3 . C h e c k p o w e r s u p p ly – m o to r p o w e r (2 4 ÷8 0 V ) a n d
o p e ra tin g p o w e r (2 4 V ). M a k e s u re th e e m e rg e n c y s to p c o n ta c t b e tw e e n p in s 7 & 8 o f C N 3
c o n n e c to r is c lo s e d .
• In s ta ll th e b o a rd . P lu g in L S -2 2 1 -B L in to a fre e b u s s lo t. A n y s lo t m a y b e u s e d .
• S c re w th e B o a rd . F ix L S -2 2 1 -B L w ith a s c re w to th e c h a s s is . N e v e r s w itc h o n th e p o w e r
w ith o u t L S -2 2 1 -B L b e in g fix e d to th e c h a s s is . T h e b o a rd m ig h t h a v e tilte d w ith in th e s lo t a n d
s h o rtc u t th e b u s w ith u n p re d ic ta b le re s u lts .
• T e s t th e in s ta lla tio n . S w itc h o n yo u r s ys te m a n d c h e c k w h e th e r th e b o a rd d o e s n o t in flu e n c e
th e n o rm a l c o m p u te r o p e ra tio n . S w itc h o n th e L S -2 2 1 -B L e x te rn a l p o w e r s u p p ly. R u n th e
a p p lic a tio n s o ftw a re .

5 Doc. #710220125
 LS-221-BL Technical Reference

4. BOARD DESCRIPTION
L o g o s o l L S -2 2 1 -B L is h ig h ly in te g ra te d 2 -a x is d ig ita l s e rv o c o n tro lle r w ith b u ilt-in p o w e r
a m p lifie rs d e s ig n e d to c o n tro l 3 -p h a s e b ru s h le s s m o to rs w ith in te g ra te d H a ll-s e n s o rs a n d
q u a d ra tu re in c re m e n ta l e n c o d e rs . It is in te n d e d fo r h ig h p re c is io n a n d h ig h re lia b ility in d u s tria l
a p p lic a tio n s . T h e b o a rd is d e s ig n e d a s a p lu g -in b o a rd fo r P C /A T c o m p a tib le c o m p u te rs w ith
IS A b u s . T h e u n iq u e F le x W a re ™ d e s ig n a llo w s fle x ib le w irin g a n d p in a s s ig n m e n t to m e e t
s p e c ific re q u ire m e n ts a n d to a c h ie v e c o m p a tib ility w ith a n e x is tin g h a rd w a re . T o a tta in a h ig h
re lia b ility o f o p e ra tio n in in d u s tria l e n v iro n m e n ts , a ll in p u ts a n d o u tp u ts a re o p to is o la te d fro m
th e c o m p u te r g ro u n d . L S -2 2 1 -B L is a n a s s e m b ly o f a m o th e r-b o a rd c a lle d B a s e M o d u le (B M ), a
p lu g -in b o a rd th a t c a rie s a ll in p u t c irc u its - In p u t B o a rd (IB ), a n d In te rfa c e W irin g (IW ) to
c o n n e c t B M a n d IB to L S -2 2 1 -B L fro n t p a n e l c o n n e c to r.

BAS E
M O D U LE

IN T E R FA C E
W IR IN G

IN P U T
BOAR D

L S -22 1 -B L
# 2
# 1 X C 9 5 3 6
X C 9 5 1 0 8 b 3 2 1
b 3 1 9

9729100b

Figure 1: LS-221-BL main components

T o d e liv e r a m a x im u m p e rfo rm a n c e a n d fle x ib ility L S -2 2 1 -B L is d e s ig n e d u s in g th e la te s t

te c h n o lo g ie s . T h e o n b o a rd 2 5 M H z P M D M C 1 2 3 1 A D S P p ro c e s s o r g u a ra n tie s p re c is e a n d
s m o o th m o tio n c o n tro l a n d s a v e s th e h o s t c o m p u te r’s tim e . A ll in p u t, o u tp u t a n d c o n tro l s ig n a ls
6 Doc. #710220125
 LS-221-BL Technical Reference

a re p ro c e s s e d b y IS P (In -S ys te m P ro g ra m m a b le ) c h ip s e t to a llo w fa s t a n d e a s y u s e r-d e fin e d

c u s to m iz a tio n s .
L S -2 2 1 -B L c o n tro lle r is e q u ip p e d w ith v a rio u s h a rd w a re s a fe ty fe a tu re s - e m e rg e n c y s to p
in p u t, o u tp u t o v e rlo a d p ro te c tio n , a m p lifie r o v e rc u rre n t p ro te c tio n , u n d e rv o lta g e a n d s h o rt
c irc u it p ro te c tio n . A d e d ic a te d d ia g n o s tic lo g ic a llo w s to id e n tify th e re a s o n fo r b re a k in g o f th e
s e rv o lo o p (a m p lifie r d is a b le ).

9729105b

Figure 2: LS-221-BL block diagram

7 Doc. #710220125
 LS-221-BL Technical Reference

4.1. Memory Map

L S -2 2 1 -B L is d e s ig n e d a s a s ta n d a rd IS A b u s p e rip h e ra l d e v ic e . T o s a v e I/O s p a c e , L S -2 2 1 -
B L u s e s o n ly 1 6 b yte s fro m th e lo w e s t 1 0 2 4 I/O a d d re s s e s ra n g e . T h e re s t o f L S -2 2 1 -B L
re g is te rs o c c u p y th e s p a c e lo c a te d a t o ffs e t 0 x 4 0 0 , 0 x 8 0 0 a n d 0 x C 0 0 . F o r in s ta n c e , if L S -2 2 1 -
B L b a s e a d d re s s is s e t to 0 x 2 8 0 , th e fo llo w in g I/O a d d re s s a re in u s e – 0 x 2 8 0 ÷0 x 2 8 F ,
0 x 6 8 0 ÷0 x 6 8 F , 0 x A 8 0 ÷0 x A 8 F , 0 x E 8 0 ÷0 x E 8 F . E ig h t b a s e a d d re s s e s a re a v a ila b le , d e p e n d in g o n
J 1 s e ttin g – 0 x 2 8 0 , 0 x 1 2 8 0 , 0 x 2 2 8 0 , 0 x 3 2 8 0 , 0 x 2 A 0 , 0 x 1 2 A 0 , 0 x 2 2 A 0 , 0 x 3 2 A 0 . T h e ta b le b e lo w
s h o w s L S -2 2 1 -B L re g is te r lo c a tio n re la tiv e ly to c o n tro lle r b a s e a d d re s s . T h e o ffs e ts a re in
h e x a d e c im a l.
READ WRITE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0 MC1231A DATA REGISTER 0 MC1231A DATA REGISTER 0
1 READY 1 MC1231A COMMAND REGISTER 1
2 2 2
3 3 3
4 4 4
5 5 5
6 6 6
7 7 7
8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 8 8
9 IN15 IN14 IN13 IN12 IN11 IN10 IN9 IN8 9 9
A AE RST OPT SPS CL1 CL0 A AE RST OPT SPS A
B EMG STP MPF OPF EMGL STPL MPFL OPFL B B
C ADI MPI C ENADI C
D OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 D OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 D
E E PCS3 PCS2 PCS1 PCS0 APERES E
F F F

400 400 400

401 401 401
402 402 402
403 403 403
404 APE D7 APE D6 APE D5 APE D4 APE D3 APE D2 APE D1 APE D0 404 REQ APE#0 404
405 APE D15 APE D14 APE D13 APE D12 APE D11 APE D10 APE D9 APE D8 405 REQ APE#1 405
406 APE D23 APE D22 APE D21 APE D20 APE D19 APE D18 APE D17 APE D16 406 406
407 APE RDY BE OF OS BA PS CE 407 407
408 408 CURRENT LIMIT #0 (0x0 - 0xF) 408
409 409 CURRENT LIMIT #1 (0x0 - 0xF) 409
40A 40A 40A
40B 40B 40B
40C 40C 40C
40D 40D 40D
40E 40E 40E
40F 40F 40F

807 ID3 = 0 ID2 = 0 ID1 = 0 ID0 = 1 807 807

C07 ID7 = 1 ID6 = 0 ID5 = 1 ID4 = 1 C07 C07

Table 1: LS-221-BL Memory Map

4.2. Base Module

T h e m a in p a rt o f L S -2 2 1 -B L s e rv o c o n tro lle r is th e B a s e M o d u le (B M ). It c a rrie s th e m o tio n
c o n tro l p ro c e s s o r, P W M p o w e r a m p lifie rs , o p to is o la te d d ig ita l o u tp u ts , a n d s e rv o c o n tro l a n d
d ia g n o s tic lo g ic . It c a n b e c o m b in e d w ith v a rio u s in p u t b o a rd s to c re a te th e o p tim a l s o lu tio n fo r
w id e ra n g e o f m o tio n c o n tro l ta s k s . T h e fo llo w in g d ia g ra m s h o w s th e la yo u t o f th e B a s e M o d u le .

8 Doc. #710220125
 LS-221-BL Technical Reference

J 1 JU M P E R B L O C K
CN1 (I/O A D D R E S S )
(IN T E R F A C E B O A R D )

J 3 JU M P E R
(C U R R E N T L IM IT M O D E )

P0
P1
(C U R R E N T L IM IT A D J U S T )
T E R M IN A L R M O TO R # 0
J 2 JU M P E R B L O C K
(IN T E R R U P T L IN E )
T E R M IN A L S M O T OR #0

L 1 (M O T O R P O W E R O K )
T E R M IN A L T M O T O R # 0
C N 2 (O U T P U T S A N D
O UTB OUND POW E R)

L 2 (O P E R AT IN G P O W E R O K )

J 4 JU M P E R
(S E R V O O F F M O D E )
T E R M IN A L S M O T OR #1
F1 F U SE
(O P E R AT IN G P O W E R )
T E R M IN A L R M O TO R # 1
C N 3 C O N N E C TO R
(E X T. P O W E R & E M . S T O P )
T E R M IN A L T M O T O R # 1
F2 F U SE
(M O T O R P O W E R )

9729101b

Figure 3: Base Module board layout

B M b o a rd is e q u ip p e d w ith tw o L E D in d ic a to rs fo r fa s t a n d e a s y v is u a l c h e c k o f th e
c o n tro lle r s ta tu s . In o rd e r to c lo s e th e s e rv o lo o p a n d e n a b le th e p o w e r a m p lifie rs b o th L E D
m u s t b e O N . A fte r th e c o n tro lle r is p o w e re d a n d in itia lis e d , L 1 is O N if th e m o to r p o w e r s u p p ly
is p re s e n t a n d if th e re is n o s h o rt c irc u it b e tw e e n a n y m o to r te rm in a l a n d th e c o m p u te r g ro u n d
o r th e g ro u n d o f th e o p e ra tin g p o w e r. L 2 is O N if th e o p e ra tin g p o w e r is p re s e n t a n d n o n e o f th e
d ig ita l o u tp u ts is o v e rlo a d e d .

4.2.1. Servo Channels

L S -2 2 1 -B L im p le m e n ts a la te s t D S P te c h n o lo g y fo r m a x im u m p e rfo rm a n c e a n d p re c is io n . T h e
c o n tro lle r is b a s e d o n P M D M C 1 2 3 1 A D S P m o tio n c o n tro l c h ip s e t. T h is a llo w s L S -2 2 1 -B L to
p e rfo rm a s m o o th a n d p re c is e c o n tro l o f tw o s e rv o a x e s re q u irin g m in im u m re s o u rc e fro m th e
h o s t p ro c e s s o r.
T h e h o s t c o m p u te r s p e c ifie s th e a c c e le ra tio n , m a x im u m v e lo c ity a n d fin a l p o s itio n . A
tra p e z o id a l o r S -c u rv e p ro file m a y b e s e le c te d . M C 1 2 3 1 A u s e s th is in fo rm a tio n to c o n tro l th e
m o v e m e n t b y a c c e le ra tin g a s s p e c ifie d , u n til th e m a x im u m v e lo c ity is re a c h e d o r u n til
d e c e le ra tio n b e g in s to s to p a t th e s p e c ifie d fin a l p o s itio n . T h e d e c e le ra tio n ra te is e q u a l to th e
a c c e le ra tio n ra te . M C 1 2 3 1 A c o n tin u o u s ly k e e p s tra c k o f th e a b s o lu te m o to r p o s itio n u s in g th e
9 Doc. #710220125
 LS-221-BL Technical Reference

e n c o d e r fe e d b a c k s ig n a l. T h e e n c o d e r d e liv e rs tw o 9 0 0 p h a s e s h ifte d s ig n a ls to d e te rm in e th e
s p e e d a n d d ire c tio n o f th e m o to r's m o tio n . A t a n y tim e d u rin g th e m o v e , th e m a x im u m v e lo c ity
a n d /o r th e ta rg e t p o s itio n m a y b e c h a n g e d , a n d th e m o to r w ill a c c e le ra te o r d e c e le ra te
a c c o rd in g ly. A ll tra je c to ry p a ra m e te rs a re 3 2 -b it v a lu e s .
D u rin g th e m o tio n , o n e v e ry s a m p lin g in te rv a l, M C 1 2 3 1 A s u b tra c ts th e a c tu a l p o s itio n (fe e d
b a c k p o s itio n ) fro m th e d e s ire d o n e (p ro file g e n e ra to r p o s itio n ). T h e re s u ltin g p o s itio n e rro r is
p ro c e s s e d b y d ig ita l filte r to p ro d u c e a m o to r c o n tro l c o m m a n d . M C 1 2 3 1 A u s e s a
p ro g ra m m a b le d ig ita l P ro p o rtio n a l In te g ra l D e riv a tiv e (P ID ) filte r to c o m p e n s a te th e c o n tro l
lo o p . T h e m o to r is h e ld a t th e d e s ire d p o s itio n b y a p p lyin g a re s to rin g fo rc e th a t is p ro p o rtio n a l
to th e p o s itio n e rro r, p lu s th e in te g ra l o f th e e rro r, p lu s th e d e riv a tiv e o f th e e rro r. A ll P ID filte r
c o e ffic ie n ts a re 1 6 -b it v a lu e s .
In a d d itio n to tra je c to ry g e n e ra tio n a n d s e rv o lo o p c lo s u re th e M C 1 2 3 1 A c h ip s e t p ro v id e s
s in u s o id a l c o m m u ta tio n fo r 3 -p h a s e b ru s h le s s m o to rs . T h e c o m m u ta tio n p o rtio n o f th e c h ip s e t
u s e s a s in p u t th e m o to r c o m m a n d s ig n a l fro m s e rv o lo o p filte r. T h is p re -c o m m u ta te d c o m m a n d
is th e n m u ltip lie d b y c o m m u ta tio n v a lu e s d e riv e d fro m a n in te rn a l lo o k u p S in /C o s ta b le . T h e
c o m m u ta tio n a n g le u s e d in th e S in /C o s ta b le is d e te rm in e d b y th e p o s itio n e n c o d e r a s w e ll a s
p a ra m e te rs s e t b y th e h o s t w h ic h re la te th e s p e c ific e n c o d e r u s e d to th e m o to r m a g n e tic p o le s .
T h e e n c o d e r in d e x p u ls e is u s e d to m a in ta in c o m m u ta tio n s yn c h ro n iz a tio n .
A n o th e r fe a tu re is th e a b ility to u s e H a ll-s e n s o rs fo r p h a s e in itia liz a tio n . T h re e H a ll-s e n s o rs
in itia lly d e te rm in e th e m o to r p h a s in g a n d s in u s o id a l c o m m u ta tio n b e g in s a u to m a tic a lly. T h e
in itia liz a tio n o c c u rs w ith o u t a n y m o to r m o tio n . F o r m o to rs n o t s u p p lie d w ith H a ll-s e n s o rs , a
s p e c ia l a lg o rith m ic p h a s e -in itia liz a tio n p ro c e d u re is a v a ila b le . D u rin g th e a lg o rith m ic
in itia liz a tio n th e m o to r m a y m o v e s u d d e n ly in a n y d ire c tio n . P ro p e r s a fe ty p re c a u tio n s h o u ld b e
ta k e n to p re v e n t d a m a g e fro m th is m o v e m e n t.
F o r p ro g ra m m in g in fo rm a tio n s e e th e P M D M C 1 2 3 1 A c h ip s e t m a n u a l. T h e fo llo w in g ta b le
s h o w s m e m o ry lo c a tio n o f th e M C 1 2 3 1 A re g is te rs :

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0 R/W MC1231A DATA REGISTER
Base Addr + 1 Write MC1231A COMMAND REGISTER
Base Addr + 1 Read READY
Table 2: MC1231A register location

4.2.2. Built-in Power Amplifiers

E a c h L S -2 2 1 -B L s e rv o c h a n n e l is e q u ip p e d w ith a b u ilt-in p o w e r a m p lifie r, c a p a b le to
d e liv e r u p to 1 0 A . T h e a m p lifie rs a re d e s ig n e d a s th re e h a lf H -b rid g e s w ith F E T tra n s is to rs
(IR F 9 5 4 0 a n d IR C 5 3 0 ). T o a c h ie v e a h ig h n o is e im m u n ity a n d re lia b ility, th e p o w e r c irc u its a re
o p to is o la te d fro m th e c o m p u te r g ro u n d .

10 Doc. #710220125
 LS-221-BL Technical Reference

M OTO R PO W E R
(F L O AT IN G )

+5V C H A N N E L #0 P O W E R A M P L IF IE R

IS O L AT E D F R O M
CO MP UTER G ROUND

M O T O R # 0 T E R M IN A L R

H C P L 2 6 31
+5V

M O T O R # 0 T E R M IN A L S

H C P L 2 6 31
+5V
F R O M M O T IO N P R O C E S S O R

P W M P R O C E S S IN G

M O T O R # 0 T E R M IN A L T
PWM

H C P L 2 6 31 OVERCURRENT
S EN S E

C H A N N E L #1 P O W E R A M P L IF IE R
M O T O R # 1 T E R M IN A L S

A M P L IF IE R E N A B L E
H O ST P R O C ES S OR

S ER V O C O N TR OL
AND
D IA G N O S T IC M O T O R P O W E R FA IL U R E
S TAT U S
TO

O P E R AT IN G P O W E R /O U T P U T FA IL U R E
E M E R G E N C Y S T O P IN P U T
S T O P IN P U T S

+12V
CO M PUTER +5V
POW ER
S U P P LY E N C O D E R P O W E R (+9 V )
+12V LM 317

9729200b

Figure 4: Build-in power amplifiers

P W M s ig n a ls g e n e ra te d b y P M D M o tio n P ro c e s s o r a re fo rm e d b y s p e c ia l c irc u it to m e e t th e
p o w e r b rid g e s re q u ire m e n ts . T h e a m p lifie r e n a b le (A E ) is c o n tro lle d b y s e rv o c o n tro l a n d
d ia g n o s tic lo g ic . T h e a m p lifie rs a re im m e d ia te ly s h u t d o w n in c a s e o f e m e rg e n c y - p o w e r
fa ilu re , e x c e s s c u rre n t o r o u tp u t o v e rlo a d , e m e rg e n c y s to p . T h e re a s o n c a u s e d a m p lifie rs to
d is a b le is la tc h e d in s p e c ia l re g is te r a n d is a v a ila b le to th e h o s t fo r d ia g n o s tic p u rp o s e . If th e
a m p lifie rs a re d is a b le d w h ile th e m o to rs ru n , th e y c a n s to p in o n e o f tw o w a ys d e p e n d in g o n J 4
ju m p e r s e ttin g . W ith J 4 in s ta lle d , th e m o to rs h a v e th e ir w in d in g s s h o rte n , w h ic h m e a n s fa s te r
s to p , to p re v e n t e v e n tu a lly m a c h in e d ro p p in g . W ith J 4 o p e n , th e m o to rs h a v e th e ir w in d in g s
o p e n , w h ic h c a u s e s m a c h in e to s to p s m o o th ly. If th e m o to rs h a v e b re a k s a s s o c ia te d w ith th e m ,
th e y c a n b e a c tiv a te d a u to m a tic a lly im m e d ia te ly a fte r th e a m p lifie rs a re d is a b le d .

11 Doc. #710220125
 LS-221-BL Technical Reference

T h e o u tp u t c u rre n t fro m e a c h h a lf H -b rid g e is c o n tin u o u s ly m o n ito re d b y a p ro te c tio n lo g ic

a n d m a y b e lim ite d to a v a lu e a d ju s ta b le in th e ra n g e o f 2 ÷1 0 A . T h e lim it fo r e a c h a x is c a n b e
p ro g ra m m e d in d iv id u a lly u s in g a s p e c ia l re g is te r. T h e ra n g e 2 ÷1 0 A is d iv id e d in to 1 6 s te p s . A
trim m e r-p o t (P 0 , P 1 ) is u s e d fo r p re c is e a d ju s tm e n t o f th e s e le c te d lim it. If th e a m p lifie r o u tp u t
is o v e rlo a d e d o r e v e n s h o rte d fo r a m o m e n t, th e b rid g e o u tp u t c u rre n t is lim ite d to th e
p ro g ra m m e d v a lu e . T h e p ro te c tio n h a s tw o m o d e s d e p e n d in g o n J 3 ju m p e r s e ttin g . W ith J 3
ju m p e r in s ta lle d , if th e o v e rlo a d in g ta k e s p la c e m o re th a n 1 0 0 m s , th e s e rv o lo o p w ill b e s h u t
d o w n a u to m a tic a lly a n d th e P W M p o w e r a m p lifie rs w ill b e d is a b le d . If J 3 is le ft o p e n , th e s e rv o
lo o p w ill re m a in c lo s e d re g a rd le s s o f th e o v e rlo a d d u ra tio n . T h e o u tp u t c u rre n t is lim ite d to th e
s p e c ifie d v a lu e .
S e e 4 .2 .4 .3 fo r m o re in fo rm a tio n o n c u rre n t lim it.

4.2.3. Digital Outputs and Outbound Power

B e in g a fu lly in te g ra te d s e rv o c o n tro lle r, a lo n g w ith th e s e rv o c h a n n e ls , L S -2 2 1 -B L o ffe rs 8
g e n e ra l p u rp o s e d ig ita l o u tp u ts e q u ip p e d w ith h ig h v o lta g e , h ig h c u rre n t F E T tra n s is to rs a n d
th re e re la y c o n tro lle d p o w e r s o u rc e s . T h e p o w e r s o u rc e s a re n a m e d b a s e d o n th e ir typ ic a l
a p p lic a tio n . S P S (S ys te m P o w e r S u p p ly) is u s e d b a s ic a lly to p o w e r s e n s o rs . It is a v a ila b le
im m e d ia te ly a fte r th e c o n tro lle r is p o w e re d a n d in itia lis e d . Y o u c a n n o t tu rn o ff th is p o w e r
w ith o u t d is a b lin g th e s e rv o lo o p a n d th e d ig ita l o u tp u ts a s w e ll. O P T (O P T io n a l p o w e r s u p p ly)
is g e n e ra l-p u rp o s e p o w e r s o u rc e a n d m a y b e c o n tro lle d in d iv id u a lly. S P S m u s t b e O N to e n a b le
O P T . O P S (O u tp u t P o w e r S u p p ly) is u s e d b a s ic a lly to p o w e r m o to r b re a k s a n d v a rio u s v a lv e s
a n d s w itc h e s . O P S c a n n o t b e c o n tro lle d s e p a ra te ly. It d e p e n d s o n a m p lifie r e n a b le s ta tu s a n d
S P S o n ly. If th e p o w e r a m p lifie rs a re e n a b le d , th e O P S is p re s e n t a n d if th e a m p lifie rs a re
d is a b le d , th e O P S is O F F . T h is is u s e fu l fo r d e v ic e s th a t s h o u ld b e s h u t o ff a u to m a tic a lly w h e n
th e a m p lifie rs a re d is a b le d , fo r in s ta n c e m o to r b re a k s o r o th e r e m e rg e n c y c irc u its .

12 Doc. #710220125
 LS-221-BL Technical Reference

9729901

Figure 5: Digital outputs and outbound power sources

T h e o u tp u ts a re o p e n c o lle c to r tra n s is to rs c o n n e c te d to th e g ro u n d o f th e o p e ra tin g v o lta g e .
T h e y a re o p to is o la te d fro m th e c o m p u te r g ro u n d . A ll o u tp u ts a re s h o rt-c irc u it p ro te c te d . If o n e
o f th e m is o v e rlo a d e d , th e p ro te c tio n c irc u it w ill s h u t d o w n a ll tra n s is to r o u tp u ts . O P T a n d S P S
re la ys w ill n o t b e a ffe c te d . T h e s e rv o lo o p w ill b e tu rn e d o ff a u to m a tic a lly (a m p lifie r d is a b le )
a n d th is w ill tu rn o ff O P S a s w e ll. O n c e a c tiv a te d , th e p ro te c tio n k e e p s o u tp u ts d is a b le d u n til
th e re a s o n th a t c a u s e d th e o v e rlo a d in g is p re s e n t. T h e o u tp u ts a re c o n tro lle d th ro u g h th e
a s s o c ia te d re g is te rs .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xA R/W AE RST OPT SPS CL1 CL0
Base Addr + 0xD R/W OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
Table 3: Digital outputs and outbound power registers
To activate an output or a power source, logic one must be written to the corresponding control bit.
Activating the emergency stop will turn off SPS and will disable all other power sources and outputs. For
safety reasons, to prevent an accidental turn on after an emergency, SPS is equipped with a
special double buffered logic. In order to restore SPS after being shut off by emergency stop,
SPS must be cycled off-on. SPS control bit should be first reset to logic zero and after that set to
logic one.

13 Doc. #710220125
 LS-221-BL Technical Reference

4.2.4. Servo Control and Diagnostic

T h e s e rv o c o n tro l a n d d ia g n o s tic lo g ic a llo w s th e h o s t to s e t u p th e c o n tro lle r a n d to k e e p
tra c k o f th e c u rre n t L S -2 2 1 -B L s ta tu s .

4.2.4.1. Motion Processor Reset

A fte r h a rd w a re re s e t o r a fte r s ys te m p o w e r u p , M C 1 2 3 1 A c h ip s e t is re s e t. T o re m o v e th e
s e rv o c h ip re s e t, lo g ic z e ro s h o u ld b e w ritte n to th e c o rre s p o n d in g R S T b it. W ritin g lo g ic o n e to
th e s a m e b it w ill p u t M C 1 2 3 1 A in re s e t c o n d itio n .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xA R/W AE RST OPT SPS CL1 CL0
Table 4: MC1231A reset control

4.2.4.2. Servo Loop

D u rin g n o rm a l o p e ra tio n , th e L S -2 2 1 -B L s e rv o lo o p m u s t b e c lo s e d . W ith s e rv o lo o p c lo s e d ,
th e c o n tro lle r c o n s ta n tly re a d s th e c u rre n t m o to r p o s itio n fro m th e e n c o d e r a n d a p p lie s th e
n e c e s s a ry v o lta g e to th e m o to r to k e e p th e d e s ire d tra je c to ry o r p o s itio n . In c a s e o f e m e rg e n c y
th is lo o p m u s t b e b ro k e n (i.e . th e p o w e r a m p lifie r m u s t b e d is a b le d ) to p ro te c t th e c o n tro lle d
o b je c t a n d /o r th e c o n tro lle r. W ith s e rv o lo o p o p e n , th e c o n tro lle r c o n tin u e s to k e e p tra c k o f th e
m o to r p o s itio n b u t d o e s n ’t a p p ly a n y v o lta g e to th e m o to r. L S -2 2 1 -B L s e rv o lo o p is c o n tro lle d b y
A E (A m p lifie r E n a b le ) s ig n a l.

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xA R/W AE RST OPT SPS CL1 CL0
Table 5: Amplifier Enable control
T o s e t A E s ig n a l a lo g ic o n e s h o u ld b e w ritte n to th e c o rre s p o n d in g c o n tro l b it. A E m a y b e
re s e t e ith e r b y w ritin g lo g ic z e ro to th e s a m e b it, o r a u to m a tic a lly b y s e rv o o ff c o n d itio n
g e n e ra te d b y L S -2 2 1 -B L p ro te c tio n c irc u its . F o r sa fe ty re a so n s, AE is e q u ip p e d w ith th e
sa m e d o u b le b u ffe re d lo g ic a s S P S to p re ve n t a n a c c id e n ta l tu rn o n a fte r a n
e m e rg e n c y sh u t d o w n . T o re sto re AE a fte r a n e m e rg e n c y, first a lo g ic ze ro m u st b e
w ritte n to AE c o n tro l b it. A su b se q u e n t w ritin g o f lo g ic o n e to AE c o n tro l b it w ill
c lo se th e se rvo lo o p a g a in a n d w ill e n a b le th e a m p lifie rs.

14 Doc. #710220125
 LS-221-BL Technical Reference

9729302b

Figure 6: Servo control and diagnostic

T h e re a re s e v e ra l s o u rc e s th a t c a n c a u s e s e rv o lo o p to b re a k .

•M o to r P o w e r F a ilu re (M P F )
T o p o w e r th e m o to rs , L S -2 2 1 -B L re q u ire s s e p a ra te p o w e r s u p p ly is o la te d fro m th e
c o m p u te r g ro u n d a n d fro m th e o p e ra tin g (2 4 V ) p o w e r s u p p ly a s w e ll. If M o to r P o w e r is
b e lo w th e u n d e rv o lta g e lim it o r a b o v e th e o v e rv o lta g e lim it, M P F is s e t to lo g ic o n e a n d
A E is a u to m a tic a lly d is a b le d . M P F is a ls o s e t to lo g ic o n e in c a s e o f le a k a g e b e tw e e n
h ig h v o lta g e m o to r c irc u its a n d a n y o f lo w v o lta g e c o m p u te r o r 2 4 V c irc u its . A c u rre n t a s
lo w a s 0 .5 m A w ill trig g e r th e p ro te c tio n . T h e c u rre n t M P F v a lu e is la tc h e d a s M P F L a t
th e m o m e n t th e s e rv o lo o p is b ro k e n .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xB Read EMG STP MPF OPF EMGL STPL MPFL OPFL
Table 6: MPF status

•O u tp u t O ve rlo a d / O p e ra tin g P o w e r F a ilu re (O P F )

T h e o p e ra tin g p o w e r re q u ire d fo r th e O u tp u ts a n d O u tb o u n d P o w e r S o u rc e s m u s t b e
2 4 V ±2 0 % . If it is o u t o f ra n g e , th e O P F is s e t to lo g ic o n e a n d A E is a u to m a tic a lly

15 Doc. #710220125
 LS-221-BL Technical Reference

d is a b le d . A ll d ig ita l o u tp u ts a re s h o rt c irc u it p ro te c te d . If a n y o f th e m is o v e rlo a d e d , a ll

o u tp u ts a re d is a b le d a n d O P F is s e t to lo g ic o n e . T o d is tin g u is h b e tw e e n th e tw o
re a s o n s , O P F s h o u ld b e c h e c k e d w ith a ll o u tp u ts re s e t. In th is c a s e o n ly m is s in g o r o u t
o f ra n g e o p e ra tin g p o w e r c a n a c tiv a te O P F . T h e c u rre n t O P F v a lu e is la tc h e d a s O P F L
a t th e m o m e n t th e s e rv o lo o p is b ro k e n .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xB Read EMG STP MPF OPF EMGL STPL MPFL OPFL
Table 7: OPF status

•E m e rg e n c y S to p In p u t (E M G )
L S -2 2 1 -B L is e q u ip p e d w ith e m e rg e n c y s to p in p u t. T o o p e ra te L S -2 2 1 -B L , a n o rm a lly
c lo s e d c o n ta c t m u s t b e c o n n e c te d to th a t in p u t. O p e n in g th e c o n ta c t w ill im m e d ia te ly
d is a b le th e a m p lifie rs a n d a ll o u tp u ts a n d w ill s h u t o ff th e o u tb o u n d p o w e r s o u rc e s . If th e
e m e rg e n c y s to p is a c tiv a te d , E M G is s e t to lo g ic o n e , o th e rw is e is re s e t to lo g ic z e ro .
E M G is c o n tin u o u s ly a v a ila b le to th e h o s t a n d th e c u rre n t E M G v a lu e is la tc h e d a s
E M G L a t th e m o m e n t th e s e rv o lo o p is b ro k e n .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xB Read EMG STP MPF OPF EMGL STPL MPFL OPFL
Table 8: EMG status

•S to p In p u ts (S T P ) (o p tio n a l)
S o m e o f th e g e n e ra l p u rp o s e in p u ts o r a s e le c te d c o m b in a tio n o f th e m c a n b e u s e d a s
a n a d d itio n a l e m e rg e n c y s to p . T h is is a c u s to m o p tio n a n d m a y b e in s ta lle d b y u s e r
re q u e s t. B y d e fa u lt it is n o t u s e d . W h e n th e o p tio n is in s ta lle d a n d s to p in p u t is a c tiv a te d ,
S T P is s e t to lo g ic o n e . U n d e r n o rm a l c o n d itio n s S T P is lo g ic z e ro . S T P is c o n tin u o u s ly
a v a ila b le to th e h o s t a n d th e c u rre n t S T P v a lu e is la tc h e d a s S T P L a t th e m o m e n t th e
s e rv o lo o p is b ro k e n .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xB Read EMG STP MPF OPF EMGL STPL MPFL OPFL
Table 9: STP status

•C u rre n t L im it (C L )
W h e n o n e o r m o re o f th e p o w e r a m p lifie rs re a c h th e p ro g ra m m e d c u rre n t lim it th e
c o rre s p o n d in g C L s ig n a l is s e t to lo g ic o n e . O th e rw is e C L is lo g ic z e ro . C L 0 , C L 1
re p re s e n t th e c u rre n t o v e rlo a d re s p e c tiv e ly fo r c h a n n e l 0 , 1 . W h ile th e s e rv o lo o p is
c lo s e d (i.e . A E = 1 ), C L 0 a n d C L 1 s h o w th e a c tu a l s ta te s o f th e c u rre n t lim ita tio n fo r th e
c o rre s p o n d in g c h a n n e ls . If th e s e rv o lo o p is b ro k e n (i.e . A E = 0 ), C L 0 a n d C L 1 k e e p th e
C L v a lu e s fro m th e m o m e n t th e s e rv o w a s s h u t d o w n . B y re a d in g th e re g is te r th e h o s t
c a n d e te rm in e o v e rlo a d in g o f w h ic h c h a n n e l h a d c a u s e d th e p ro b le m .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xA Read AE RST OPT SPS CL1 CL0
Table 10: CL status

16 Doc. #710220125
 LS-221-BL Technical Reference

4.2.4.3. Amplifiers Current Control

The output of each amplifier is protected against short circuit or overload. The current delivered to
the load is constantly monitored and compared to a limit that can be set individually for each axis. The
current may be limited to a value in the range of 2÷10 A with 4-bit precision. Only the four MSB are used.
Writing 0x00 to the corresponding register sets the current limit to the lowest level (less than 1A). Writing
0xF0 sets the current limit to the highest level - 10A.

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0x408 Write CURRENT LIMIT #0 (0 ÷ 0xF)
Base Addr + 0x409 Write CURRENT LIMIT #1 (0 ÷ 0xF)
Table 11: Current limit registers
If J 3 ju m p e r is in s ta lle d , e a c h tim e a c h a n n e l re a c h e s th e c u rre n t lim it, th e c o rre s p o n d in g
C L s ig n a l is s e t to lo g ic o n e . T h e C L s ig n a ls a re c o n tin u o u s ly a v a ila b le to th e h o s t fo r d ia g n o s tic
p u rp o s e o r fo r a re a l tim e c o n tro l. If th e o v e rlo a d in g ta k e s p la c e fo r m o re th a n 1 0 0 m s , th e
s e rv o lo o p w ill b e s h u t d o w n a u to m a tic a lly a n d th e P W M p o w e r a m p lifie rs w ill b e d is a b le d .
S p e c ia l re g is te r la tc h e s c u rre n t C L v a lu e s a t th e m o m e n t th e s e rv o lo o p is b ro k e n . B y re a d in g
th e re g is te r th e h o s t c a n d e te rm in e w h ic h c h a n n e l h a d c a u s e d s e rv o o ff.
If J 3 is le ft o p e n , C L s ig n a ls a re fo rc e d to lo g ic z e ro . T h e s e rv o lo o p w ill re m a in c lo s e d
re g a rd le s s o f th e o v e rlo a d d u ra tio n . T h e o u tp u t c u rre n t is lim ite d to th e s p e c ifie d v a lu e .

4.2.4.4. Interrupt Processing

R e a d in g L S -2 2 1 -B L In te rru p t S ta tu s re g is te r re tu rn s lo g ic o n e fo r e a c h e v e n t th a t c u rre n tly
h a v e re q u e s te d in te rru p t. W ritin g lo g ic z e ro to th e In te rru p t M a s k re g is te r a llo w s e a c h e v e n t to
b e in d iv id u a lly m a s k e d o ff. B y d e fa u lt a fte r p o w e r u p , In te rru p t M a s k re g is te r is c le a re d a n d n o
in te rru p ts a re e n a b le d (e x c e p t th e IR Q fro m M C 1 2 3 1 A , s e e 4 .2 .5 .2 .)
L S -2 2 1 -B L h a s tw o s o u rc e s th a t c a n g e n e ra te in te rru p t re q u e s t (IR Q ) to th e h o s t a s fo llo w s :

ADI - Amplifier Disable Interrupt

L S -2 2 1 -B L is c a p a b le to g e n e ra te in te rru p t re q u e s t, e a c h tim e th e a m p lifie rs a re d is a b le d . It
d o e s n ’t m a tte r if th e a m p lifie rs a re d is a b le d b y a n y o f th e p ro te c tio n c irc u its o r b y th e s o ftw a re .
S e ttin g th e In te rru p t M a s k e n a b le s o r d is a b le s A D I.
E N A D I = 1 , A D I e n a b le d
E N A D I = 0 , A D I d is a b le d

MPI – Motion Processor Interrupt

M C 1 2 3 1 A m o tio n p ro c e s s o r c a n g e n e ra te IR Q d u e to v a rio u s e v e n ts . S e e M C 1 2 3 1 A m a n u a l
fo r in fo rm a tio n h o w to c o n tro l in te rru p t re q u e s ts .
If M C 1 2 3 1 A in te rru p t is e n a b le d a n d a c tiv a te d , M P I fla g in th e L S -2 2 1 -B L In te rru p t S ta tu s
re g is te r is s e t to lo g ic o n e . M P I is ju s t a fla g a n d c a n n o t b e m a s k e d o ff u s in g L S -2 2 1 -B L
In te rru p t M a s k re g is te r. M C 1 2 3 1 A c o n tro l re g is te r s h o u ld b e u s e d to h a n d le th is in te rru p t.

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xC Read ADI MPI
Base Addr + 0xC Write EN ADI
Table 12: IRQ Status and Mask registers
J 2 ju m p e r b lo c k s e le c ts in te rru p t lin e to th e h o s t. IR Q 7 , IR Q 1 0 , IR Q 1 2 , IR Q 1 5 m a y b e u s e d .

17 Doc. #710220125
 LS-221-BL Technical Reference

4.2.5. Board Identifier

D u e to its fle x ib le a rc h ite c tu re a n d IS P (In S ys te m P ro g ra m m a b le ) c a p a b ility, L S -2 2 1 -B L
a llo w s fa s t a n d e a s y c u s to m iz a tio n s . T o p ro v id e in fo rm a tio n fo r th e c u rre n t c o n tro lle r
c o n fig u ra tio n , L S -2 2 1 -B L fe a tu re s a n 8 -b it ID n u m b e r. T w o fo u r-b it re a d -o n ly re g is te rs fo rm th e
c o n tro lle r ID .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0x807 Read ID3 ID2 ID1 ID0
Base Addr + 0xC07 Read ID7 ID6 ID5 ID4
Table 13: ID registers

B a se ad d ress+ 0 x 8 0 7 = X X X X D D D D

B a se ad d ress+ 0 x C 0 7 = X X X X D D D D

B a se M o d u le ID = D D D D D D D D
F ig u re 7 : ID n u m b e r

T h e ID fo r th e s ta n d a rd L S -2 2 1 -B L c o n fig u ra tio n is 0 x B 3 .

4.2.6. Interface Connectors

T h e B a s e M o d u le c a rrie s tw o in te rfa c e c o n n e c to rs a v a ila b le to th e u s e r. C N 3 is th e e n try fo r
th e e x te rn a l m o to r a n d o p e ra tin g p o w e r s u p p lie s . T h e e m e rg e n c y s to p in p u t is a ls o lo c a te d
h e re . A ll d ig ita l o u tp u ts a n d o u tb o u n d p o w e r s o u rc e s a re w ire d to C N 2 c o n n e c to r. A b lo c k
d ia g ra m o f C N 2 to g e th e r w ith C N 3 is s h o w n b e lo w .

18 Doc. #710220125
 H -B R ID G E S H -B R ID G E S

M C1231A
M O T IO N P R O C E S S O R

T R S T S R
M O T #1 M O T #0

C N 2 C ON N EC TO R
SHORT
C IR C U IT
S EN S O R

19
OU T7
OU T6
OU T5
OU T4
OU T3
OU T2
OU T1
OU T0

S PS OPS

OU TPU T
OVERLOAD

FUS E

FUS E
S EN S O R
OPT
FRO M
P R O T E C T IO N
L O G IC AE

OU TPU TS A N D O U TB OU N D P OW E R

Figure 8: Block Diagram of CN2 & CN3 connectors

C O N T R O L R E G IS T E R S
C N 3 C ON N EC TO R

M OTO R
P OW ER
O P E R AT IN G
P O W E R (2 4 V )
E M ER G EN C Y S TOP

9 72 91 0 2b

Doc. #710220125
LS-221-BL Technical Reference
 LS-221-BL Technical Reference

4.2.6.1. CN3 Connector (External Power)

8
E M ER G EN C Y S TOP
7
6 O P E R AT IN G P O W E R G R O U N D ( )
5 O P E R AT IN G P O W E R (+ 2 4 V )
4
3
2
1
} M OTO R PO W E R

9729103b

Figure 9: CN3 connector location and pinout

20 Doc. #710220125
 LS-221-BL Technical Reference

4.2.6.2. CN2 Connector (Outputs & Outbound Power)

14 - OUT 0
13 - OUT 1
12 - OUT 2
11 - O U T 3
10 - OUT 4
9 - OUT5
8 - OUT6
7 - OUT7
6 - + 24 V O P S
5 - + 24 V O P T
4 - + 24 V S P S
3 - + 24 V O P E R AT IN G P O W E R (F U S E )
2 - E ME R G EN C Y S TOP
1 - O P E R AT IN G P O W E R G R O U N D

9 72 91 0 4b

Figure 10: CN2 connector location pinout

21 Doc. #710220125
 LS-221-BL Technical Reference

4.3. Input Board

L S -2 2 1 -B L is d e s ig n e d a s m u ltip u rp o s e m o tio n c o n tro lle r. T o in c re a s e c o n tro lle r fle x ib ility, a ll
in p u t c irc u its a re lo c a te d o n a s e p a ra te b o a rd - in p u t b o a rd (IB ). A fla t rib b o n c a b le c o n n e c ts IB
to th e c o n tro lle r’s in te rfa c e c o n n e c to r, m o u n te d o n th e fro n t p a n e l.

T h e fro n t p a n e l c o n n e c to r a n d th e in p u t b o a rd m a y b e o rd e re d in
d iffe re n t c u s to m d e s ig n e d c o n fig u ra tio n s fo r s p e c ific a p p lic a tio n s .

T h e s ta n d a rd L S -2 2 1 -B L in p u t b o a rd is L S -4 2 1 -2 1 1 2 .

9737100

Figure 11: LS-421-2112 input board layout

L S -4 2 1 -2 1 1 2 fe a tu re s :
• 1 6 g e n e ra l p u rp o s e d ig ita l o p to is o la te d in p u ts
• 6 o p to is o la te d in p u ts fo r H a ll-s e n s o rs
• O p to is o la te d in te rfa c e a n d p o w e r s u p p ly fo r 2 in c re m e n ta l e n c o d e rs
• 2 -c h a n n e l o p to is o la te d re c e iv e r fo r 2 m u lti-tu rn a b s o lu te p o s itio n e n c o d e rs , p o w e r
s u p p ly a n d b a c k u p b a tte ry.

A ll in p u t lin e s a n d e n c o d e r s ig n a ls a re p ro c e s s e d b y IS P (In S ys te m P ro g ra m m a b le ) lo g ic
d e v ic e fo r m a x im u m fle x ib ility.

22 Doc. #710220125
 LS-221-BL Technical Reference

9737904b

Figure 12: LS-421-2112 Input Board block diagram

23 Doc. #710220125
 LS-221-BL Technical Reference

4.3.1. Digital Optoisolated Inputs

A ll 1 6 in p u ts IN 0 ÷IN 1 5 m a y b e u s e d a s g e n e ra l-p u rp o s e in p u ts , a lth o u g h s o m e o f th e m m a y
h a v e a d d itio n a l fu n c tio n s . S ix m a y s e rv e a s s tro b e s fo r h ig h s p e e d p o s itio n c a p tu rin g . A P E 0
a n d A P E 1 a re d e d ic a te d a s in p u ts fo r tw o m u lti-tu rn a b s o lu te p o s itio n e n c o d e rs .

4.3.1.1. General Purpose Inputs

T h e o p to is o la te d in p u ts a re d e s ig n e d to w o rk w ith o p e n c o lle c to r o r c o n ta c t s e n s o rs .

9737903b

Figure 13: General purpose inputs

In p u ts IN 0 ÷IN 1 5 re q u ire e x te rn a l + 2 4 V p o w e r s u p p ly. O n L S -4 2 1 -2 1 1 2 in p u t b o a rd , th e
o p e ra tio n p o w e r s u p p ly (O P S ) is u s e d to p o w e r th e in p u ts . T h e c o rre s p o n d in g s e n s o r s h o u ld
b e c o n n e c te d b e tw e e n th e in p u t a n d th e p o w e r s o u rc e g ro u n d . T h e s e n s o r s h o u ld b e a b le to
s in k 1 0 m A @ 2 4 V in o rd e r to a c tiv a te th e in p u t.

24 Doc. #710220125
 LS-221-BL Technical Reference

9737905

Figure 14: LS-221-BL input connection diagram

A P E 0 , A P E 1 a re d e s ig n e d to w o rk a s d a ta in p u ts fo r A b s o lu te P o s itio n E n c o d e rs (A P E ).
B o th in p u ts u s e + 5 V p o w e r s u p p ly. T o a c tiv a te in p u ts A P E 0 , A P E 1 lo a d s h o u ld b e a b le to s in k
20m A @ 5V.

9738902b

Figure 15: Absolute Position Encoder (APE) inputs

T w o e ig h t-b it re g is te rs re p re s e n t IN 0 ÷IN 1 5 s ta te .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0x8 Read IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0
Base Addr + 0x9 Read IN15 IN14 IN13 IN12 IN11 IN10 IN9 IN8
Table 14: Input registers
25 Doc. #710220125
 LS-221-BL Technical Reference

When input is activated (i.e. the sensor is closed) the corresponding input register bit is set to logic
zero. For non-activated inputs register bits are set to logic one.

4.3.1.2. Hall-sensor Inputs

L S -4 2 1 -2 1 1 2 is e q u ip p e d w ith s ix (th re e p e r a x is ) d e d ic a te d in p u ts fo r H a ll-s e n s o rs . T h e
in p u ts u s e + 5 V p o w e r s u p p ly. T o a c tiv a te th e m , lo a d s h o u ld b e a b le to s in k 2 0 m A @ 5 V .

9737908b

Figure 16: Hall-sensor inputs

T h e H a ll-s e n s o r in p u ts c a n n o t b e a c c e s s e d d ire c tly fro m th e h o s t c o m p u te r. T h e M C 1 2 3 1 A
re g is te rs s h o u ld b e u s e d to re a d th e ir s ta tu s .

4.3.1.3. High Speed Position Capture Inputs

M C 1 2 3 1 A D S P m o tio n c o n tro l c h ip s e t is a b le to re c o rd th e a b s o lu te m o to r p o s itio n u s in g
e n c o d e r in d e x lin e a s s tro b e . S e e M C 1 2 3 1 A m a n u a l fo r in fo rm a tio n h o w to u s e p o s itio n c a p tu re
m o d e . L S -2 2 1 -B L is e q u ip p e d w ith s p e c ia l lo g ic , w h ic h a llo w s re p la c in g th e e n c o d e r in d e x
s ig n a l w ith s o m e o f th e c o n tro lle r in p u ts . W ritin g c o rre s p o n d in g n u m b e r to P C S (P o s itio n
C a p tu re S e le c t) re g is te r s e le c ts o n e o f IN 6 , IN 9 , IN 1 0 , IN 1 1 , IN 1 2 , IN 1 3 in p u ts to s e rv e a s a
s tro b e .

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xE Write PCS3 PCS2 PCS1 PCS0 APE RES
Table 15: PCS control registers
E ith e r lo w (in p u t is c lo s e d to th e g ro u n d ) o r h ig h (in p u t is o p e n ) le v e l m a y b e s e le c te d to
trig g e r th e c a p tu re . F o r L S -4 2 1 -2 1 1 2 s e le c te d s tro b e in p u t is c o m m o n fo r b o th a x e s . R o w 1 4 o r
1 5 s h o u ld b e s e le c te d d u rin g th e h o m e p ro c e d u re . T h is w ill a llo w e a c h a x is to c a p tu re m o to r
p o s itio n u s in g its o w n e n c o d e r in d e x s ig n a l.

26 Doc. #710220125
 LS-221-BL Technical Reference

# PCS3 PCS2 PCS1 PCS0 Channel#0 Channel#1 Active level

0 0 0 0 0 IN 6 IN 6 Low
1 0 0 0 1 IN 6 IN 6 H ig h
2 0 0 1 0 IN 7 IN 7 Low
3 0 0 1 1 IN 7 IN 7 H ig h
4 0 1 0 0 R e se rve d R e se rve d -
5 0 1 0 1 N o t use d N o t use d -
6 0 1 1 0 IN 2 IN 2 Low
7 0 1 1 1 IN 2 IN 2 H ig h
8 1 0 0 0 IN 5 IN 5 Low
9 1 0 0 1 IN 5 IN 5 H ig h
10 1 0 1 0 IN 8 IN 8 Low
11 1 0 1 1 IN 8 IN 8 H ig h
12 1 1 0 0 IN 9 IN 9 Low
13 1 1 0 1 IN 9 IN 9 H ig h
14 1 1 1 0 Ind e x# 0 Ind e x# 1 Low
15 1 1 1 1 Ind e x# 0 Ind e x# 1 Low
Table 16: Selecting Strobe Inputs

4.3.1.4. Emergency Stop Inputs (optional)

In s o m e c u s to m iz e d c o n fig u ra tio n s , o n e o r m o re o f g e n e ra l-p u rp o s e in p u ts m a y b e u s e d a s
a d d itio n a l e m e rg e n c y s to p . T h e s ta n d a rd v e rs io n o f L S -4 2 1 -2 1 1 2 d o e s n ’t s u p p o rt th is o p tio n .

4.3.2. Incremental Encoder Interface

L S -4 2 1 -2 1 1 2 in p u t b o a rd is d e s ig n e d to w o rk w ith q u a d ra tu re in c re m e n ta l e n c o d e rs w ith in d e x
p u ls e . E n c o d e rs m u s t b e e q u ip p e d w ith o p e n c o lle c to r o u tp u ts o r lin e d riv e rs c a p a b le to s in k
2 0 m A @ 5 V . M e d iu m -s p e e d H P 2 5 3 1 o p to c o u p le rs a re u s e d to p ro v id e 2 0 m A c u rre n t lo o p fo r
in c re a s e d n o is e im m u n ity. L S -4 2 1 -2 1 1 2 re c e iv e rs a re ra te d fo r s p e e d s u p to 1 ,0 0 0 ,0 0 0 e n c o d e r
c o u n ts p e r s e c o n d .

9737906b

Figure 17: Incremental Encoder interface

27 Doc. #710220125
 LS-221-BL Technical Reference

T o p re v e n t v o lta g e d ro p a c ro s s lo n g in te rfa c e c a b le s , L S -2 2 1 -B L p ro v id e s + 9 V fo r e n c o d e r
p o w e r. A d d itio n a l 7 8 0 5 v o lta g e re g u la to r lo c a te d c lo s e to th e e n c o d e rs is re q u ire d .

9737907

Figure 18: Encoder power supply

See application notes for more information.

4.3.3. Multi-turn Absolute Encoder Receiver

L S -4 2 1 -2 1 1 2 is d e s ig n e d to w o rk w ith tw o m u lti-tu rn a b s o lu te p o s itio n e n c o d e rs . T h e
fo llo w in g typ e s fro m T a m a g a w a S e ik i C o a re s u p p o rte d :
S A 3 5 -1 1 /2 4 b it-L P S -5 V
S A 5 6 -1 1 /2 4 b it-L P S -5 V
S A 3 5 /5 6 s e rie s e n c o d e r c o n s is ts o f tw o p a rts – in c re m e n ta l a n d a b s o lu te . T h e in c re m e n ta l
p a rt w o rk s a s s ta n d a rd in c re m e n ta l e n c o d e r. It s h o u ld b e c o n n e c te d to L S -4 2 1 -2 1 1 2
in c re m e n ta l e n c o d e r in te rfa c e . T h e d a ta fro m S A 3 5 /5 6 in c re m e n ta l e n c o d e r is re c e iv e d a n d
p ro c e s s e d b y M C 1 2 3 1 A m o tio n c o n tro l c h ip s e t. S A 3 5 /5 6 a b s o lu te p a rt c o n s ta n tly tra n s m its
s e ria l d a ta c o n s is tin g o f 2 4 -b it a b s o lu te p o s itio n a n d 6 -b it s ta tu s . M a n c h e s te r c o d e w ith 3 -b it
C R C is u s e d . R e c e iv e d d a ta is d e c o d e d , c h e c k e d fo r e rro rs a n d s to re d in 2 4 -b it d a ta re g is te r
a n d 6 -b it s ta tu s re g is te r, a v a ila b le to th e h o s t. T h e re is o n ly o n e d a ta a n d s ta tu s re g is te r fo r
b o th a b s o lu te e n c o d e rs . R e c e iv e r w o rk s o n re q u e s t. R e q u e s t fro m th e h o s t s e le c ts o n e o f th e
e n c o d e r in p u ts A P E 0 , A P E 1 a n d c le a rs A P E d a ta re a d y fla g . C le a rin g A P E re a d y e n a b le s
re c e iv e r. It a c q u ire s o n e v a lid d a ta p a c k e t a n d s e ts A P E d a ta re a d y fla g to lo g ic o n e . T h e re a fte r
th e re c e iv e r e n te rs s ta n d b y m o d e a n d w a its fo r th e n e x t re q u e s t c o m m a n d .
O n c e A P E re a d y fla g is s e t to lo g ic o n e A P E d a ta a n d s ta tu s a re v a lid a n d m a y b e re a d b y
th e h o s t. T h e m in im a l tim e to c o m p le te th e re q u e s t is 6 7 ÷1 0 9 µs . In n o is y e n v iro n m e n t th is tim e
m a y in c re a s e . If th e re c e iv e r d e te c ts a n e rro r, it w ill d is c a rd re c e iv e d d a ta a n d a u to m a tic a lly
s ta rt n e w a c q u irin g p ro c e d u re . In m o s t c a s e s th e re q u e s t w ill b e c o m p le te d fo r le s s th a n 1 m s .
T o re q u e s t a b s o lu te p o s itio n fro m c e rta in e n c o d e r, h o s t s h o u ld w rite a d u m m y d a ta to th e
c o rre s p o n d in g re g is te r.

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0x404 Write REQ APE#0
Base Addr + 0x405 Write REQ APE#1
Table 17: APE request registers

A P E d a ta a n d s ta tu s re g is te rs a re lo c a te d a s fo llo w s :

28 Doc. #710220125
 LS-221-BL Technical Reference

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0x404 Read APE D7 APE D6 APE D5 APE D4 APE D3 APE D2 APE D1 APE D0
Base Addr + 0x405 Read APE D15 APE D14 APE D13 APE D12 APE D11 APE D10 APE D9 APE D8
Base Addr + 0x406 Read APE D23 APE D22 APE D21 APE D20 APE D19 APE D18 D17 APE D16
Base Addr + 0x407 Read APE RDY BE OF OS BA PS CE

Table 18: APE data & status registers

T h e fo llo w in g is a b rie f d e s c rip tio n o f th e a b b re v ia tio n s u s e d in T a b le 1 8 . F o r m o re
in fo rm a tio n p le a s e re fe r to T a m a g a w a S A 3 5 /5 6 -1 1 /2 4 b it-L P S -5 V d a ta s h e e t.

APE RDY APE ready flag. If READY=1, data and status are valid. If READY=0, data acquiring is in
progress.
APE D23 ÷ D0 Absolute position encoder data
CE Counter error status
PS Pre-load status
BA Battery alarm
OS Over-speed
OF Over-flow
BE Battery error

S A 3 5 /5 6 n e e d s re s e t a fte r b e in g d is c o n n e c te d o r to c le a r a n e rro r (i.e . o v e r-s p e e d , o v e r-

flo w ). T o re s e t e n c o d e r, lo g ic o n e s h o u ld b e w ritte n to th e c o rre s p o n d in g c o n tro l b it. S A 3 5 /5 6
re q u ire s re s e t s ig n a l to b e h e ld fo r a t le a s t 4 ÷5 s e c . T o e n a b le S A 3 5 /5 6 , lo g ic z e ro s h o u ld b e
w ritte n to th e s a m e c o n tro l b it.

R/W access D7 D6 D5 D4 D3 D2 D1 D0
Base Addr + 0xE Write PCS3 PCS2 PCS1 PCS0 RES

Table 19: APE reset control bit

T a m a g a w a S A 3 5 /5 6 m u lti-tu rn a b s o lu te e n c o d e r re q u ire s a s m a ll e x te rn a l b a tte ry to k e e p
tra c k o f m o to r p o s itio n w h e n th e m a in p o w e r is o ff. A fu lly c h a rg e d L S -4 2 1 -2 1 1 2 o n -b o a rd
b a tte ry is c a p a b le to p o w e r tw o S A 3 5 e n c o d e rs fo r m in 3 0 0 h o u rs . D u rin g th e n o rm a l o p e ra tio n
th e b a tte ry is a u to m a tic a lly re c h a rg e d .

29 Doc. #710220125
 M O T0 R A
M OT0 R N .C . N .C . M OT1 R
M O T1 R D

M OT1 T
M OT0 T

M OT1 S
M OT0 S
M OT0 R

M OT1 R
M O T0 S E A B C D
M O T0 T F
OUT0 H M OT0 S M OT0 T OU T0 M OT1 S M OT1 T
TO M O TO R TE R M IN AL S M O T1 S J
4.4. Interface Wiring

(B A SE M O D U L E ) M O T1 T K E F H J K
OUT1 L
OUT2 M
OUT3 N OU T1 OU T2 OU T3 OU T4
OUT4 P

2 4V
APE R ES R L M N P

OU T7
OU T6
OU T5
OU T4
OU T3
OU T2
OU T1
OU T0
OUT5 S

2 4V /S P S
2 4V /O P T
OUT6 T

2 4V /O P S
OUT7 U APERES OU T5 OU T6 OU T7 N .C .
W R S T U V
2 4 V /S P S X
TO C N 2 C O N N EC TO R 2 4 V /O P S Y
2 4 V /O P T Z 2 4V /S P S 2 4V /O P S 2 4V /O P T
(B A SE M O D U L E )
standard interface wiring is shown below.

W X Y Z
2 x2 0 FE MA LE
24V
APE0 APE1 IN 0 IN 1
1 2 APE RE S APE RE S R a b c d
3 4 APE0 APE0 a
5 6 APE1 APE1 b IN 2 IN 3
IN 0 /A PE 2 IN 0 c
IN 1 /A PE 3 IN 1 d e f
7 8
IN 2 IN 2 e

30
9 10 IN 3 IN 3 f
IN 4 IN 4 h
IN 5 IN 5 j IN 4 IN 5
11 1 2
IN 6 IN 6 k h j
13 14 IN 7 IN 7 l
IN 8 IN 8 m
15 16 IN 9 IN 9 n IN 6 IN 7 IN 8 IN 9
IN 1 0 IN 1 0 p
IN 11 IN 11 r k l m n
17 18 IN 1 2 IN 1 2 s
19 20 IN 1 3 IN 1 3 t
IN 1 4 IN 1 4 x IN 1 0 IN 11 IN 1 2 IN 1 3
21 22 IN 1 5 IN 1 5 y p r s t
+9 V +9 V w
23 24 +9 V +9 V
B AT B AT FF
S H IEL D E N C .G N D +9 V IN 1 4 IN 1 5

Figure 19: Standard Interface Wiring

25 26 B AT B AT
GN D GN D v u v w x y
27 28 GN D GN D u
HB1 HB1 JJ
29 30 HC1 4 0 C O N D U C T O R R IBB O N C AB LE HC1 CC C0 HC0 C1 HC1
C1 C1 BB
HA1 HA1 NN z AA BB CC
31 32
A1 A1 M M
33 34 B1 B1 HH
HB0 HB0 EE B0 HB0 B AT B1 HB1
35 36 HC0 HC0 AA
C0 C0 z DD EE FF HH JJ
37 38 HA0 HA0 LL
A0 A0 KK
B0 B0 DD A0 HA0 A1 HA1
39 40
KK LL MM NN
.
TO C N 1 01 C O N N EC T O R
5 6 - P IN E L C O C O N N E C T O R
(IN P U T B O A R D ) (F R O N T V IE W )

97 29 50 1b
on the front panel and is connected to the controller with a set of wires (user harness). The LS-221-BL
user-defined interface and pinout, the interface connector is designed as separate module. It is mounted

Doc. #710220125
LS-221-BL may be equipped with various interface connectors. To allow fast and easy adaptation to
LS-221-BL Technical Reference
 LS-221-BL Technical Reference

4.5. Power Supply

L S -2 2 1 -B L c o n tro lle r re q u ire s tw o e x te rn a l p o w e r s u p p lie s - o p e ra tin g p o w e r (2 4 V D C ) a n d
m o to r p o w e r (2 4 ÷8 0 V D C ). T h e m o to r p o w e r s u p p ly is u s e d to d riv e th e m o to rs o n ly. T h e
o p e ra tin g p o w e r s u p p ly is u s e d to p o w e r th e o n b o a rd in p u t a n d o u tp u t c irc u its a n d , o p tio n a lly,
to p o w e r th e s e n s o rs a n d o th e r c irc u its in th e c o n tro lle d s ys te m .

Im p o rta n t: No te th a t th e m o to r p o w e r is
flo a tin g . T h is is re q u ire d fo r p ro p e r o p e ra tio n o f
th e p ro te c tio n c irc u its . O th e rw is e , in c a s e o f w ro n g
w irin g o r a s h o rt c irc u it, c o n tro lle r a n d /o r u s e r
e le c tro n ic s m a y b e d a m a g e d .

C N 3 c o n n e c to r is th e e n try fo r th e e x te rn a l p o w e r s u p p lie s . In a d d itio n , th e e m e rg e n c y s to p

is c o n n e c te d h e re . T h e s c h e m a tic o f a typ ic a l p o w e r s u p p ly fo r L S -2 2 1 -B L is s h o w n b e lo w :

T O L S -2 2 1 -B L S E R V O C O N T R O L L E R
(C N 3 C O N N E C TO R )

M OTO R PO W E R

24 - 80V

M A IN S Z E N E R D IO D E
3 0 -1 0 0 V / 0 .5 W
(O V E R V O LTA G E
SHUT DOWN)
O P E R AT IN G P O W E R

24V

E M ER G EN C Y S TOP

9 7 2 9 92 0 b

Figure 20: Typical power supply

31 Doc. #710220125
 LS-221-BL Technical Reference

5. BOARD SETUP

5.1. Base I/O Address

U p to 8 b o a rd s m a y b e in s ta lle d in o n e c o m p u te r.

0 x0 2 8 0 0 x0 2 A 0 JUMPER OPEN

0 x1 2 8 0 0 x1 2 A 0 JUMPER CLOSED

0 x2 2 8 0 0 x2 2 A 0

0 x3 2 8 0 0 x3 2 A 0

9 72 91 0 6b

Figure 21: Base I/O Address (J1 jumper block)

5.2. Interrupt Line

T h e re a re fo u r h a rd w a re in te rru p t lin e s a v a ila b le . It is n o t a llo w e d IR Q lin e to b e s h a re d w ith
a n o th e r L S -2 2 1 -B L c o n tro lle r o r o th e r d e v ic e .

IR Q 7 JUMPER OPEN

IR Q 1 0 JUMPER CLOSED

IR Q 1 2

IR Q 1 5

9 72 91 0 7b

Figure 22: Interrupt line (J2 jumper block)

32 Doc. #710220125
 LS-221-BL Technical Reference

5.3. Current Limit Mode

C U R R E N T L IM IT JUMPER OPEN

SHUT DOWN JUMPER CLOSED

9 72 91 0 8b

Figure 23: Current Limit Mode (J3 jumper)

5.4. Servo Off Mode

S M OOT H STO P JUMPER OPEN

FA S T S T O P JUMPER CLOSED

9 72 91 0 9b

Figure 24: Servo Off Mode (J4 jumper)

33 Doc. #710220125
 LS-221-BL Technical Reference

6. APPLICATION NOTES

A97 2900 2

Figure 25: Absolute encoder sample wiring

34 Doc. #710220125
 LS-221-BL Technical Reference

7. BASIC CONTROL PROCEDURES

T h is s e c tio n s h o w s a lg o rith m flo w c h a rts fo r s o m e b a s ic c o n tro l p ro c e d u re s .

7.1. Board identification

Start

Extract high ID nibble

(Read Base addr. + 0xC07)

Extract low ID nibble

(Read Base addr. + 0x807)

Form ID number

Validate ID No Identification error End

Yes

Identification OK

End

35 Doc. #710220125
 LS-221-BL Technical Reference

7 .2 . B o a rd In itia liza tio n a n d P o w e r O n

Start

Yes
RST == 0 MC1231A is already initialized

No

Initialize MC1231A

No Error initializing MC1231A

Init == OK End
Set RST = 1; SPS = 0
Yes

Deactivate all outputs

APE RES = 0
Disable ADI

Yes Emergency Stop is activated

EMG == 1 or Operation Power is missing End
Set SPS = 0
No

Activate SPS
(Set SPS = 0; Set SPS = 1)

Wait 100 mS

Yes Operation Power is out of range

OPF == 1 or an output is overloaded End
Set SPS = 0
No

Yes Motor Power is out of range

MPF == 1 or there is a leakage End
Set SPS = 0
No

Initialize with default values

PCSi = default;
Outputs = defaults;
OPT = default;
Current limit[i] = defaults

End

36 Doc. #710220125
 LS-221-BL Technical Reference

7.3. Enable Amplifiers

Start

Yes
AE == 1 The amplifiers are already enabled End

No
No
SPS == 1 SPS is not activated End

Yes

OPF == 0 No
& Operating Power or Motor Power End
MPF == 0 are missing

Yes

Send STOP Command to MC1231A

Yes
Moving axis ? One or more axes are moving End

No
Activate AE
(AE=0; AE=1)

Wait 150 mS

No The amplifier enable failed

AE == 1 End
Run amplifier diagnostic

Yes

Set up Amplifier Disable Interrupt

if proper interrupt handler is installed
(EN ADI = 1)

End

37 Doc. #710220125
 LS-221-BL Technical Reference

7.4. Disable amplifier

Start

Disable EN ADI
(EN ADI=0)

Deactivate AE
(AE=0)

End

38 Doc. #710220125
 LS-221-BL Technical Reference

7.5. Diagnostic – Finding Out the Reason Caused Amplifier Disable

Start

Yes
AE ==1 Amplifier is enabled End

No

Yes
EMG(L) ==1 Update status: Emergency Stop activated

No
Yes
STP(L) == 1 Update status: Emergency Input activated
Yes

No

MPF(L) == 1 Update status: Motor Power Failure

No
Yes
OPF(L) == 1 Update status: Operating Power Failure

No
Yes
CL0 == 1 Update status: Amplifier channel #0 overloaded

No
Yes
CL1 == 1 Update status: Amplifier channel #1 overloaded

No
If no hardware Amplifier Disable reasons found,
amplifier disabled by software.

End

39 Doc. #710220125
LOGOSOL

Logosol, Inc.
1155 T asman Driv e
Sunny v ale, CA 94089
USA
Document No 710220125
T el: (408) 744 0974 © 1999 Logosol, Inc.
Fax: (408) 744 0977 Printed in USA
Http://www.logosolinc.com