This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics
A Reduced Switch Count Three-Phase AC/AC
Converter with Six Power Switches: Modeling,
Analysis, and Control
Mojtaba Heydari, Member, IEEE, Alireza Fatemi, Member, IEEE, and Ali Yazdian Varjani, Member,
IEEE
 translates to increased cost, weight, and size of the system and
Abstract—Reducing the number of semiconductor
switches in power electronics converters has been a
continuing effort in recent years as a measure to enhance
the system reliability and to decrease its size, weight, and
component cost. For these reasons, a new reduced switch
count three-phase AC/AC converter is being proposed.
Being realized by only six active switches and anti-parallel
diodes, the proposed converter topology employs the
minimum number of semiconductor devices amongst the
converters of its kind. It also features unity power factor,
regenerative operation, pulse width modulated output
voltage, and sinusoidal input current. The reduced number
of switches results in a simplified associated gate drive
circuit as well as cooling system which, in turn, may
reduce the overall manufacturing cost and increase the
reliability, especially in low voltage and low power
applications. The modulation scheme of the new converter
is developed, and a control algorithm is proposed for the
converter’s rectifier side. Moreover, an analysis is
performed on the DC link capacitor sizing for the purposes
of reducing the DC link voltage ripple, and balancing the
input current and lowering its THD. The simulation and
experimental results corroborate the transient and steady
state performance of the proposed converter topology.
Index Terms—Three-phase AC/AC converter, Reduced switch
count converter, DC-link capacitor sizing, DC-link voltage ripple
reduction, Back to back AC/AC converter
I. INTRODUCTION
B I-BIDIRECTIONAL power flow, unity power factor, and
sinusoidal input currents can be achieved by conventional
back-to-back (B2B) active-front-end converters (B6-B2B). A
drawback of B6-B2B converters is the use of 12 active
switches and antiparallel diodes in their structure which
Manuscript received December 16, 2016; revised January 30, 2017;
accepted June 04, 2017.
M. Heydari is with the Faculty of Electrical and Computer Engineering,
Qom University of Technology (QUT), Qom, Iran (e-mail: heydari@qut.ac.ir)
A. Fatemi is with General Motors Global Research and Development,
Pontiac, MI 48340, USA (e-mail: alireza.fatemi@gm.com)
A. Yazdian Varjani is with the Department of Electrical and Computer
Engineering, Tarbiat Modares University, Tehran, Iran (e-mail:
yazdian@modares.ac.ir)
2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
reduced reliability. Furthermore, the double-stage power
conversion, that is AC to DC at the rectifier side and DC to
AC at the inverter side, incurs additional power losses. The
required bulky DC-link storage element is considered as
another disadvantage of B6-B2B converters.
Many recent studies focus on developing reduced switch
count converters (RSCC) in a B2B configuration [1-17]. Such
RSCCs can contribute to the system reliability, and can help to
reduce size and cost, particularly in low power applications
where these considerations are more pressing, i.e. robotics.
This can be especially of interest when wide band gap (WBG)
switching devices are used [18]. Numerous topologies have
been proposed for B2B-RSCCs such as the B4-B2B converter
shown in Fig. 1 [2]. Being comprised of a B4 converter at
each end, this B2B converter has eight active switches and
antiparallel diodes, and hence the number of switches is
reduced by 33 % compared to B6-B2B. This configuration is
composed of an active rectifier structure that provides the
capability of drawing sinusoidal input currents with unity
power factor and the bidirectional power flow. Moreover, a
four-switch inverter with split capacitors in the DC link
produces balanced three-phase waveforms in the output
terminals. The B4-B2B converter has been suggested as a low
cost alternative for common B6-B2B converters in a number
of applications such as AC motor drives, power conditioners,
and renewable energy systems [3-5].
Another example of RSCCs which was proposed in [19],
and was subsequently used in [1, 9], and [16] as a three-phase
AC/AC converter, is realized by sharing a complete row of
switches between two B6 converters, as illustrated in Fig. 2.
Being comprised of nine active switches and antiparallel
diodes, the new topology is called a nine-switch converter
(NSC). This structure not only retains the major desirable
features of B6-B2B, but also reduces the number of required
switches by 25% and hence proves more attractive in low
voltage and power ratings applications [9]. Similar to other
RSCCs, the reduction of the number of switches in the NSC is
achieved at the expense of an elevated DC bus voltage level.
As a result, the NSC is more suitable for low voltage, and low
power applications due to the increased voltage stress on the
switches which translates into higher device rating, increased
switching loss, and electromagnetic interference (EMI) issues.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics
Power Grid
Li C1
C2
Fig. 1. B4-B2B reduced switch count AC/AC converter
Power Grid
Li
Three-Phase Load
C RSCC shown in Fig. 1, but further reducing the number of
Fig. 2. Nine-switch AC/AC converter
In this paper, combining the methods of switch reduction in
the NSC and B4 converters, a new AC/AC converter is
proposed. The total number of active switches in the proposed
converter is six, thus leading to a reduction in the number of
switches by 33% and 25%, when compared with NSC and B4-
B2B converters, respectively. The proposed configuration
establishes a record low number of switches thus far obtained
for a reduced switch count three-phase AC/AC converter with
active front end. In the proposed converter, the number of
semiconductor switches, gate drives and hence cooling
systems is considerably less than conventional topologies,
which, in turn, may reduce the overall manufacturing cost and
increase the reliability especially in low voltage and low
power applications.
The topology of the proposed converter and its carrier-
based PWM scheme are described in the following section.
Two designated modes of operation are defined for the
converter and are elaborated upon in Section III. Design
considerations of active and passive elements as well as
reliability analysis and an investigation of the converter loss
profile, including switching and conduction losses, are
provided in Section IV. It is demonstrated in the same section
that proper DC-link capacitor sizing minimizes the DC-link
voltage ripple, balances the input current and suppresses its
total harmonic distortion (THD). The dq0-based control
scheme in the synchronous reference frame which is used to
regulate the DC bus voltage level and the input current is
presented and the simulation results are provided in section V.
Section VI is dedicated to presentation of the experimental
results and discussion of system steady-state and dynamic
responses. Finally, the conclusions of this paper are reviewed
in section VII.
2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
II. THE PROPOSED THREE-PHASE SIX-SWITCH AC/AC
CONVERTER
Three-Phase Load
This section first describes the switch arrangement in the
new configuration, followed by presenting the developed
carrier-based PWM scheme.
A. The Proposed Configuration
The topology of the proposed three-phase AC/AC converter
is shown in Fig. 3. It consists of two switch-legs, each with
three power switches, and one capacitor-leg with three
capacitors put in series to form the DC bus. Two phases of
each three-phase terminal are connected to the two-switch legs
whereas the third phase is connected to the middle nodes of
the DC link capacitors. The four upper switches function as a
B4 PWM rectifier and the four lower switches function as a
B4 inverter, thus sharing the middle row of the switches. The
operation of the proposed configuration is comparable to the
active switches by 25%. The proposed structure can also be
considered as a post-fault configuration of a NSC capable of
supplying the load with the remaining switches after a short-
circuit or open-circuit fault in one of the legs. Furthermore,
utilization of the proposed converter can decrease the number
of current sensors required for closed-loop applications. This
is owing to the fact that the currents of middle switches are
equal to the input or output currents during particular
switching states, i.e. those in which both upper or both lower
switches are off correspondingly cause the input or output
currents to pass through the middle switches. Therefore, using
only two current sensors in series with middle switches and
assuming balanced input and output, i.e. ia +ib +ic =0, the two
three-phase currents could be measured.
Two modes of operation are defined for the proposed
converter. The first mode is called the different frequency
(DF) mode in which the frequencies as well as the amplitudes
of the rectifier side, here the upper terminal, and the inverter
side, here the lower terminal, are independent. The second
mode is called the equal frequency (EF) mode in which the
frequency of the inverter side, i.e. load, is equal to the
frequency of the rectifier side, or grid, with different phase
angles and amplitudes at each side in order to control the
S4 S1
Power Grid aV dc Cd1
Ar
Br
Li Cr
S5 S2
Three-Phase Load
bV dc Cd2
Ai
Bi
Ci
S6 S3
cV dc Cd3
Fig. 3. The proposed six-switch AC/AC converter
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

power flow between the grid and the load. the input connected to the leg is positive and the output is
The voltage levels of the DC link capacitors in the new negative, when the lower switch of each leg is OFF, state Q3,
converter are to be determined so as to achieve balanced both input and output connected to the leg are positive.
output voltages/currents without a DC component. This will The three allowed states of each leg create a total of nine
be thoroughly investigated in the third section. switching modes for the converter. These switching modes are
shown in Fig. 6, in which the ON and OFF switch modes are
B. Developing the Carrier Based Sinusoidal Pulse Width
respectively represented by black and gray color lines.
Modulation Scheme (CB-SPWM)
Moreover, the resultant phase voltages at the rectifier and
Fig. 4 displays the carrier-based SPWM modulation scheme inverter sides are provided in Table II.
of the proposed converter and the resultant switching vectors. In Fig. 3, the DC-link capacitors voltage levels are defined
For each leg, there are two reference signals for the rectifier as a function of three a, b and c coefficients. These
side (Vxr, x = (A, B)) and two for the inverter side (Vxi, x = (A, coefficients should be determined such that the three-phase
B)). The interference of the rectifier and inverter modulation voltages at the rectifier and inverter terminals are balanced and
signals should be prevented at any given time. In this case, the without any DC component. Let the three-phase source
rectifier modulation signal should be higher than the inverter voltage be:
modulation signal at any moment (Vxr >Vxi). This is realized
v As V m sin r t  (1)
by adding proper offsets to the reference signals, the
calculations of which are carried out in the next section. v Bs V m sin r t  2 / 3 (2)
Consequently, two modulation signals are obtained for each v Cs V m sin r t  2 / 3 (3)
leg which will be compared to a high frequency triangular
where Vm, and ωr are the amplitude and angular frequency of
carrier to generate the switching gate signals according to the
the grid voltage, respectively.
block diagram shown in Fig. 5.
The modulation signals of the rectifier side are expressed in
The gate signals of the middle switches in each leg are
(4), and (5):
produced by the logical XORs of the gate signals of the upper
and lower switches of the same leg as shown in Fig. 5. Such
*
v Ar  m r sin rt    offset r (4)
operation ensures that out of the eight possible switching *
v Br  m r sin rt   r   offset r (5)
states that can be generated by the three switches of each leg, where mr, and ψ are the modulation index and the phase angle
five of which that cause DC bus short-circuit or floating of the of the rectifier reference voltage, respectively. offsetr is the
loads are avoided. The three acceptable switching states are added offset, and φr is the phase difference between the
listed in Table I. When the upper switch of each leg is OFF, reference waveforms of the two legs.
state Q1, both input and output connected to that leg are The similarity of the triangles in Fig.4 yields the following
negative, when the middle switch of each leg is OFF, state Q2, equations for T1 and T2 switching periods:
 
1 Ts
vAr* T1  1  v Ar
*
(6)
T1 2

 
*
v T
T 2  s 1  v Br
Br *
0
T2 T/2 (7)
2
T3
vAi* Using Table II, the average of VAr is determined next:
T4
vBi*  aV V
-1 V Ar  T s  T 2  DC  T 2  T1  2a  b  c  DC 
 3 3
S1 1 1 0 1 1 1 0 1 1 (8)
V 
S4 1 0 0 0 1 0 0 0 1
T1 b  c  DC  / T s
S3 0 0 0 1 0 0 0 1 3 
S6 1 0 1 1 1 0 1 1
Following the same method for the voltages of the
Fig. 4. Carrier based SPWM scheme and the resultant switching vectors remaining two phases (VBr and VCr) and replacing v*Ar and v*Br
with their equivalents from (4) and (5), the fundamental values
Rectifier Offset
of the rectifier side phase voltages are obtained in (9)-(11):
a b c  a b c 
V Ar V DC         m r sin r t    
0 0
+
Rectifier Ref +
6 6 6  3 3 3 
+
S1 , S4 (9)
*v xr _
a b c  a b c  
    m r sin r t     r       offset r 
S2 , S5 6 6 6 6 6 6 
0 0
Inverter Ref + + TABLE I
+
S3 , S6 SWITCHING STATES OF EACH LEG
*v xi _
Switching States Q1 Q2 Q3
Inverter Offset S1 OFF ON ON
0
Carrier S2 ON OFF ON
Fig. 5. Gate signal generation block diagram S3 ON ON OFF

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

TABLE II
CONVERTER SWITCHING STATES AND THE RESULTANT PHASE VOLTAGES

SWITCHING STATES INVERTER SIDE PHASE VOLTAGES GRID SIDE PHASE VOLTAGES

S1 S2 S3 S4 S5 S6 VAi VBi VCi VAr VBr VCr

0 1 1 0 1 1 -cVDC/3 -cVDC/3 2 cVDC /3 -(b+c)VDC/3 -(b+c)VDC/3 2(b+c)VDC/3
0 1 1 1 0 1 -cVDC/3 -cVDC/3 2 cVDC /3 (-a-2b-2c)VDC/3 (2a+b+c)VDC/3 (-a+b+c)VDC/3
0 1 1 1 1 0 (-a-b-2c) VDC/3 (2a+2b+c)VDC/3 (-a-b+c)VDC/3 (-a-2b-2c)VDC/3 (2a+b+c)VDC/3 (-a+b+c)VDC/3
1 0 1 0 1 1 -cVDC/3 -cVDC/3 2 cVDC /3 (2a+b+c)VDC/3 (-a-2b-2c)VDC/3 (-a+b+c)VDC/3
1 0 1 1 0 1 -cVDC/3 -cVDC/3 2 cVDC /3 aVDC/3 aVDC /3 -2 aVDC /3
1 0 1 1 1 0 (-a-b-2c)VDC/3 (2a+2b+c)VDC/3 (-a-b+c)VDC/3 aVDC /3 aVDC /3 -2 aVDC /3
1 1 0 0 1 1 (2a+2b+c)VDC/3 (-a-b-2c) VDC/3 (-a-b+c)VDC/3 (2a+b+c)VDC/3 (-a-2b-2c)VDC/3 (-a+b+c)VDC/3
1 1 0 1 0 1 (2a+2b+c)VDC/3 (-a-b-2c) VDC/3 (-a-b-2c)VDC/3 aVDC /3 aVDC /3 -2 aVDC /3
1 1 0 1 1 0 (a+b)VDC/3 (a+b)VDC/3 -2(a+b)VDC/3 aVDC /3 aVDC /3 -2 aVDC /3

Ar Ar Ar
Br AC Term 1 Br AC Term 1 Br AC Term 1
Cr Cr Cr

Ai Ai Ai
Bi AC Term 2 Bi AC Term 2 Bi AC Term 2
Ci Ci Ci

Mode 1 Mode 2 Mode 3

Ar Ar Ar
Br AC Term 1 Br AC Term 1 Br AC Term 1
Cr Cr Cr

Ai Ai Ai
Bi Bi Bi
AC Term 2 AC Term 2 AC Term 2
Ci Ci Ci

Mode 4 Mode 5 Mode 6

Ar Ar Ar
Br AC Term 1 Br AC Term 1 Br AC Term 1
Cr Cr Cr

Ai Ai Ai
Bi AC Term 2 Bi AC Term 2 Bi AC Term 2
Ci Ci Ci

Mode 7 Mode 8 Mode 9

Fig. 6. Switching modes of the proposed six-switch converter

a b c  a b c  expressed in (12)-(14).
V Br V DC         m r sin r t    
6 6 6  6 6 6  3  
(10) v Ar  m rV DC sin  r t     (12)
a b c  a b c   6  6
    m r sin r t     r       offset r   
3 3 3 6 6 6  v Br 
3
m rV DC sin  r t     (13)
 a b c a b c 
6  2
V Cr V DC          m r sin r t     3  5 
 3 3 3 6 6 6 v Cr  m rV DC sin  r t     (14)
(11) 6  6 
a b c  a b c  
    m r sin r t     r       offset r  For the inverter side of the proposed converter, the
6 6 6 3 3 3 
similarity of the triangles in Fig. 4 can be used again to
Considering (9) to (11) and the fact that a + b + c =1, it is
determine the switching periods.
deduced that for having balanced voltages, φr should be equal
to π/3. Furthermore, the DC link capacitors (coefficients a, b, T3 
Ts
2

1  v Ai
*
 (15)
and c) will assume voltage levels such that the DC component
is eliminated from the three-phase voltages. As an example, if T
2

T 4  s 1  v Br
*
 (16)
offsetr =0.5, then a =0.25, b =0.5, and c =0.25. Fig. 7 illustrates
the DC link voltage coefficients for different offset values where the inverter side modulation waveforms, v*Ai , and v*Bi
added to the rectifier reference voltage. Given these are given in (17), and (18):
assumptions, the final voltage terminal at the rectifier side is
*
v Ai  mi sin i t   offset i (17)

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

V SW 5 
T s T 2 T 4 V V DC offset r  offset i 
DC
Ts (26)
m r sin r t    2 / 3  m i sin i t  2 / 3 / 2 
V SW 6
T

 4 V DC V DC 1  offset i  m i sin i t  2 / 3 / 2
Ts
 (27)

According to the Fig. 8, and based on Kirchhoff's Voltage

Law, we have:
v Cd 1  v sw 4 v BL v Bs v Cs v CL (28)
v Cd 1  v sw 1 v AL v As v Cs v CL (29)
Fig. 7. DC link voltage coefficients per unit DC bus voltage level versus By averaging the above equations over a switching cycle,
rectifier side offset the voltage across the capacitors can be calculated as
*
v Bi  mi sin i t  i   offset i (18) V Cd 1  v sw 4  v BL  v Bs  v Cs  v CL (30)
where mi and offseti are the modulation index of the inverter
V Cd 1  v sw 1  v AL  v As  v Cs  v CL (31)
reference waveform and the added offset to it, respectively,
and ωi is the angular frequency of the load voltage. Considering the fact that the average values of vAs, vBs, vCs,
Repeating the same procedure, the fundamental components vAL, vBL and vCL are equal to zero, one can write
of the inverter side terminal are given in (19)-(21) after V Cd 1  v sw 4  v sw 1 (32)
eliminating the DC signal and setting φi=π/3:
3   According to (22)-(27), VSWi, (i=1-6) has two AC and DC
v Ai  m iV DC sin  i t   (19) components. Since the capacitors are parallel to each source,
6  6
the DC component, indicated by ̅ , will entirely appear across
3   the capacitors.
v Bi  m iV DC sin  i t   (20)
6  2
V Cd 1  v sw 4  v sw 1 V DC 1  offset r  / 2 (33)
3  5 
v Ci  m iV DC sin  i t   (21) Adopting the same procedure, the voltages across the
6  6 
capacitors of the converter are obtained as follows:
C. Investigation of Voltage Balancing across the DC-Link V Cd 2  v sw 2  v sw 5 V DC offset r  offset i  / 2 (34)
Capacitors
In this section, it is demonstrated that the offsets added to V Cd 3  v sw 3  v sw 6 V DC 1  offset i  / 2 (35)
the modulation waveforms determine the capacitors voltage
levels and that DC-link capacitors would spontaneously be III. CONVERTER MODES OF OPERATION
charged at the expected voltage levels without requiring any
The converter has two operation modes, each utilizing two
specific control technique. To investigate the voltage of DC-
different methods to eliminate the DC component from the
link capacitors, the converter switches are replaced with
terminal voltages. In the first method, the voltage levels of the
dependent voltage sources controlled by gate signals. The
DC link capacitors will be constant whereas in the second
equivalent circuit is shown in Fig. 8.
method, those levels will change with the variation of
Considering that at any moment of time only one switch in
converter modulation indexes at the rectifier or inverter sides
each leg is off, the average voltages over a switching cycle can
to provide the maximum DC bus voltage utilization. The
be calculated using the switch off time interval. According to
converter operation modes as well as the methods mentioned
Fig. 4, the off time interval is T1, T3 and Ts-T1-T3 for the upper,
for the DC component elimination are described next and their
lower and middle switches in the first leg, respectively.
advantages and disadvantages are discussed.
V SW 1 
T1
Ts

V DC V DC 1  offset r  m r sin rt    / 2  (22)
+ + +
T T1 T 3 V
 s V DC offset r  offset i  v VCd1 Vsw4
-
Vsw1
-
V SW 2 DC + As - + vAL - -
Ts (23)
m r sin r t     m i sin i t / 2  v v
+ Bs - + BL -
T3
V SW 3  V DC V DC 1  offset i  m i sin i t  / 2 (24) +
vCs
- +vCL -
+
Vsw5
+
Vsw2 Three-Phase Load
Ts + - -
VCd2
Adopting the same procedure, the average voltages for the
-
other leg switches of the converter is obtained as follow.
+ + +
V SW 4 
T2
Ts

V DC V DC 1  offset r  m r sin r t  
(25) -
VCd3 Vsw6
-
Vsw3
-

2 / 3 / 2 Fig. 8. Equivalent circuit for investigating voltages across DC-link capacitors

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

A. Different Frequency (DF) Operation Mode inverter sides in the basic SPWM scheme can ideally reach 1
In this mode of operation, the terminal voltages of the and the DC-link utilization of the proposed converter in EF
rectifier side are fully independent from the terminal voltages mode is similar to B4-B2B converter. The EF mode is
of the inverter side in terms of amplitude and frequency. This especially useful in applications in which there is no need to
mode of operation is suitable for applications in which perform frequency regulation. If the phase difference between
frequency isolation is required. To produce balanced voltages the references is a non-zero value, proper offsets should be
without any DC component in this mode, the following two added to them to prevent their interference. Adding offsets,
methods can be adopted. however, limits the maximum modulation index and changes
the voltage levels of DC link capacitors which are regulated
1) First Method accordingly without requiring any external control. The details
In the first method, to prevent the interference of the upper of the converter operation in this mode are presented in Table
and lower modulating waves and also to avoid over- IV.
modulation, the rectifier and the inverter offsets should
TABLE III
fulfill the criteria shown in Table III. Adding offsets to the SUMMARY OF DC BUS VOLTAGE ADJUSTMENT METHODS IN DF MODE (SEE
references will limit the maximum modulation indexes of SECTION III-A)
both sides by values given in the same table. Moreover, it
First Method Second Method
changes the distribution of the total DC voltage on the DC
link capacitors as specified by coefficients a, b, and c in 1 mi 
a 1  
Table III. As an example, using the first method with
a
1  offset r  2  m r  mi 
offsetr= 0.5 and offseti= -0.5, the maximum modulation Capacitor 2 1
indexes are restricted to 0.5. Voltage b
Coefficients b  offset r 2
If the inverter side and the rectifier side are required to
have terminal voltages of similar voltage ratings, it
(See Fig. 3)
1  offset r  c
1 mr 
c 1  
indicates that they should share equal portions of the total 2 2  m r  mi 
DC link voltage level. Therefore, the maximum
modulation index of both of them will be limited to 0.5 in a Upper and 0  offset r  1 offset r  offset i  1
basic SPWM scheme. This implies that the offsets of each Lower
Offset 1  offset i  0 offset r  1  
side should be 0.5, and -0.5, respectively. These offset Limits
values determine the voltage levels of each of the DC link (See Fig. 4) offset i  offset r offset i  
capacitors as illustrated in Fig. 7; hence the voltage level of
the middle capacitor should be twice the upper and lower m r  m i  offset r  offset i mr  mi  1
Maximum
capacitors voltages in the latter example. In another case of Modulation m r  1  offset r mr  1
interest, if the offsetr=1/3, the voltage levels of all the three Index
m i  1  offset i mi  1
DC link capacitors will be the same.
2) Second Method TABLE IV
The second method increases the maximum modulation SUMMARY OF DC BUS VOLTAGE ADJUSTMENT METHODS IN EF MODE (SEE
index by actively sharing the total DC link voltage level SECTION III-B)
between the output terminals. For this purpose, the offset First Method Second Method
values in Table III are determined based on the rectifier
and inverter modulation indexes using α which determines
the DC bus voltage utilization factor (36). a
1  offset r  a
mr
Capacitor 2
mr 2
 (36) Voltage m r mi
m r  mi Coefficients b  offset r b 1 
2 2
The range of the offsetr, offseti, mr, and mi using the two (See Fig. 3)
c
1  offset r  mi
methods are listed in Table III according to which the 2 c
2
voltage levels of the DC link capacitors depends on the
modulation indexes.
Upper and 0  offset r  1
B. Equal Frequency (EF) Operation Mode Lower offset r  1  m r
Offset 1  offset i  0
As mentioned previously, in the EF mode, the amplitudes of Limits offset i  mi  1
the converter voltage terminals can change independently. (See Fig. 4) offset i  offset r
Their frequencies, however, should be the same. The main
m r  m i  offset r  offset i
advantage of this mode is the increased upper limit of the Maximum mr  1
modulation index, and thus increased DC bus voltage Modulation m r  1  offset r
Index mi  1
utilization. When there is no phase difference between the m i  1  offset i
references, the modulation indexes of both the rectifier and

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

TABLE V
SEMICONDUCTOR SWITCH RATING IN COUNTERPART TOPOLOGIES in terms of per-unit values as in (44).
PG ( pu )  PL ( pu ) V s ( pu ) I s ( pu ) (43)
Nominal Rating of the switches


24 1  3X s ( pu ) I s ( pu ) 
1 2
mr   (44)
 3 
 2PG 
  3 
 2PL 
 V DC ( pu )  
B6-B2B 6*     6*    
 2 
 3V LL G PFG 
  2 
 3V LL  L PFL 

According to (44), maximum modulation index of the
B4-B2B
 3 
 2PG 
  3 
 2PL 
 rectifier side coincides with the maximum input current (Is(pu)
(Fig.1) 4*     4*    
 2 
 3V LL G PFG 
  2 
 3V LL  L PFL 
 =1)
 3  
6*  
2PG
 2   3V LL G PFG

 3   
3*   max 
 2  
2PG
 3V LL G PFG

m r (max) 

24 1  9X s2( pu )  (45)
NSC

V DC ( pu )
(Fig.2) 2PL 2PL 
 
3V LL  L PFL  3V LL  L PFL  According to (45), mr(max) is inversely proportional to the
 3   2PG  3    2PG DC bus voltage level, where its minimum is 2 6V s , and is
4*    2 *   max  
SSC  2   3V LL G PFG  2    3V LL G PFG directly proportional to the series reactance. The required
(Fig.3) 2PL  2PL  rectifier maximum modulation index versus the DC bus
 
3V LL  L PFL  3V LL  L PFL  voltage level for different reactance values when the system is
working under nominal conditions (Is(pu)) is illustrated in Fig.
IV. DESIGN CONSIDERATION 9.
A. Switch Rating C. DC Link Capacitor Sizing
The rating of the active components of the six-switch A method has been developed for the DC link capacitor
AC/AC converter is compared with the counterpart three- sizing of the new converter to minimize the DC link voltage
phase AC/AC converters in Table V (see Appendix A). The ripple and to reduce the size of the capacitors simultaneously.
parameters used to express the nominal ratings are as follows: Provided that the input current of the PWM rectifier is
1) PG: the power drawn from the grid, 2) PFG: The grid power sinusoidal and in-phase with the utility voltage, the three
factor, 3) PL: The power delivered to the load, 4) PFL: The capacitor-voltages can be calculated as a function of the input
load power factor, 5) VLL-G: the line voltage of the grid and 6) and the output currents (see Appendix B).
2
1  offset r  cos  r t  
VLL-L: the line voltage of the load. 1 I sm
V Cd 1 
Cd1 
i Cd 1dt 
2C d 1r  3 
5
1  offset i  cos  i t    
B. Input Inductor Sizing I Lm
 (46)
To find the series inductance value, the grid active/reactive 2C d 1i  6 
power equations can be used (37), (38).  3  2  3 
 m r I sm sin    m i I Lm cos L  t V Cd 1 (0)
VV  4C d 1  3  4C d 1 
PG  s r sin (37)
Xs
2
offset r  1 cos  r t  
1 I sm
V
QG  s V r cos V s  (38)
V Cd 2 
Cd 2 
i Cd 2dt 
2C d 2r  3 
Ls r
5
1  offset i  cos  i t    
I Lm
where Vs, and Vr are the rms values of the grid voltage and the  (47)
2C d 2i  6 
rectifier side terminal voltage, respectively, ψ is the phase
difference between them, and Xs is the series reactance.  3  2  3 
 m r I sm sin    m i I Lm cos L  t V Cd 2 (0)
Ignoring the converter power loss and assuming a unity  4C d 2  3  4C d 2 
power factor, one can write:
PG  PL (39) 1
QG  0 (40)
Considering (37) to (40) and replacing Vr with its equivalent 0.8

term from (12), the inductance value is obtained in (41).

2 0.6
V s2 1  m rV DC 
r(max)

Ls     1 (41) Xs(pu)=0.6
PL r 24  V s  Xs(pu)=0.5
m

0.4
Xs(pu)=0.4
Knowing the inductance value, the maximum modulation Xs(pu)=0.3
index of the rectifier side can be determined as 0.2 Xs(pu)=0.2
Xs(pu)=0.1

V  X P 
2

24 1   s 2 L  
Xs(pu)=0.06
mr  s (42)
V DC   V s  
0
4 6 8 10 12 14 16 18 20
 Vdc(pu)

Adopting Vs and Is as base values, the per-unit power is Fig. 9. Rectifier maximum modulation index versus DC bus voltage level for
different input reactance values
expressed in (43). Subsequently, equation (42) can be written

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

6
2 6

4 4

2 2

is [A]

is [A]
1.5 0 0

-2 -2
2

-4 -4
K ,K

1 -6 -6
1

0.36 0.37 0.38 0.39 0.4 0.36 0.37 0.38 0.39 0.4
Time (s) Time (s)
(a) (b)
0.5 6

i [A]
0
0 0.1 0.2 0.3 0.4 0.5

s
-2
offsetr
-4
Fig. 10. K1 and K2 coefficient versus the rectifier offset, first method
-6
0.36 0.37 0.38 0.39 0.4
Time (s)
300
Cd1=2000uF, Cd2=2000uF, Cd3=2000uF (c)
Cd1=1500uF, Cd2=750uF, Cd3=1500uF (Proposed)
35
Cd1=1500uF, Cd2=1500uF, Cd3=1500uF
DC Link Voltage (V)

200 30

Mag (% of Fundamental)
220
C d1=1500uF, C d2=750uF, C d3=1500uF, (Proposed)
25
C d1=2000uF, C d2=2000uF, C d3=2000uF
DC Link Voltage (V)

C d1=1500uF, C d2=1500uF, C d3=1500uF

20
100 200

15
180
0.25 0.26 0.27 0.28 0.29 0.3
10
0 Time (s)
0 0.1 0.2 0.3 0.4 0.5
Time (s) 5
Fig. 11. DC link voltage ripple for different capacitor sizes
0
0 1
2
offset r  1 cos  rt  
1 I sm 2 3

4 5
V Cd 3  i Cd 3dt  6 7 8
Cd 3 2C d 3r  3  9 10
11
5 (d)
offset i  1 cos  i t    
I Lm
 (48) Fig. 12. The input current waveforms and its harmonic spectrum, (a)
2C d 3i  6  Cd1=Cd3=1500μF, Cd2=750μF (proposed capacitor sizing), (b)
 3  2  3  Cd1=Cd2=Cd3=1500μF, (c) Cd1=Cd2=Cd3=2000μF
 m r I sm sin    m i I Lm cos L  t V Cd 3 (0)
 d 3
4C  3  4C d 3  offset r  offset i
K2  (51)
where VCd1(0), VCd2(0), VCd3(0) are the initial (constant DC) 1  offset i
voltages across the capacitors, Ism and ILm are the grid and the This relationship is illustrated in Fig. 10 for the first
load current amplitudes, respectively, and ϕL is the load power method. For instance, considering the offsetr=0.5 and offseti=-
factor. 0.5, and choosing Cd1=Cd3=2Cd2, the total DC link voltage
The total DC link voltage ripple is given in (49) ripple would be eliminated.
V DC  V DC 1  V DC 2  V DC 3  Fig. 11 shows the measured waveforms of the DC link
 1  1 
voltages of the proposed converter for different capacitors
I sm 1 1 1 1  2 
    offset r      cos  r t   sizes. Simulation parameters are tabulated in Table X. offsetr
2r  Cd 1 Cd 2 Cd 3   3 
  C d 1 C d 2 C d3 
and offseti are 0.5 and -0.5, respectively. As the figure
I Lm  1 1 1  1 1 1   5  indicate, the cancellation of DC link voltage ripple is more
  cos  i t  6   
     offset i 
2i  Cd 1 Cd 2 Cd 3  C  C  C
  d 1 d 2 d3  effective when capacitor sizes are determined using (50) and
(49) (51), even compared to the case when even larger capacitors
are chosen.
From (49), the total DC link voltage ripple contains two Also notice the three-phase rectifier/input current waveform
frequency components with respect to the rectifier side and the along with its harmonic content spectrum in Fig. 12. The
inverter side fundamental frequencies. Provided that determination of the DC link capacitors as outlined in (50) and
Cd1=K1Cd2 and Cd3=K2Cd2 for eliminating the ripple in (49), (51) not only minimizes the total DC link voltage ripple but
the coefficients K1 and K2 should be chosen according to (50) also balances the three-phase current drawn from the grid and
and (51), respectively. decreases its total harmonic distortion. Nonetheless, the
effectiveness of this approach for sizing the DC link capacitors
offset r  offset i
K1  (50) is restricted by the underlying assumption of offsets offsetr and
1  offset r offseti being constant, as is the case in the first method of DF

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

TABLE VI current sensors for current measurement in closed-loop

SEMICONDUCTOR LOSS IN COUNTERPART THREE-PHASE AC/AC CONVERTERS
applications.
Switching Loss Conduction Loss Reliability. In order to precisely investigate the reliability of
fs
 EON  E OFF  E rr  6i acG  
6
V CE  i acG  i acL   the proposed converter and compare it with counterpart
 
B6-B2B converters, a theoretical method based on the most widely
 
Vi
6i acL 
3 2
RCE i acG  i acL
2
used standard MIL-HDBK-217F is utilized. Using this
VnIn 2
fs standard, reliability analysis of each system is performed by a
 EON  E OFF  E rr  4i acG   4
V CE  i acG  i acL  
B4-B2B   parameter called failure rate (λ). The failure rate of an item is
 
(Fig.1) V
4i acL  i 2
RCE i acG  i acL
2
an indication of the “proneness to failure” of the item after
VnIn
fs
time t has elapsed [21]. The total failure rate of each converter
 EON  E OFF  E rr  9i acU  
6
V CE  i acU  i acL   is the sum of the failure rate of its components.
NSC  
  total   i 1 i
(Fig.2) V n
6i acL  i
3 2
RCE i acU  i acL
2
(52)
VnIn 2
fs The major subsystems in the three-phase AC/AC systems
 EON  E OFF  E rr  6i acU   4
V CE  i acU  i acL  
SSC   are the switch modules, gate drivers that control the
 
(Fig.3) V
4i acL  i 2
RCE i acU  i acL
2
semiconductor switches and the energy-storage capacitors.
VnIn
Therefore, failure rates must be estimated for each of these
subsystems. The other items in fact have very little influence
operation described in Section III.A.1. Therefore, if dynamic on the total reliability. To estimate total failure rates for
offset values are used for maximizing the DC bus voltage various topologies, specifications for the components from
utilization as described in Section III.A.2, the DC link each of the major subsystems are used to estimate component
capacitors should be adequately large to yield acceptable failure rates. Then, part counts are used to aggregate these into
ripple levels for the full range of offset variations. failure rates for the entire subsystem. The calculations used to
estimate the failure rates for individual components are
D. Loss Calculation
detailed as follows.
The proposed converter loss profile including switching
losses and conduction losses is examined in Table VI. 1) Storage-Capacitor failure rate:
Moreover, a comparison is made in the same table between the The failure-rate model for capacitors prescribed by MIL-
counterpart converters. In Table VI, EON, EOFF, and Err are the HDBK-217F is
dissipated switching energies during switch turn-on, switch C  b CV Q  E (53)
turn-off, and diode turn-off. These values are measured at a where λb is the base failure rate, πCV is the capacitance factor,
given voltage Vn and current In and are included in the IGBT πQ is the quality factor, and C is the environment factor. The
datasheet. It is assumed that the conduction losses of the base failure rate λb for a capacitor with a maximum operating
diodes and the switches are identical. This implies that the temperature of 105 ◦C is
collector-emitter saturation voltage (VCE) of a switch is equal  s 3    T  273  
5

to the forward voltage of a diode, and their “on” resistance is b  0.00254    1 exp 5.09    (54)
 0.5     378  
also the same (RCE ). In table VI, the conduction and switching
losses in NSC and SSC are calculated in the worst condition where the stress factor S is the ratio of operating voltage to
when the input and output currents are 180 o out of phase with maximum rated voltage and T is the operating temperature in
equal frequencies. degree Celsius. The capacitance factor πCV is
 CV  0.34C 0.18 (55)
E. Comparison between Different Converters
where C is the rated capacitance in microfarads. Values for πQ
In this section, the results of the comparative evaluation of
and πE are tabulated in MIL-HDBK-217F for various quality
the B6-B2B, B4-B2B, NSC, and SSC based on device rating,
and environment specifications, respectively. Because the
number of elements, reliability and power loss are presented.
capacitors are not military spec, πQ =10, and also the ground,
To compare these four converters, the converter parameters
stationary and weather protected operating environment yields
are selected based on design parameters in Table VII.
πE =1.
Requirements of various systems are shown in Table VIII.
Appendix A discusses the design procedure in detail. Since the 2) IGBT Failure Rate:
NSC and SSC have two modes of operation, the rating of their The IGBT failure rate is calculated according to:
components is presented in each operating mode separately. IGBT  b T Q  E (56)
For comparing four converters in Table VIII, a safety factor where λb is the base failure rate which is 0.012, πT is the
between 40% and 50% for switches and a safety factor about temperature factor and πQ and πE are the quality and
25% for passive components are considered [20]. As it can be environment factors, respectively. For non-military spec
seen in Table VIII, in the proposed converter, the number of IGBTs, πQ =10, and for the same ground, stationary and
semiconductor switches, gate drives and hence cooling system weather protected operating environment πE is equal to 1.
is considerably less than conventional topologies. In addition, The temperature factor is computed from
the proposed converter requires the minimum number of

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

TABLE VII
DESIGN PARAMETERS
PG PFG PL PFL VLL-G VLL-L

4 kW 0.6 4 kW 0.6 300V 200 V

TABLE VIII
CONVERTER PARAMETERS FOR VARIOUS CONVERTERS
NSC SSC
B4-B2B Fig. 2 Fig. 3
B6-B2B
Fig. 1
EF DF EF DF

Rated DC Voltage
350 V 600 V 350 V 700 V 600 V 1200 V
(VDC)

Rated IGBT voltage 6*600V/27A 4*1200V/27A 6*600V/45A 6*1200V/45A 4*1200V/45A 4*1700V/45A

VCE,R/ current IC,R 6*600V/18A 4*1200V/18A 3*600V/27A 3*1200V/27A 2*1200V/27A 2*1700V/27A

Number of IGBT
12 8 9 9 6 6
Drivers
Number of Current
4 4 2 2 2 2
Sensors
2*1000uF/375V 2*1000uF/375V
Capacitors 1*450uF/450V 2*1000uF/375V 1*450uF/450V 1*450uF/900V
1*500uF/375V 1*500uF/750V

TABLE IX
IGBT SWITCHES SELECTED FOR VARIOUS CONVERTERS
NSC SSC
B4-B2B Fig. 2 Fig. 3
B6-B2B
Fig. 1
EF DF EF DF
6*IKW30N60T 4*IHW30N120R3 6*IKW50N60T 6*IRG7PH42UDPbF 4*IRG7PH42UDPbF 4*IXGH24N170
IGBT
Switches 2*IXGX
6*IKW20N60T 4*IHW20N120R5 3*IKW30N60T 3*IHW30N120R3 2*IHW30N120R3
32N170AH1

total failure
10.62 8.61 8.94 6.92 8.14 5.99
rate (λtotal)

Power loss. The four discussed topologies are also

  1 1 
compared in terms of their power losses. As mentioned
T  exp  1925    (57) previously, table VI shows the conduction and switching
  T j  273 298  
  losses of the different converters in the worst condition when
Tj is the junction temperature of IGBTs and depends on their the input and output currents are at the same frequency with
power dissipation and Z(th)JC in accordance with the relation 180o phase difference. Analytical calculation of losses under
Tj=25+ Z(th)JC× Pc. other conditions such as the design example given in table VII
is prohibitive; hence, loss analysis is conducted for different
3) Gate Driver Circuit Failure Rate:
converters using the simulation approach [22] to obtain power
MIL-HDBK-217F does not directly address gate driver
loss profile. The different converters/operation modes are
circuit failure rate. For purposes of this paper, according to
simulated with the same value of base power (SR) and system
[20], the authors elected to use the gate driver circuit failure
specification identical to those given in Table VII. Table IX
rate equal to half that of an equivalent power IGBT.
lists the choices of power switches for different topologies.
What has been discussed so far is now illustrated in an
In SSC and NSC, the analysis is carried out for two modes
example. The analysis is performed on a three-phase AC/AC
of operation, EF and DF modes. In EF mode, the rectifier and
system with the parameters listed in Table VII. As a
inverter reference signals are in phase and mmax=1. In DF
comparison, the difference in the required rating of passive
mode, the first method is applied and the modulation area is
and active components, DC bus voltage level, the number of
equally shared between the input and output terminals and
IGBT drivers and the number of current sensors of the four
hence mmax=0.5. The rated output power is delivered to the
discussed topologies is illustrated in Table VIII. Table IX
load at maximum modulation index. The converters are
displays the IGBT switches selected for each converter. The
operated with unity power factor, switching frequency is 10
calculated reliability of each converter can also be seen in
kHz and the input and output frequencies in DF mode are
Table IX in terms of total failure rate. As shown in the table,
respectively 60 Hz and 80 Hz, and in EF mode the input and
the proposed converter has the minimum total failure rate and
output frequencies are 60 Hz. Fig. 13 displays the
hence the highest reliability among the other topologies. This
semiconductor power losses in SSC in comparison with B6-
is because the proposed converter has the minimum number of
B2B, B4-B2B and NSC. Each figure indicates the total power
active switches and gate drivers.
loss (Ptot) and its individual components including the

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

P loss ( % o f S R)
4
Ptot PconT
3.5 PonT PoffT
3 PconD PoffD
2.5
2
1.5
1
0.5
0
0 0.2 0.4 0.6 0.8 1

(a) (b) (c)

(d) (e) (f)

Fig. 13. Semiconductor loss versus modulation index versus mi/mmax, (a) B6-B2B, (b) NSC, EF, (c) NSC, DF, (d) B4-B2B, (e) SSC-EF, (f) SSC-DF

conduction loss of IGBTs (PconT), conduction loss of diodes
(PconD), turn-off loss of IGBTs (PoffT), turn-on loss of
IGBTs (PonT) and reverse recovery loss of diodes (PoffD) as
a function of the output modulation index. In EF mode, as it
can be seen in the figure, owing to utilizing less number of
active switches and diodes, the proposed converter has lower
conduction loss compared with B6-B2B and NSC topologies.
The total power loss is also comparable with B6-B2B and B4-
B2B and is lower than NSC in this operating mode. In DF
mode, since the switching loss of the proposed converter is
higher than other converters, the total power loss increases.
This is because of the higher DC-link voltage compared with
other converters and the necessity to use IGBT switches with
higher ratings. The analysis of loss distribution in the switches
of the proposed converter, which has been carried out for NSC
in [23], is the subject of a future study.
V. SIMULATION RESULTS
To fully investigate the performance of the proposed
converter, the control scheme shown in Fig. 14 was conceived.
As can be seem in Fig. 14, the modulation indices v*ABr, v*BCr
and v*ABi, v*BCi enter the block labeled as ‘Fig. 5’. This block
refers to Fig. 5 in which the modulation indices v*ABr, v*BCr and
v*ABi, v*BCi are added up with the appropriate offset, i.e.
respectively offsetr and offseti. Accordingly, two resultant
modulation signals are obtained for each leg which will be
compared to a high frequency triangular carrier to generate the
switching gate signals according to the block diagram shown
in Fig. 5. The offset values in DF mode and EF mode are set
according to the limitation of modulation indices and the
discussed methods for elimination of DC component in each
mode of operation as summarized in Table III and Table IV.
The system demonstrated in Fig. 14 is simulated under
steady state as well as transient conditions. The simulation
parameters are described in Table X. The reference value of
the DC link voltage (V*DC) is determined by the required load
voltage and the rectifier side maximum modulation index
(mr(max)). Additionally, as described in (45), Ls influences
mr(max) and the THD of the input current. Therefore,
determination of the system parameters is an iterative process
based on a set of predefined initial criteria.
The current control in the synchronous frame of reference is
employed to control the proposed converter. The reference
signals of the inverter side and rectifier side are produced with
the active and reactive power exchanged between the load and
the grid by using a current regulator in the synchronous
reference frame. Assuming the utility AC voltage as reference,
the power equations in the synchronous frame can be derived
as follows:
3
PG  v dr i dr (58)
2
3
QG   v dr i qr (59)
2
3
PL  v di i di (60)
2

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

S4 S1
Power Grid
Li Cd1

S5 S2 Three-Phase Load
Cd2
VABC-grid iABC-grid

S6 S3
Cd3
iABC-Load VABC-Load

S1 S4 S2 S5 S3 S6
VABC-grid ƟL PLL/ VABC-Load
PLL Ɵs Fig. 5 VdL dq
* * * *
*
V DC V ABr VBCr VABi VBCi
+- PI PL*
idr* Phase Line Phase Line 2/3
VCd1+VCd2+VCd3 i i di*
dr Vdr* Vdi*
iABC-grid -+ PI * * PI -+
-1
VABC-rec VABC-inv -1 i ABC-Load
dq i dq dq Vqi* dq
qr Vqr*
-+ PI PI -+
Ɵs ƟL ƟL
Ɵs
iqr*=0 iqi*=0

Fig. 14. The control block diagram of the proposed six-switch AC/AC converter

3 The dynamics of the rectifier ac-side current are described

QG   v di i qi (61)
2 by the following space-phasor equation:
di
where PG and QG are the active and reactive powers supplied Ls  R s i  v r  v s (62)
by the grid, PL and QL are the active and reactive powers dt
consumed by the load, vdr and idr are the direct components of where Ls is the inductance of the rectifier side reactor, Rs is
the rectifier side voltage and current, vdi and idi are the direct resistance of the rectifier side reactor and v r is the rectifier
components of the inverter side voltage and current, and iqr terminal voltage of the proposed converter which can be
and iqi are the quadrature components of the rectifier side and controlled as
inverter side currents, respectively. According to (58)-(61), it 3
vr  V DC m r (63)
is possible to control the grid/load active and reactive powers 6
by controlling the corresponding direct and quadrature where m r represents the space-phasor corresponding to the
components of the rectifier/inverter currents.
PWM modulating signals which are normalized with respect
TABLE X to the peak value of the triangular carrier signal. Replacing
SIMULATION PARAMETRS
v r from (63) in (62), one deduces
Parameter Value
di 3
Cd1&Cd3 1500μF Ls  R s i  V DC m r  v s (64)
The six-switch dt 6
Cd2 750μF
converter The current-control system in dq reference frame is
DC link voltage (VDC) 200V designed based on (65) and (66).
Line to line voltage 35V di dr 3
Ls  R s i dr  Ls r i qr  V DC mdr  v ds (65)
The utility Frequency 50Hz dt 6
Series inductance (Ls) 4mH di qr 3
Ls  R s i qr  Ls r i dr  V DC mqr  v qs (66)
Resistance (RLoad) 5Ω dt 6
The load In order to decouple the dq reference frame equations and
inductance (LLoad) 6.3 mH
further simplify the system, mdr and mqr are determined based
Frequency 60 Hz on the following formulations:

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

Fig. 15. Steady state simulation results of the proposed converter in DF mode, first method, (a) DC link voltage [V], (b) grid voltage [V] and current of phase A
[A], (c) grid current [A], (d) rectifier side line voltage vABr [V], (e) rectifier side line voltage vBCr [V], (f) rectifier side line voltage vACr [V], (g) load current [A], (h)
inverter side line voltage vABi [V], (i) inverter side line voltage vBCi [V], (j) inverter side line voltage vCAi [V]

m dr 
6
3

u dr  Ls r i qr  v ds  (67)
m qr 
6
3

u qr  Ls r i dr  v qs  (68)
where udr is the output of the compensator that processes the
error between the reference current and the actual current in d-
axis (edr=i*dr-idr). In a same manner, uqr is the output of the
compensator that processes the error signal eqr=i*qr-iqr. The
compensator is designed as a PI controller, the proportional
and integral terms of which are determined as:
K p  Ls  i , K i  R s  i (69)
where τi is the time constant of the closed loop current control.
The time constant τi should be made small for a fast response,
but sufficiently large so as the bandwidth of the current
control loop is smaller than the switching frequency. Thus, τi
is chosen as ten times smaller than the switching time [24]. In
Fig. 14 two control loops are devised which in one of them,
the reference value of the quadrature component of the current
(i*q ) is obtained based on the reference reactive power; unity
power factor at the grid side yields i*qr = 0. In the other loop,
the direct component of the current (i*d ) is determined based
on the required active power; i*dr is obtained through the DC
link voltage control loop at the rectifier side, as the DC link
voltage level constitutes a direct relationship with the
transferred power.
Since the input and output frequencies are not identical, the
converter will operate in DF mode sharing the total
modulation index evenly between the rectifier side and the
inverter side. This necessitates adding two offsets of 0.5 and -
0.5 to the rectifier side and inverter side references,
respectively. As a result, the DC link voltage coefficients will
be equal to a=1/4, b =1/2, and c =1/4 according to Table III.
A. Steady State Performance of the Proposed System
To investigate the performance of the proposed system, its
steady state operation is presented first. Fig. 15 shows the
simulation results in the steady state. As illustrated in Fig.
15(a), the DC link voltage ripple is negligible and its level
follows the reference value. Furthermore, the voltages across
the DC link capacitors have settled to VCd1=(1/4)VDC,
VCd2=(1/2) VDC, and VCd3=(1/4) VDC without extra control
corresponding to the voltage coefficients mentioned before.
The reactive power supplied by the grid is equal to zero
(operation in unity power factor) which is deduced from Fig.
15(b), where the utility voltage and the input current are in
phase. Fig. 15(c) shows the three-phase input current drawn
from the grid. Low THD of 4.1% and sinusoidal waveforms

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

are successfully achieved using the developed algorithm. The

rectifier and inverter terminal voltages are provided in Figs.
15(d) to (f) and Figs. 15(h), to (j), respectively. Similar to B4-
B2B configuration, the line voltages of the proposed converter
terminals are different for the three phases. Presuming that the
DC-link capacitors are placed in leg C, vABx (x=r, i) has a
unipolar waveform of three levels (VDC, 0 and -VDC), whereas
vBCx and vCAx (x=r, i) are bipolar waveforms with two unequal
levels due to the unequal distribution of DC-link voltage
levels. Yet, the three-phase load current is balanced with
minimum harmonic content (Fig. 15(g)). Figs. 15 (c) and (g)
clearly show frequency independency of grid and load
currents.
B. Dynamic Performance of the Proposed Converter
To investigate the dynamic behavior of the proposed
converter, its transient response in no-load to full-load
transition is studied. In this case at t =0.3s, the converter
undergoes a no-load to full-load transition. The simulation
waveforms are displayed in Fig. 16. As illustrated in Fig.
16(a), when the load is connected to the converter, the DC link
voltage experiences a small drop for a limited period after
which it returns to its predesignated level. Furthermore, the
DC link capacitor voltages have again settled to VCd1=(1/4)
VDC, VCd2=(1/2) VDC, and VCd3=(1/4) VDC to produce balanced
inverter output voltages and rectifier input currents. Fig. 16. Transition from no-load to full-load simulation results in DF mode, first
method, (a) DC link voltage [V], (b) DC link capacitor voltages [V], (c) grid
The DC link capacitor voltages undergo marginal current [A], (d) load current [A]
fluctuations as can be seen in Fig. 16(b). The three-phase
current waveforms drawn from the grid and supplied to the
load are presented in Figs. 16 (c) and (d), respectively. The
PWM voltage waveforms are similar to those in Fig. 15 (d) to
(f) and Fig. 15(h) to (j) and are not repeated here. Fig. 16
verifies the desirable operation of the converter from no-load
to full-load conditions.

VI. EXPERIMENTAL RESULTS

To verify the validity of operation of the proposed system, a
prototype of the three-phase AC/AC converter of Fig. 14 is
built as shown in Fig. 17. The TMS320F2812 digital signal
controller is implemented to perform the control algorithm.
The load is a balanced three-phase RL network connected
directly to the inverter side terminals without any output filter.
The system performance is examined under steady state
conditions as well as during a transition from no-load to full-
load. In steady-state operation, the results are provided for
both DF and EF modes. However, for brevity, and because of
the similar nature of both modes, the transient condition is
discussed here only for DF mode. The system parameters
including the specifications of the source, the load and the
converter are the same as Table X.
A. Steady State Operation
1) DF Mode
In this case, the total DC bus voltage is shared between the
inverter and the rectifier by assigning equal maximum
modulation indexes. The rectifier and the inverter reference
offsets are 0.5 and -0.5, respectively and the load frequency is
Fig. 17. Prototype of the proposed system
equal to 60 Hz. The modulation index for the rectifier and the
inverter is 0.45. The experimental results demonstrating the
steady state performance of the converter in DF mode are
displayed in Fig. 18. As can be seen in Fig. 18(a), the total DC
link voltage has followed the reference value (200V) and the
voltage levels of the DC link capacitors have settled in
accordance with the offsets added to the rectifier and inverter
references. The line-to-line PWM voltages of the rectifier side
(vABr) and the inverter side (vABi) are shown in Figs. 18(b) and
(c), respectively. Fig. 18(d) shows that the utility voltage and
the input current are in phase indicating operation in unity
power factor. As expected, the three-phase input current has
low harmonic content and is balanced as shown in Fig. 18(e).
The load current is presented thereafter in Fig. 18(f). It should

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

index to reach one. The utility voltage and the input current
are in phase similar to those in Fig. 19 (d) and are not repeated
here.
B. Dynamic Behavior
Another test carried out on the experimental prototype
analyzes the dynamic response of the system when it
undergoes a no-load to full-load transition. The system
parameters are tabulated in Table X and the load frequency is
equal to 60Hz. Fig. 20 shows the results of this study. Notice
in Fig. 20(a) that although the DC link voltage experiences a
small drop for a short duration when the load is connected to
the inverter side terminals, the steady state voltage levels
remain constant at 200V, which agrees with the simulation
results. The rectifier input current shown in Fig. 20(b) is
sinusoidal with low harmonic distortion. The load current is
also provided in Fig. 20(c). The high frequency ripple content
of each phase current is distinctive because the voltage levels
of dc bus capacitors are different as seen by the R-L load. Yet,
as shown in the figure, the inverter is capable of providing
balanced three-phase currents with identical fundamental
values.
To avoid verbiage and because of the similar nature of DF
and EF modes, the transient conditions of the DF mode is only
included in the paper. Nonetheless simulation and

Fig. 18. Steady state experimental results, DF mode, first method (a) DC link
voltage and DC link capacitor voltages, (b) rectifier side terminal line voltage
(vABr), (c) inverter side terminal line voltage (vABi), (d) grid voltage and
current of phase A, (e) grid current, (f) load current

be noted that the frequency of the load current is different than

that of the utility current which confirms the frequency
independence of the load from the source.
2) EF Mode
Fig. 19 shows the experimental waveforms with the
converter operating in the EF mode when the second
method is used. The DC voltage is maintained at 100 V by the
rectifier and the converter modulation index is mr=mi=0.9. The
input and output frequencies are equal to 50 Hz. The other
parameters are similar in value to the parameters tabulated in
Table X. As can be seen in Fig. 19, the output currents are less
distorted since the higher modulation index can be achieved in Fig. 19. Steady state experimental results, EF mode, second method (a) DC
EF mode. In fact, the rectifier and inverter side frequencies are link voltage, (b) rectifier side terminal line voltage (vABr), (c) inverter side
equal in EF mode, thus allowing the maximum modulation terminal line voltage (vABi), (d) grid current, (e) load current

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

APPENDIX A-DEVICE RATING CALCULATION

The peak of input and output terminals of proposed six
switch-switch converter, IPK-U and IPK-L, can be calculated by
(A1) and (A2).
PG
I PK U  (A1)
3V LL G PFG
PL
I PK  L  (A2)
3V LL  L PFL

The peak currents of the proposed converter switches

The current peak of the upper and lower switches of
proposed converter, IPK-Upper and IPK-Lower, can be calculated by
(A3).
I PK  Lower  I PK Upper  I PK U  I PK  L (A3)
The current peak of the mid switches of proposed converter,
IPK-middle, can be calculated by (A4).
I PK  middle  max I PK U , I PK  L  (A4)
Recently in [20] a questionnaire survey was conducted with
a number of high-profile semiconductor manufacturers,
integrators, and users in the aerospace, automation, motor
drive, utility power, and other industry sectors. A key result
from this survey is safety factor for the voltage and current of
switches. The result indicates that the voltage and current
margins of switches had averages of 41% and 47%,
respectively. If we consider 50% safety factor, then the current
rating of the proposed converter switches would be
3
I rated  Lower  I rated Upper   I PK U  I PK L  (A5)
2
3
Fig. 20. Transition from no-load to full-load experimental results, (a) DC link I rated  middle  max I PK U , I PK  L  (A6)
voltage, and DC link capacitor voltages, (b) grid current, (c) load current. 2
Please note fsw = 2.4 kHz Considering the aforementioned equations, the current peak
experimental verification, which were carried out for EF mode of lower and upper switches and the current peak of mid
switches can be calculated by
also confirmed the similarity of responses between the two
modes. 3 PG PL 
I rated  Lower  I rated Upper     (A7)
2  3V LL G PFG 3V LL  L PFL 
VII. CONCLUSION  
3  PG PL 
A novel three-phase AC/AC converter with six IGBTs was I rated  middle  max  ,  (A8)
2 
 3V LL G PFG 3V LL  L PFL 

proposed in this paper which establishes a record low switch
count by reducing the number of semiconductor switches of DC link voltage and voltage peak of switches
the conventional three-phase AC/AC converters by half. The If the peak currents of the input and output terminals are the
use of the proposed converter in potential low and medium same, minimum power rating is obtained. To achieve this
power applications, such as non-isolated UPS systems, and in purpose, we have
high modulation indices such as in EF mode of operation, can m r PG PFL V LL G
translate into several benefits including reduction of the cost,   (A9)
m i PL PFG V LL  L
size, weight, and power losses of the system, and can enhance
where VLL-G and VLL-L are the line voltage amplitudes of
the reliability by reducing the number of drive circuits, and rectifier and inverter side terminals, respectively.
current sensors. Introducing the new topology; the modulation Furthermore, considering the applied method and working
schemes for its two defined operation modes were developed. either in DF or EF modes, the sum of rectifier and inverter
A comprehensive analysis was conducted on sizing the dc link modulation indices is different. Using the second method in
capacitors to determine the optimum sizing for minimum DF mode, we have
ripple. A comparative loss analysis provided an insight into mr  mi  1 (A10)
the loss profile of the proposed topology with respect to the Thus, the modulation indices should be selected as (A11)
alternative configurations. The effective operation of the and (A12)
proposed converter was demonstrated by simulation and PG PFL
confirmed through experimental implementation. mr  (A11)
PG PFL  PL PFG

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

PL PFG i Bs  I sm sin r t  2 3 (B9)

mi  (A12)
PG PFL  PL PFG i Cs  I sm sin r t  2 3 (B10)
Using (A10) in DF mode, we have
where Ism is the input current amplitude.
1 1 1
m rV DC  m iV DC  V DC (A13) Assuming the output load to be inductive, the output
2 2 2 currents will be as
1
V LL G V LL  L  V DC (A14) i Ao  I Lm sin i t   6  L  (B11)
2
i Bo  I Lm sin i t   2  L  (B12)
By replacing (A9) in (A14), we have
PG PFL  PL PFG i Co  I Lm sin i t  5 6  L  (B13)
V DC  2V LL G (A15)
PG PFL where ILm and ϕL are, respectively, the load current amplitude
PG PFL  PL PFG and the phase difference between the load voltage and the load
V DC  2V LL  L (A16)
PL PFG current in each phase.
Considering these two equations, DC-link voltage can be Thus, the DC link capacitor currents can be calculated as
expressed as (A17) (B14) to (B16).
1

 P PF  PL PFG P PF  PL PFG 
 iC 1   1  offset r  I sm sin r t  2 3
V DC  max 2V LL G G L , 2V LL  L G L  2

 P PF P PF 
 1
G L L G
 1  offset i  I Lm sin i t  5 6  L  (B14)
(A17) 2
3 3
According to (A17) and by applying 50% safety factor, the  m r I sm sin   2 3  m i I Lm cos L
voltage rating of the proposed converter switches in DF and 4 4
1
EF mode are given by (A18) and (A19), respectively. i C 2   offset r  1 I sm sin r t  2 3
2
3 
 P PF  PL PFG P PF  PL PFG 

V rated  DF   max 2V LL G G L , 2V LL  L G L   1
    1  offset i  I Lm sin i t  5 6  L  (B15)
2  PG PFL PL PFG  2
(A18) 3 3
 m r I sm sin   2 3  m i I Lm cos L
3 
 P PF  PL PFG P PF  PL PFG 
 4 4
V rated  EF   max V LL G G L ,V LL  L G L  
  
1
i C 3   offset r  1 I sm sin r t  2 3
2  PG PFL PL PFG 
2
(A19) 1
Following the same procedure for nine switch converter,  offset i  1 I Lm sin i t  5 6  L  (B16)
2
B6-B2B converter and B4-B2B converter, the device rating 3 3
can be calculated which are tabulated in Table V.  m r I sm sin   2 3  m i I Lm cos L
4 4
In the case of power balance between the input and the
APPENDIX B-CALCULATION OF DC LINK CAPACITOR output sides, the DC term of capacitor currents have to be zero
CURRENTS
3 3
It is possible to calculate three capacitor-currents as a m r I sm sin   2 3  m i I Lm cos L  0
4 4 (B17)
function of the input and output currents.  m r I sm sin   2 3  m i I Lm cos L
i C 1  d 11i As  d 12  i Ao   d 44i Bs  d 45  i Bo  (B1)
Finally, calculating the integral of the capacitor currents,
iC 2  iC 1  iCs (B2) their voltages can be obtained.
iC 3  iC 2  iCo (B3)
where ixs (x =A, B, C) is the input currents, ixo is the output REFERENCES
currents, dij (i, j = 1, 2, . . . ,6 and i=j) is the duty cycle of Si
and Sj switches and dii (i= 1, 2, . . . ,6 ) is the duty cycle of the [1] F. Gao, L. Zhang, D. Li, P. C. Loh, Y. Tang and H. Gao, “Optimal pulse
width modulation of nine-switch converter,” IEEE Trans. on Power
Si switch.
Electronics, Vol. 25, No. 9, pp. 2331, 2343, 2010.
The duty cycles in (B1) can be expressed as [2] Gi-Taek Kim, T.A.Lipo, “VSI-PWM rectifier/inverter system with a
d 11 
1
2
 1  v Ar
*
 (B4)
reduced switch count,” IEEE Trans. On Industry Applications, Vol
32, pp.1331 – 1337, 1996.
[3] J. Wu, H. Jou, Y. Feng, W. Hsu, M. Huang, and W. Hou, “Novel circuit
d 12 
1
2
1  v  *
Ai (B5) topology for three-phase active power filter”, IEEE Trans. on Power
Delivery, Vol. 22, no. 1, pp.444-449, 2007.
[4] J. Wu,“Novel Circuit Configuration for Compenasting for Reactive
d 44 
1
2

1  v Br
*
 (B6) Power of Induction Generator”, IEEE Trans. On Energy Conversion,
Vol. 23, no. 1, pp.152-162, 2008.
B. K. Lee, T. H. Kim, M. Ehsani, “On the Feasibility of Four-Switch
1  v 
1 [5]
d 45  *
Bi (B7) Three-Phase BLDC Motor Drives for Low Cost Commercial
2 Applications: Topology and Control”, IEEE Trans. on Power
Let the input currents be sinusoidal and in phase with grid Electronics, vol. 18, no. 1, pp. 164-172, 2003.
phase voltage as [6] R.L.A.Ribeiro, C.B.Jacobina, E.R.C.da Silva, A.M.N.Lima, “AC/AC
converter with four switch three phase structures,” Power Electronics
i As  I sm sin r t  (B8) Specialists Conference, PESC '96, Vol 1, pp.134 - 139, 1996.

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2017.2720722, IEEE Journal
of Emerging and Selected Topics in Power Electronics

[7] C. B. Jacobina, E. R. C. Silva, M. B. R. Corra, and A. M. Lima, “AC with the Faculty of Electrical and Computer Engineering,
motor drive systems with a reduced-switch-count converter,” IEEE
Qom University of Technology (QUT), Qom, Iran. His
Trans. on Industry Applications, vol. 39, pp. 1333–1342, 2003.
[8] D. C. Lee and Y. S. Kim, “Control of single-phase-to-three-phase research interests include power electronics, renewable energy
AC/DC/AC,” IEEE Trans. on Aerospace and Electronic Systems, vol. systems, and motor drives.
54, no. 2, pp. 797–804, 2007.
[9] L. Congwei, W. Bin, N. R. Zargari, and X. Dewei, “A novel three-phase
three-leg AC/AC converter using nine IGBTs,” IEEE Trans. on Power
Electronics, Vol. 24, no. 5, pp. 1151–1160, 2009. Alireza Fatemi (S’10-M’16) received the
[10] X. Liu, P. Wang, P. C. Loh and F. Blaabjerg, “A compact three-phase A.S. degree from Birjand University,
single-input/dual-output matrix converter,” IEEE Trans. On industrial Birjand, Iran, in 2006, the B.S. degree
Electronics, Vol. 59, No. 1, pp. 6-16, 2012.
from Shiraz University of Technology,
[11] X. Liu, P. c. Loh, P. Wang and F. Blaabjerg, “A direct power conversion
topology for grid integration of hybrid AC/DC energy resources,” IEEE Shiraz, Iran, in 2008, the M.S. degree
Trans. On Industrial Electronics, Vol, 60, No. 12, pp. 5696-5707, 2013. from Tarbiat Modares University, Tehran,
[12] H. Keyhani and H. Toliyat, “Isolated ZVS high-frequency-link AC-AC Iran, in 2011, and the Ph.D. degree from
converter with a reduced switch count,” IEEE Trans. On Power
Marquette University, Milwaukee, WI,
Electronics, Vol. 29, No. 8, pp. 4156-4166, 2014.
[13] C. B. Jacobina, N. Rocha, N. S. Rocha, N. S. De Moraes Lima Marinus USA, in 2016, all in electrical engineering and with first-class
and E. C. dos Santos Junior, “Single-phase to three-phase DC-link honors.
converters with reduced controlled switch count,” IEEE Trans. On Since 2015, he has been a Researcher with the Propulsion
Industry Applications, Vol. 50, No. 2, pp.1150-1160, 2014.
Systems Research Labs, GM Global Research and
[14] L. de Macedo Barros, C. B. Jacobina, A. C. Oliveria, I. S. de Freitas and
E. R. C. da Silva, “Three-phase-to-three-phase AC/AC DC-link five-leg Development, Pontiac, MI, USA. His research interests
converters based on three- and two-level legs,” IEEE Trans. On Industry include design and control of power electronics converters,
Applications, Vol. 51, No. 1, pp.521-530, 2015. performance optimization of electromechanical energy
[15] N. Rocha, A. C. de Oliveria, E. C. de Menezes, C. B. Jacobina, J. A.
conversion systems, and computational electromagnetics in
Alves Dias, “Single-phase-to-three-phase converters with two parallel
single-phase rectifiers and reduced switch count,” IEEE Trans. On machines and drives.
Power Electronics, Vol. 31, No. 5, pp.3704-3716, 2016.
[16] M. Heydari, A. Yazdian, M. Mohamadian and H. Zahedi, “A novel
variable-speed wind energy system using permanent-magnet
Ali Yazdian Varjani received his BSc.
synchronous generator and nine-switch AC/AC converter” 1st Power
Electronic & Drive System Technologies Conference (PEDSTC), from the Sharif University of Technology
Tehran, Iran, pp.5 – 9, 2010. in 1989 and his M.Eng. and PhD. in
[17] M. Heydari, A. Yazdian, M. Mohamadian and A. Fatemi, “A novel Electrical Engineering from the
reduced switch count single-phase to three-phase AC/AC converter,”
University of Wollongong, Australia, in
37th Annual Conference of IEEE Industrial Electronics Society
(IECON’11), Melbourne, Australia, 2011. 1995 and 1999 respectively.
[18] J. L. Hudgins, “Power Electronic Devices in the Future”, IEEE Journal Since 1999, he has been with Tarbiat
of Emerging and Selected Topics in Power Electronics, vol.1, no.1, pp. Modares University, Tehran, Iran, as an
11-17, Mar. 2013.
Assistant Professor in the Faculty of Electrical and Computer
[19] T. Kominami, and Y. Fujimoto, “A novel nine-switch inverter for
independent control of two three-phase loads,” IEEE Industry Engineering. His major research activities are in the areas of
Applications Society Annual Conference (IAS), pp. 2346-2350, 2007. digital signal processing applicable power systems and power
[20] S. Yang, A. Bryant, P. Mawby, X. Dawei, L. Ran, P. Tavner, “An electronics. His current academic interests include a variety of
industry-based survey of reliability in power electronic converters,”
research issues associated with “Information and
IEEE Trans. on Industry Applications, Vol. 47, pp.1441-1451, 2011.
[21] Y. Song and B. Wang, “Survey on Reliability of Power Electronic Communication Technology”, “Information Security” and
Systems”, IEEE Trans. on Power Electronics, Vol. 28, no. 1, 2013. “Power Electronics” related Topics.
[22] F. Blaabjerg, U. Jaeger, and S. Munk-Nielsen, “Power losses in PWM–
VSI inverter using NPT or PT IGBT devices,” IEEE Trans. Power
Electronics., vol. 10, no. 3, pp. 358–367, May 1995.
[23] Z. Qin, P. C. Loh, F. Blaabjerg, “Application Criteria for Nine-Switch
Power Conversion Systems with Improved Thermal Performance,”
IEEE Trans. On Power Electronics, Vol. 30, No. 8, pp.4608-4620, 2015.
[24] A. Yazdani and P. P. Dash, “A Control Methodology and
Characterization of Dynamics for a Photovoltaic (PV) System Interfaced
With a Distribution Network,” IEEE Trans. on Power Delivery, Vol. 24,
no. 3, pp.1538-1551, 2009.

Mojtaba Heydari (S’09–M’17) received

his undergraduate and graduate degrees
from Kashan University, Isfahan, Iran,
Iran University of Science and
Technology (IUST), Tehran, Iran and
Tarbiat Modares University, Tehran, Iran,
all in electrical engineering.
From 2012 to 2013, he was a Research
Scholar in the Power Electronics Laboratory, University of
California, Irvine (UCI), CA, USA. Since 2014, he has been

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.