Below is the Timing team interview questions:

1)Explain about your work done in past

2) How you finalize floorplan
3) How you solve timing issues
4) unix shell script: a) Find pnr_verilog in a log file and move all those lines
which contain that word in a separate file
b) pnr_verilog was part of long path of some file.
Replace all paths before pnr_verilog then move all lines to another file
c) Show me if statement example in shell and print
some value.

5) What are inputs for PT and timing paths

6) What are bottleneck analysis
7) Write structure of lib file and what it contains

 Explain PD flow which input and output at every stage of flow

 What is CTS and why we do it?
 What are the inputs to Primetime?
 What is setup and hold and what is the impact of +ve skew on setup and hold?

SET-1:

Answer to the interview questions:

1. Tell about Recent Project

Sol:

2. Challenges in Project
Sol: Design Dependent (Need some inputs)

3. Explain regarding special cells (Power switches, Isolation or clamp cells and Level Shifters)
Sol:
Power switches:Power switches has the potential to reduce overall power consumption substantially
because it lowers leakage power as well as switching power.
Isolation cells:In a design with power switching, an isolation cell is required where each logic signal
crosses from a power domain that can be powered down to a domain that is not powered down. The cell
operates as a buffer when the input and output sides of the cell are both powered up, but provides a
constant output signal during times that the input side is powered down.
Level Shifters: In a multi voltage design, a level shifter is required where each signal crosses from one
power domain to another. The level shifter operates as a buffer with one supply voltage at the input and a
different supply voltage at the output. Thus, a level shifter converts a logic signal from one voltage swing to
another, with a goal of having the smallest possible delay from input to output.
Retention Registers: In a design with power switching, there are several different ways to save register
states before power-down and restore them upon power-up in the power-down domain. One method is to
use retention registers, which are registers that can maintain their state during power-down by means of a
low-leakage register network and an always-on power supply.
Always-on Logic cells: When dealing with shutdown domains, there can be some situations in which certain
cells in the shutdown portion need to continuously stay active, such as for implementing retention registers,
isolation cells, retention control paths, and isolation enable paths. For example, if a save signal or restore
signal passing through a shutdown voltage area needs buffering, an always-on buffer cell must be used.
This type of logic is called always-on logic, which is built with always-on library cells.

4. Working on those special cells.

Sol: Locations of these special cells are decided in power network synthesis and power network analysis,
Further during placement these cells are instantiated from the library.

5. How many power domains and how are they inter linked each other?
Sol: There were 3 power domains. As per the power domain information given in UPF, they are inter linked
through special cells given in libraries.

6. Congestion and its solving kind of approach?

Sol: Congestion occurs at different stages,
a> Placement Stage: placement congestion: solution → Spreading the standard cells (avoid cell
clustering), In-Place-Optimization and addition of placement blockages .
b> Routing Stage: routing congestion: solution → Adding regular routing blockages on the memory
block, jogging, Area based routing optimizations.

7. What are End-cap and Tap Cells and there uses ?

Sol: End-caps and Tap cells are used to connect power and ground rails across an area and are also used to
ensure gaps do not occur between well or implant layers which could cause design rule violations.
Tap cells and End-caps are very technology dependent. Some technologies don't require them at all (or, the taps
are built in to the std cells), and for other technologies you may need a well tap every X microns, and endcaps at
the end of every std cell row as the end boundaries for the standard cells placement.

8. How many kinds of power switches used and there type of connection why?
Sol: Types/ kinds of power switch below,
a> fine-grain.
b> coarse-grain
→ Daisy chain
→ Ring Structure

9. How do you handle cross talk why it occurs ? explain problems associated with it?
Sol: Cross talk problem and fixing:
Problem: Transition on an aggressor net causes logic level glitch on victim net and its receiver.
Symptom: unintended logic transitions on receiver.
Result: Repeatable failures of certain logic operations. Dynamic logic fails. Static logic has timing
problems.
Fixing: by various proven techniques:
a> Buffer insertion
b> Driver upsizing
c> Increasing spacing between lines
d> Shielding

10. Why do you target for less latency number and skew number? need to explain according to project
Sol: Effects of less latency and skew:
a> we see considerably less setup and hold timing violations.
b> if skew is very tightly constrained large number of buffers/inverters get added in CTS.
c> if more latency, then OCV will impact timing.

11. What is min pulse width and explain its importance?

Sol: Minimum width of the clock required to accurately latch the data (D).Minimum pulse width violations
can affect setup and hold.

12. Do you tape-out the chip if there is more fan-out and if it has transition and capacitance limits are met?
Sol: How can there be Max fan-out if transition is met? → need elaboration on the exact issue.

13. What are kinds of derating factors used in your design?

Sol: Usually, we don't derate for setup check because it is already analyzed in ideal condition whereas for
hold check we use negative derating factor (scaling factor) for pessimistic analysis.
14. What is main difference between AOCV and OCV?
Sol:Difference is below,
OCV applies blanket margin across the chip for increasing variation due to process, voltage and
temperature and variation across the devices.
AOCV solution determines derating values as a function of logic depth and/or cell, and net
location. These two variables determining how much a specific path in a design is impacted by the
process variation.

15. What is meant by CPPR?

Sol:

16. How do you calculate depth and distance for AOCV derated Paths explain briefly only it?
Sol: We have not used AOCV.

17. what is setup and hold time and how do you handle it ?
Sol: Setup time:the amount of time the synchronous input (D) must be stable before the active edge of the
clock.
Hold time:the amount of time the synchronous input (D) must be stable after the active edge of the clock .
Setup time fixing:
1) reducing combinational logic delay by minimizing number of logic levels
2) splitting the combinational logic
3) Implementing Pipelining
4) Using double synchronizer using flip-flops
Hold time fixing:
1) Can be fixed by adding delays on input ports
2) adjusting clock speed.

SET-2:

Answer to the interview questions:

1. What are the issues u faced in 10nm ?

Sol: We have not worked on 10nm. (need inputs on the same)

2. How much clocks are there in your current block ?

Sol: In my design there was a single master clock and 5 generated clocks.

3. Explain the flow by each stage?

Sol: Flow below,
1.Data flow Preparations → creation of library and directory structure.
a> Technology files (.tf file)
b> LEF files (.lef file)
c> Timing Library files (.lib file)
d> SDC constraints (.sdc file)
e>Celview/FRAM constraints files (.celview file).
f> Table Look up (TLU+) files
g>Netlist file (.v)
h> UPF power constraints file (.upf file).
i> Pin information files (.io file)
2. Sanity checks → checking whether the given files and libraries contains unconnected ports,
instances, floating pins, missing information.
3. Design Planning → this has 2 stages:
a>Floorplan→ Die/Core Area, Aspect ratio, utilization and manual macro placement and
halos.
b>Powerplan→ Power ring, power stripes, power rails(VDD and VSS).
4. Placement → 2 steps : a> Global placement and b> In-Place-Optimization
5. CTS → 2 steps: a> pre-CTS loading clock spec file and checking clock spec file and b> post-
CTS building up the clock tree and global route.
6. Routing & PV → Detail Route – SI aware routing optimizations

4.How you will fix the die size and core size ?
Sol: core size = netlist area/estimated cell density.
Die size = core size + Pad height + Power ring.
Or (Die size = core size + 2*pad width + 2* spacing from core to pad)

5. Upto how much utilization u have reached ?

Sol: In one of the case, target was 75% and we achieved upto 73% after pnr.

6. How much corners you have in current project ?

Sol: In our design minimum corner used is 18 and maximum is 32.

7. How much setup corners and hold corners ?

Sol: In our design, Setup corner: 9, hold corners: 9

8. How you have met timing in each corners ?

Sol: Need inputs on the same (Because every corners has different solutions).

9. What are the different methods you have used in placement stage ?
Sol: We have used,
a> Global and
b> In-Place-Optimization.

10. Explain about aocv and pocv ?

Sol: AOCV: Advanced on-chip variation (AOCV) analysis reduces unnecessary pessimism by taking the
design methodology and fabrication process variation into account. AOCV determines derating factors
based on metrics of path logic depth and the physical distance traversed by a particular path. A
longer path that has more gates tends to have less total variation because the random variations from
gate to gate tend to cancel each other out. A path that spans a larger physical distance across the
chip tends to have larger systematic variations. AOCV is less pessimistic than a traditional OCV
analysis, which relies on constant derating factors that do not take path-specific metrics into account.
POCV: Is the next generation of variation analysis targeted at 14/16nm and below processes. It provides a
lightweight statistical margining approach to variation margining. It offers Graph-based
Analysis(GBA) pessimism reduction, improved PrimeTime ECO turnaround time, and simpler library
characterization than the Advanced OCV approach. Pocv provides:
a. Reduced pessimism gap between graph-based analysis and path-based analysis.
b. Less overhead for incremental timing analysis

11. Explain the critical issues you faced in one of the project to fix timing ?
Sol: Need inputs on the same (Because these issues are Design dependent)

12. Have you used useful skew techniques ?

Sol: No
But concept is similar to below:
When achieved skew is less than target skew then some paths can be deliberately delayed to solve setup
violations provided further paths have enough positive slack.

13. why we want to fix full chip timing ?

Sol: Any hold violations in the entire chip leads to chip failure, so we need to fix chip timing.

14. Why we have feed through paths (in to out)?

Sol: To decrease routing overheads at top-level (i.e at higher hierarchy).

15. What is skew and latency ?

Sol: Clock skew:clock skew is difference of clock signal arrival time between two flops.
If you have two flops which works on the same clock frequency but due to position in the chip they
are farther from each other, then there is a possibility is that u will see this problem.
Latency:Clock insertion delay is the estimated/realistic delay of reaching clocks from the PAD to each flop
after CTS. HOLD violations can be fixed by this. While doing CTS it inserts Clock buffers before the
flops if the clock path delay is more in the second flop, this is actually causing the insertion delay.

16. what is your maximum target skew ?

Sol: We usually decide maximum target skew depending on the target % of IR drop (Need some inputs)

17. How you used to balance the skew and insertion delay ?
Sol: Based on the design scenario, we generally follow Thumb rule “ lower the insertion delay better the
clock skew”,

18. If your skew is zero but you have more insertion delay what is the effect ?
Sol: If our skew is zero and have more latency then we need to work on latency because to avoid the effects
of OCV,clock jitter, which will be effecting the launch and capture path. “ But ideally we don't close design
with zero skew”.
(Insertion delay with respect to OCV has a large impact because the larger the insertion delay the greater the
impact on capture path and thus the greater the impact will be on your setup time. If your insertion delay
includes a large portion of common path, then CRPR will help reduce the impact of OCV)

19. Have you worked on low power techniques ?

Sol: Yes.

20. How much duration you used to take to close the block ?
Sol: Approximately 3 months for design > 200k gates.

SET-3:

Answer to the interview questions:

1. How you start PD once you get inputs and what are the checks ?
Sol: Once we get inputs,
a> Data flow Preparations → creation of library and directory structure.
a> Technology files (.tf file)
b> LEF files (.lef file)
c> Timing Library files (.lib file)
d> SDC constraints (.sdc file)
e>Celview/FRAM constraints files (.celview file).
f> Table Look up (TLU+) files
g>Netlist file (.v)
h> UPF power constraints file (.upf file).
i> Pin information files (.io file)
b> Sanity checks → checking
a> Loops in the design (like unconnected ports, floating pins, multi-ports).
b> missing libraries, io's, power files.
c> critical constraints in SDC missing.
d>Netlist missing.
e>Celview/FRAM view of macros missing in the hierarchy.
f> technology file missing.

2. How much micron blockage you put on memory and why ?

Sol: Depending on technology nodes, for the size of blockages(halos) we refer memory IP datasheet.

3. On what basis you come with that number (apart from congestion problem)
Sol: we refer IP Datasheet for the same (need some inputs on the same).

4. Why design ports are not placed in Metal1 and metal2?

Sol: Generally we will take Metal1 for std cell pin package and Metal2 is used for power rails. If we
use metal1 and metal2 as ports it may occur short between the nets while routing.

5. What is CRPR, OCV,POCV, how it affect your design with respect to setup and hold scenario?
Sol: OCV:On Chip Variations refers to the variations of delay properties between digital components and
interconnect in the same chip/die. OCV includes random and deterministic components of
variation. By random OCV component, we mean the variation in gate-oxide thickness, implant doses,
metal or dielectric thickness etc.
POCV:Is the next generation of variation analysis targeted at 14/16nm and below processes. It provides a
lightweight statistical margining approach to variation margining. It offers Graph-based
Analysis(GBA) pessimism reduction, improved PrimeTime ECO turnaround time, and simpler library
characterization than the Advanced OCV approach.
CRPR: When applying derating factors for launch and capture paths, OCV derates get applied to cells
which are common for both paths which is over pessimistic analysis.

“Hence through CRPR this extra pessimism is removed by applying the difference of OCV derates for setup
and hold on the clock re-convergence point”.

6. How you balance or fix the skew ?

Sol: By adding,
a> clock Buffers.
b> clock Inverters.
c> Optimum depth of clock tree.
d> Register stacking.
7. What type of cells to be used while fixing hold and how does these cell behave with different
scenario?
Sol: Usually we swap the LVT cells to HVT type of cells during CTS to fix hold violations, at high
voltage and nominal temperature hold is fixed and this may not help in closing hold at high
temperature scenario.

8. How you do power planning for different power domain?

Sol: The different power domains are partitioned into different voltage areas which are again defined
in a power constraint file known as UPF. In power planning stage we use this UPF for creating
different voltage areas in floorplan.

9. What are switch cells, when and why we use it?

Sol: Power switches has the potential to reduce overall power consumption substantially because it lowers
leakage power as well as switching power.
Power switches are used during PNS (Power network synthesis) to power-down and power-up.

10. What is cross talk ? how you fix it and how does it affect for hold corner?
Sol: Problem:Transition on an aggressor net causes logic level glitch on victim net and its receiver.
Symptom: unintended logic transitions on receiver.
Result: Repeatable failures of certain logic operations. Dynamic logic fails. Static logic has timing
problems.
Fixing: by various proven techniques:
a> Buffer insertion
b> Driver Upsizing
c> Increasing spacing between lines
d> Shielding
“Yes it affects the hold corner.”

11. What is NDR, what are the rules used, when and on which nets you apply?
Sol: NDR → Non Default Rule: Apart from vendor specified rules, NDR is user defined constraints.
There are different NDR rules at different stages:
a> CTS stage.
b> Routing stage.
“Usually we apply on the clock and critical nets”

3) How many PD projects have you done

4) When would you consider Placement stage as over? Criteria for that?
5) When would you consider CTS stage as over? Criteria for that?
6) What are the commands/settings used in ICC before placement is
done?
7) List in TcL
8) TcL syntax
9) PERL list, data structures: storing list of cells

We need to know what Behavioural questions are asked during Qualcomm Client
Interview, to help Engineers answer them better.

Have jotted down some of them, please add anymore to the list :
 1. Flexible with timings?
2. Can you stay back to complete tasks?
3. Need long term engagement with the company, will not quit in 6months
time?
4. To be ready to Work over the weekends?
5. Etc....

What if you have to stay as a buffer for long time?

2) Instances where you were able to share your knowledge with your friends/colleagues.
3) What if somebody is struck with his work and not able to go forward.
4) How well can you network with managers?
5) What if you were promised something and it's taking longer time?
6) How flexible are you working across varied tasks?
7) You have a colleague and a friend from another service company who are stuck with their work.
Who is your first priority?

We can't ask the 3rd question directly. Anybody will answer that he will be associated for long term.
I think its a process of finding out answer for that question.

what is power analysis ?

2) why we should do power analysis?
3)what is dynamic and static IR drop?
4) what happens if you don't fix?
5)what are the timing checks affected by power? and how ?
6)what are your block sizes?
7)how much is the run time taken for your blocks in redhwak tool?
8)what are the preliminary checks need to perform before you start fixing
dynamic IR?or grid robust checks?
9) where will be IR limit ?how to calculate? who will provide this?
10) how redhawk calculates resistance?
11)what are the inputs required for redhawk?
12)what STA file contains?
13)what is the difference between ploc and pad file?
14)how do you fix EM and IR ?
15)why we need to run static analysis?
16)you worked on vcd or vector less?
17) what is the IR limit in your project?

PD flow?
what is your block size? (expecting number)
how many macros in your block and explain placement of macros in your block.
Channel space calculation? why we need to maintain that?
about IO pins direction and IO pads?
what is a halo? why we need to addHalo to Macro?
suppose a std cell is sitting at the edge of macro ? what will happen and what type of care you take?
How will you give the inputs to start with floor plan?(command)
Tell me how you wrote the script for that?
Inputs for PD?
Explain about Sanity checks? commands?
what happens if netlist and lef doesn't matches? what type of warning/error it will encounter?
dbcommand to change the status of cell from placed to fixed
What does LEF contains? Type of LEFs?
how will you invoke the multiple LEFs? is there any order to go with?
how will you invoke if i give 10 netlists and how will u come to know that it is top level netlist?