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  • 01 131192 015 8146371931 09012021 100331pm

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    The objective of this lab was to implement and test the functioning of the B-register for the SAP-1 computer architecture. The B-register is a buffer register used in arithmetic operations that loads the word on the W bus into it when LB is low and the clock has a positive edge. It contains the data to be added or subtracted from the accumulator and produces a two-state output for the adder/subtracter using chips C20 and C21. The student was able to complete all tasks for the lab successfully.

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    01-131192-015-8146371931-09012021-100331pm

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    The objective of this lab was to implement and test the functioning of the B-register for the SAP-1 computer architecture. The B-register is a buffer register used in arithmetic operations that loads the word on the W bus into it when LB is low and the clock has a positive edge. It contains the data to be added or subtracted from the accumulator and produces a two-state output for the adder/subtracter using chips C20 and C21. The student was able to complete all tasks for the lab successfully.

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    © All Rights Reserved
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    3 views4 pages

    01 131192 015 8146371931 09012021 100331pm

    Uploaded by

    ahmedtasadduq6123
    The objective of this lab was to implement and test the functioning of the B-register for the SAP-1 computer architecture. The B-register is a buffer register used in arithmetic operations that loads the word on the W bus into it when LB is low and the clock has a positive edge. It contains the data to be added or subtracted from the accumulator and produces a two-state output for the adder/subtracter using chips C20 and C21. The student was able to complete all tasks for the lab successfully.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    of 4

    Computer Architecture &

    Organization Lab
    Lab # 9

    NAME: KAMRAN WAHAB

    ENROLLMENT NO.: 01-131192-015

    SUBMITTED TO: SIR AAMIR SOHAIL

    Department of Software Engineering


    Lab 09

    Buffer Register
    Objective:
    The objective of this lab is to implement and test the working of
    B-register for SAP-1 computer architecture.

    Tools Used:
    NI Multisim, MS Word

    Procedure:
    The B register is a buffer register. It is used in arithmetic operations. A low LB and a positive-
    clock edge load the word on the W bus into the B register. The two state output of the
    B-register drives the Adder/ Subtracter, supplying the number to be added or subtracted from the
    contents of the accumulator.

    Chips C20 and C21, which are 74LS173s, form the B-register. It contains the data to be added or
    subtracted from the accumulator. Grounding pins 1 and 2 of both chips produces a two-state
    output for the adder/subtracter.

    Circuit Diagram:
    Conclusion:
    I was able to perform all Lab tasks successfully.

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