Scribd
Upload
88 views8 pages

Gate Level Minimization Lab Rubrics

This document provides rubrics for evaluating a lab on gate level minimization of Boolean functions using K-maps. It lists several rubrics including: [1] use of engineering knowledge and following experiment procedures, [2] ability to record raw data, [3] following coding standards, [4] understanding tools, [5] individual work contributions, and [6] management of team work. It then provides a lab report on verifying the operation of multiplexers including objectives, theory, and in-lab tasks to implement 4x1 and 8x1 multiplexers using logic gates and integrated circuits. It concludes with a post-lab assignment to design a 16x1 multiplexer.

Uploaded by

Talha Tufail
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
88 views8 pages

Gate Level Minimization Lab Rubrics

This document provides rubrics for evaluating a lab on gate level minimization of Boolean functions using K-maps. It lists several rubrics including: [1] use of engineering knowledge and following experiment procedures, [2] ability to record raw data, [3] following coding standards, [4] understanding tools, [5] individual work contributions, and [6] management of team work. It then provides a lab report on verifying the operation of multiplexers including objectives, theory, and in-lab tasks to implement 4x1 and 8x1 multiplexers using logic gates and integrated circuits. It concludes with a post-lab assignment to design a 16x1 multiplexer.

Uploaded by

Talha Tufail
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Rubrics for CEC-141 DLD Lab

Lab #: 06
Lab Title: Gate Level Minimization of Boolean Function using K-Map
Submitted by: Muhammaad.Zain
Name Registration #
Muhammad.Zain Fa20-bce-015

Rubrics name & number Marks

In-Lab Post-Lab

Engineerin R2: Use of Engineering Knowledge and follow Experiment


g Procedures:
Knowledge Ability to follow experimental procedures, control variables, and
record procedural steps on lab report.
Problem R5: Data/Evidence Measurements:
Analysis Ability to record raw data / evidence.

Design R8: Best Coding Standards:


Ability to follow the coding standards and programming practices.

Modern R9: Understand Tools: Ability to describe and explain the


Tools principles behind and applicability of engineering tools.
Usage

Individual R12: Individual Work Contributions: Ability to carry out


and individual responsibilities.
Teamwork

R13: Management of Team Work:


Ability to appreciate, understand and work with multidisciplinary
team members.

Rubrics # R2 R5 R8 R9 R12 R13


In –Lab

Post- Lab
Lab Report # 6
Title: Verifying the Operation of Multiplexer

Objectives:
To understand the functioning of multiplexer circuits.

Designing and implementation of 4x1 Multiplexer using


logic gates Implementing 8x1 multiplexer using digital IC
74LS151

Theory:

A multiplexer is a device that has multiple inputs and one output. It also has
data select inputs, which permit digital data on any one of the inputs to be
switched to the output line. The multiplexer, shortened to “MUX” or “MPX”, is
a combinational logic circuit designed to switch one of several input lines
through to a single common output line by the application of a control signal.
Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to
the output. A diagram below shows the basic working of multiplexer.

The multiplexers are also known as data selectors because they can “select”
each input line, are constructed from individual Analogue Switches encased in
a single IC package as opposed to the “mechanical” type selectors such as
normal conventional switches and relays.

Generally, the selection of each input line in a multiplexer is controlled by an


additional set of inputs called control lines and according to the binary
condition of these control inputs, either “HIGH” or “LOW” the appropriate data
input is connected directly to the output. Normally, a multiplexer has an even
number of 2n data input lines and a number of “control” inputs that
correspond with the number of data inputs.

Note that multiplexers are different in operation to Encoders. Encoders are


able to switch an n-bit input pattern to multiple output lines that represent the
binary coded (BCD) output equivalent of the active input.

In Lab Task:

Implement 4x1 Mux in logic works/Proteus using


logic gates Implement 8x1 Mux using IC 74LS151

4x1 Multiplexer:

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0and
one output Y.

Truth table:

Select lines Output


S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Circuit diagram:

Proteus diagram:
8x1 Multiplexer:

The 74LS151 has eight data inputs (D0-D7) and therefore three data select
lines (S0-S2). Three bits are required to select any one of the data inputs. A
LOW on the Enable input allows the selected data input data to pass through
to the output. The pin diagram is shown below.

Circuit diagram:
IC diagram:
In-Lab diagram:
Post Lab Assignment:

Q1. Design a 16x1 multiplexer using IC 74LS151

IC diagram:

You might also like