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ES - MEL - AEL ZG554 - Lec4
ES - MEL - AEL ZG554 - Lec4
Possible solution:
– Add a flip‐flop to the output of LUT
FF FF FF
FF FF FF FF FF FF FF FF
y(7) y(6) y(5) y(4) y(3) y(2) y(1) y(0)
Actual Solution:
– Configurable Logic Blocks (CLBs)
3‐in, 1‐out
LUT
CLB
FF
2x1
2x1
FF FF FF FF
Cin(1)
2x1
FF FF FF FF
I=2N+2 (for N less than or equal to 16) is sufficient for good logic utilization.
The ‘Logic Utilization’ is defined as the average number of BLEs per logic block that a circuit is able to use
divided by the total number of BLEs per logic block, N.
Reconfigurable Interconnect
Problem 2: If FPGA doesn’t know which CLBs will be connected, where does
it put wires?
Solution:
– Put wires everywhere!
• Referred to as channel wires, routing channels, routing tracks,
many others
– CLBs typically arranged in a grid, with wires on all sides
Connection box
CLB CLB
Flexibility = 2 Flexibility = 3
Island style
• The island style is adopted by most FPGAs and there
are routing channels in the vertical and horizontal
directions among logic blocks.
• Connections between logic blocks and routing blocks
are generally a two‐point connection or a four‐point
connection,
• Also, with the uniform structure of the logic tiles, the
execution time of routing process can be reduced.
S witch boxe s
– S hort cha nne ls
• Us e ful for connecting a dja ce nt CLBs
– Long cha nne ls
• Us e ful for connecting CLBs tha t a re s e pa ra te d
• Allows for re duced routing dela y for non-adjace nt CLBs
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FPGAFabrics
BITS Pilani,
PilaBnITi SCPaim
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i, u
Pislani Campus
FPGA MemoryComponents
Existing FPGAs are 2‐dimensional arrays of CLBs, DSP, Block RAM, and
programmable interconnect
– Actual layout/placement differs for different FPGAs
I/O
– Virte x 7 has 1,200 pins
– Communication is s till ofte n a bottleneck
• Pins don’t incre a s e with ne w FPGAs , but logic doe s
– Tre nd: High-spe e d s e rial trans ce ivers
Clock re s ource s
– Us ing re configurable interconne ct for clock introduces timing
problems
• S ke w, jitte r
– FPGAs often provided clock tree s , both globa lly and loca lly
– e .g. Virte x 7
http://www.xilinx.com/s upport/docume nta tion/use r_guide s/ug472_7S
e ries _Clocking.pdf
BITS Pilani,
PilaBnITi SCPaim
lanp
i, u
Pislani Campus
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