FPGA Fabric

 Elements of an FPGA fabric

– Logic element
– Placement
– Wiring
– I/O
 Programming technologies
– Configuration
– Programming
– Reconfigurable
 FPGA questions

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Elements of an FPGA fabric

 Logic element IOB IOB IOB …

 Interconnect LE LE LE
 I/O pins interconnect
LE LE
… LE

LE LE LE

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Terminology
 Configuration
– bits that determine logic function + interconnect.
 CLB
– combinational logic block = logic element (LE).
 LUT
– Lookup table = SRAM used for truth table.
 I/O block (IOB)
– I/O pin + associated logic and electronics.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Logic element
 Programmable
– Input connections.
– Internal function.
 Coarser-grained than logic gates.
– Typically 4 inputs.
 Generally includes register.
 May provide specialized logic.
– Adder carry chain.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Example logic element

 Lookup table: a b out

0 0
0 1

a 0010 0 1 0 0
memory out
b 1001 1 0 1 0

1 1 0 1

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Placement

 Put each piece of logic in the array of logic

elements

LE LE LE

LE LE
… LE

LE LE LE

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Programmable wiring

 Organized into channels.

– Many wires per channel.
 Connections between wires
– Made at programmable interconnection points.
 Must choose
– Channels from source to destination.
– Wires within the channels.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Programmable interconnection
point

Register bit controls the interconnection

D Q

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Programmable wiring paths

Connect multiple segment paths

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR
 Choosing a path

LE

LE

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Routing problems

 Global routing:
– Which combination of channels?
 Local routing:
– Which wire in each channel?
 Routing metrics:
– Net length.
– Delay.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 I/O

 Fundamental selection
– input, output, three-state
 Additional features
– Register.
– Voltage levels.
– Slew rate.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Programming technologies

 SRAM.
– Can be programmed many times.
– Must be programmed at power-up.
 Antifuse.
– Programmed once.
 Flash.
– Similar to SRAM but using flash memory.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Configuration

 Must set control bits for:

– LE.
– Interconnect.
– I/O blocks.
 Usually configured off-line.
– Separate burn-in step (antifuse).
– At power-up (SRAM).

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Configuration vs. programming
 FPGA configuration:  CPU programming:
– Bits stay at the device – Instructions are fetched
they program. from a memory.
– A configuration bit – Instructions select
controls a switch or a complex operations.
logic bit.

add r1, r2 addIR

r1, r2
memory CPU

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Reconfiguration

 Some FPGAs are designed for fast

configuration.
– A few clock cycles, not thousands of clock
cycles.
 Allows hardware to be changed on-the-fly.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 FPGA fabric architecture
questions

 Given limited area budget:

– How many logic elements?
– How much interconnect?
– How many I/O blocks?

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Logic element questions
 How many inputs?
 How many functions?
– All functions of n inputs or eliminate some
combinations?
– What inputs go to what pieces of the function?
 Any specialized logic?
– Adder, etc.
 What register features?

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Interconnect questions

 How many wires in each channel?

 Uniform distribution of wiring?
 How should wires be segmented?
 How rich is interconnect between channels?
 How long is the average wire?
 How much buffering do we add to wires?

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 I/O block questions

 How many pins?

– Maximum number of pins determined by
package type.
 Are pins programmed individually or in
groups?
 Can all pins perform all functions?
 How many logic families do we support?

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR