Topics

 SRAM-based FPGA fabrics:

– Xilinx.
– Altera.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 SRAM-based FPGAs
 Program logic functions, interconnect using SRAM.
 Advantages:
– Re-programmable;
– dynamically reconfigurable;
– uses standard processes.
 Disadvantages:
– SRAM burns power.
– Possible to steal, disrupt configuration bits.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Logic elements

 Logic element includes combinational

function + register(s).
 Use SRAM as lookup table for
combinational function.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 LUT-based logic element
n
inputs

Lookup 1
table out
configuration
bits

Can multiplex at output or address at input

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR
 Example
111

1, 1, 1, 0,
0, 1, 1, 0,
1, 0,
1, 1
0 0 1

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Evaluation of SRAM-based LUT
 N-input LUT can handle function of 2n inputs.
 All logic functions take the same amount of space.
 All functions have the same delay.
 SRAM is larger than static gate equivalent of
function.
 Burns power at idle.
 Want to selectively add register to LE:

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Registers in logic elements

 Register may be selected into the circuit:

Configuration bit

LUT LE out
D Q

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Other LE features

 Multiple logic functions in an LE.

 Addition logic:
– carry chain.
 Partitioned lookup tables.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Xilinx Spartan-II CLB

 Each CLB has two identical slices.

 Slice has two logic cells:
– LUT.
– Carry logic.
– Registers.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II CLB details
 Each lookup table can be used as a 16-bit
synchronous RAM or 16-bit shift register.
 Arithmetic logic includes an XOR gate.
 Each slice includes a mux to combine the results
of the two function generators in the slice.
 Register can be configured as DFF or latch.
 Has three-state drivers (BUFTs) for on-chip
busses.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II CLB operation
 Arithmetic:
– Carry block includes XOR gate.
– Use LUT for carry, XOR for sum.
 Each slice uses F5 mux to combine results of
multiplexers.
 F6 mux combines outputs of F5 muxes.
 Registers can be FF/latch; clock and clock enable.
 Includes three-state output for on-chip bus.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Altera APEX II logic element

 Each logic array block has 10 logic

elements.
 Logic elements share some logic.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Apex II LE modes

 Modes of operation:
– Normal.
– Arithmetic.
– Counter.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 APEX-II LE normal mode

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 APEX-II LE arithmetic mode

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 APEX-II LE counter mode

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 APEX-II LE control logic

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Programmable interconnect
 MOS switch controlled by configuration bit:

D Q

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Programmable vs. fixed
interconnect

 Switch adds delay.

 Transistor off-state is worse in advanced
technologies.
 FPGA interconnect has extra length =
added capacitance.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Interconnect strategies
 Some wires will not be utilized.
 Congestion will not be same throughout
chip.
 Types of wires:
– Short wires: local LE connections.
– Global wires: long-distance, buffered
communication.
– Special wires: clocks, etc.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Paths in interconnect

 Connection may be long, complex:

LE LE LE LE LE

Wiring channel
Wiring channel
LE LE LE LE LE

LE LE LE LE LE

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Interconnect architecture

 Connections from wiring channels to LEs.

 Connections between wires in the wiring
channels. Wiring channel

LE LE

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Interconnect richness

 Within a channel:
– How many wires.
– Length of segments.
– Connections from LE to channel.
 Between channels:
– Number of connections between channels.
– Channel structure.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Segmented wiring

Length 1

Length 2

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Offset segments

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Switchbox

channel
channel channel
channel

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II interconnect

 Types of interconnect:
– local;
– general-purpose;
– dedicated;
– I/O pin.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II general-purpose
network

 Provides majority of routing resources:

– General routing matrix (GRM) connects
horizontal/vertical channels and CLBs.
– Interconnect between adjacent GRMs.
– Hex lines connect GRM to GRMs six blocks
away.
– 12 longlines span the chip.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II routing
 Relationship
between
GRM, hex
lines, and
local
interconnect:

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II three-state bus

 Horizontal on-chip busses:

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II clock distribution

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 APEX II interconnect

row
column

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II I/O

 Supports multiple I/O standards:

– LVTTL, PCI, LVCMOS2, AGP2X, etc.
 Provides registers.
 Programmable delay for pin-dependent hold
time.
 Programmable weak keeper circuit.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II I/O block diagram

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Configuration

 Need to set all configuration SRAM bits:

– minimum pin cost;
– reasonable speed.
 Configuration can also be read back for
testing.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Configuration ROM

 Configured on start-up from ROM:

Configuration
memory
FPGA

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Spartan-II configuration
 Configuration length depends on size of chip:
– 200,000 to 1.3 million bits.
 Configuration modes:
– Master serial for first chip in chain.
– Slave serial for follow-on chips.
– Slave parallel.
– Boundary-scan.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Scan chain

 Scan chain: shift register used to access

internal state.
 Logic-sensitive scan design (LSSD): scan
structure that uses some hardware for
normal mode and scan.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 JTAG boundary scan

 JTAG: Joint Test Action Group.

 Boundary scan:
– provide scan chain at pins;
– allow control of chip interior;
– decouple chip from rest of board for test.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Chip-on-board testing

 Boundary scan decouples chips:

board

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR

 Boundary scan concepts

 TAP: test access port.

– Requires three pins not shared with other logic.
– Test reset, test clock, test mode select, test data
in, test data out.
 TAP controller recognizes pins, controls
boundary scan registers.
 Instruction register defines boundary scan
mode.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR