HIGH EFFICIENCY BUCK DC-DC CONVERTER

USING AUTOMATIC PWM/PFM MODE CONTROL

BASED ON LOAD CURRENT VARIATION

Nguyen Minh Tan, Nguyen Van Tuan, Doan Minh Tien, Pham Xuan Thanh*
1
Faculty of Electronics Engineering, Ha Noi University of Industry
Email: thanhpx@haui.edu.vn

Abstract. This paper proposes a dual-mode buck DC-DC converter that operates
alternately between Pulse Width Modulation (PWM) and Pulse Frequency Con-
trol (PFM) modes, achieving high efficiency over a wide load range, making it-
suitable for applications in the Internet of Things (IoT) and biomedical technol-
ogy fields. The zero current detector (ZCD) technique is utilized for the purpose
ofto eliminatinge negative current when the inductor is in a discontinuous con-
duction mode (DCM) state. It simultaneouslyIt transitions the converter into
pulse frequency modulation (PFM) mode simultaneously to reduce power losses
under light load conditions. The converter utilizes current sensing to detect the
inductor current in continuous conduction mode (CCM) and switches operation
to PWM mode, achieving peak efficiency under high load currents. To ensure
precise and stable operation with fast response during operation this paper pro-
pose aes rail-to-rail comparator with wide bandwidth, combined with an efficient
soft-start technique. The converter is designed using 180 nm CMOS technology
and achieves a peak efficiency of 96% with VDD = 3.3 V (standard battery volt-
age) and VOUT staysranging aroundfrom 1.3 V. The load current advantageously
spans from 250 - 6.5 mA, with load values ranging from 5 - 200 Ω. The switching
frequency varies from 0.051.1 -– 1.10.05 MHz, and the time for output voltage
recovery between the two modes is 10 and 8 μs when transitioning from heavy
to light load and vice versa.
Keywords: DC-DC converter, soft start, on-chip capacitor, Pulse Width Modu-
lation, undershoot voltage.

1 Introduction

More and more power management integrated circuits (ICs), particularly buck DC-
DC converters are utilized in these devices to convert a battery supply into various
regulated voltages, are in great demands as crucial blocks in portable applications areas
battery-powered portable electronic devices improve [1-3]. High efficiency buck DC-
DC converters with a wide load current range are required to increase battery life [4].
As a result, the study of PWM, PFM dual-mode buck converters has long been a hot
topicspot [5-6]. Moreover, in PFM mode, the error amplifier is often switched off to
2

decrease power dissipation and hence improve efficiency. In high-load conditions, as

shown in Fig.1(a),
T=1/fSW T=1/fSW

VX VX

t t

IL
∆IL IOUT IL ∆IL
IOUT
0
t t
a) b)

Fig. 1. Inductor current of the DC-DC converter in CCM(a) and DCM(b) operations.

the converter operates in Continuous Conduction Mode (CCM) when theis inductor
current never reaches zero during the switching cycle and continuously charged and
discharged at a very high frequency. In contrast, at light-load conditions, as depicted in
Fig.1(b), the converter operates in Discontinuous Conduction Mode (DCM) using PFM
control, the inductor currnent periodically drops to zero before the starting start the next
cycle. In the load current ranging frome of the 6.5 to 250 mA mode, the load value is
restricted from 5 to 200 Ω withat an input voltage of 3.3 V, and and has an output
voltage at around ltage range of 1.3V. The circuit's conversion efficiency isof 96%, and
the output voltage recovery time when switching between the two modes is 10 and 8
us.

2 Structure of Buck DC DC Converter

Fig 2. depicts a buck DC-DC converter with PWM/PFM control and soft start. The
PWM modulator and PFM modulator are combined using MUX to control the buck
converter in either PWM or PFM mode. MUX is controlled by the V CTROL signal to
switch between the two modes, with logic '0' representing PWM mode and logic '1'
 3

OFF CHIP PWM

VCTROL VOUT VDD
VFB ON CHIP PFM
VH VP
VEA

OVERLAPPING
VREF_SS S1
L=4.7uH VOUT
VL DRIVER_P
VX
LIMITER VRAMP

CL=300nF
R1 ``

ERROR RL
AMPLIFIER VFB
COMPARATOR VN S2 R2 ``

DRIVER_N
CLK VP
CLK Q R QB

AND
DFF AND
D Q ZCD CURRENT
S
SENSING
VCTROL
VZCD VSEN
VFB VCTROL VSTART
MODE PWM/PFM
VTH_S
VREF_SS VREF VRAMP
VDD
SOFT VREF_SS RAMP
VSTART CLK 1 MHz BGR
COMPARATOR START VH
VL

Fig. 2. Structure buck DC DC converter using PWM/PFM.

representing PFM mode. The buck converter performs automatically switch modes
mode switching based on the signal VCTROL, which is set by a load current sensor. The
VCTROL is at has a state logic '0' when the load is light and '1' when the load becomes
heavy. Fig 3. shows PWM/PFM control block mode conversion block detects the out-
put current of the converter and switches between PWM and PFM modes as necessary
to optimize efficiency and performance. This helps to ensure that the converter operates
in the most efficient mode based on the load conditions. This block is responsible for
detecting the output current of the converter and includes detectors for PWM-to-PFM
and PFM-to-PWM modes. The switch frequency is 1MHz in PWM mode and 50KHz
in PFM mode. Fig 4. (a)
VDD VDD

``

VSS
VX VX VP
OUT

LEVEL
SHIFTER
VZCD
IN

VSEN VB4
VSS 250Ω
ZERO CURRENT VSS
DETECTION LEVEL SHIFTER CURRENT SENSING

VN XOR
`

VZCD R R R R
CLK Q NAND
`

CLK Q CLK Q CLK Q PWM\PFM

NAND
DFF DFF DFF DFF
VCTROL
D Q D Q D Q D Q
VSTART
PWM\PFM

VCTROL S Q S Q
VSEN `
Logic Logic
NAND
`

PFM\PWM
SR SR VCTROL
LEVEL AND R Q R Q
SHIFTER
VTH
VSTART

MODE PWM/PFM

Fig. 3. The architecture of mode control PWM/PFM.

4

shows the proposed rail to rail comparator this paper propose architecture comparator
rail to rail, the comparator is an essential component in a buck converter circuit. The
accuracy of the comparator affects the conversion efficiency of the circuit. The conven-
tional comparator consists of a PMOS or NMOS differential pair with low accuracy
and input range dependedent on the voltage threshold of the NMOS or PMOS. To im-
prove the accuracy and increase the bandwidth of the comparator, this paper proposes
a rail-to-rail comparator without a clock signal. Fig. 4. (b) shows this paper proposed
architecture bandgap reference architecture which using generates a stable voltage re-
gardless of temperature. The CMOS transistors MP8, MP9, MN6, MN7 have the same gate
voltage initially. As temperature rises, currents through the CMOS devices increases,
changing the gate voltage values. An increase in gate voltage results in an increase in
the resistance of MP8 and MP9, while decreasing the resistance of MN6 and MN7. Thus,
tThe gate voltage will thus vary according to the temperature fluctuation. At this point,
VH, VL, and VTH_S are maintained within a certain temperature range. The switching
time between the two modes must stay differentiatedrent by an 10 μs interval, denoted
as Tns showed Fig 5. (c). Because switching between the two modesthe two modes
switch at different load currents values helpsto prevent misinterpretation and maintain
the switching oepration countinuouslycontinuous mode switching. Additionally, the
circuit can compare at a frequency of less than 10MHz based on bandwidth fre-

VDD
VDD 1μ/ 1μ/
1μ/
0.7μ 0.7μ
0.7μ
MP5 MP6 MP7 m=4
VB1 4μ/ 0.25μ/
`` ``

0.25μ/
0.7μ 0.35μ 0.35μ
MP1 MP2 MP2 2μ/
1μ/ 1μ/ 1μ/
0.7μ 0.5μ
OUT 0.7μ
MP8 MP9 MP10 ``
MP11
0.7μ

VIN 0.5μ/ 0.5μ/ VIP 0.5μ/ 0.5μ/ VIN VH 1μ/

0.35μ 0.35μ 0.35μ 0.35μ 2μ/ 2μ/ 0.7μ
MP3 MP4 MN1 MN2 0.7μ 0.7μ 1μ/ MN9
MN6 MN7 0.7μ
OUT MN8 1μ/
0.7μ
VL
MN10
0.25μ/ 0.25μ/ 2μ/ VB4
``

2μ/ 2μ/ 2μ/

0.35μ 0.35μ 0.7μ 30μ/ 0.7μ
MN5 MN4 MN3
0.7μ
MN11 MN12
0.7μ 2μ/
0.5μ 0.7μ m=10 VTH
R= 2Ω

MN13 C6 MN15
C5 MN14 C7
60μ/
0.4pF 0.4pF 0.7μ 0.4pF
VSS VSS MN16 m=10

COMPARATOR
BANDGAP REFERENCE
RAIL TO RAIL
a) b)

Fig. 4. The architecture of Comparator rail to rail (a) and bandgap reference (b).

quency Fig 5. (a), giving a sine wave signal with a frequency of 10MHz, amplitude of
25mV to obtain an output signal in Fig 5. (b). AlsoInaddition, the comparison speed of
the circuit also depends on the current flowing through M P1 and MN3, the larger the
currnet the faster the comparison. The results show that over a temperature range from
-40 to 80°C, the voltage varies by a small amount as shows in Fig 5. (d). The power
consumption of the architecture bandgap reference and comparator are 12μW and
0.4μW, respectively.
 5

3dB

BANDWIDTH FIN=10MHZ
10MHZ Amp=25mV

a) b)

Tns

c) d)

Fig. 5. The simulation wareforms of bandwidth comparator (a), signal ouput comparator (b),
mode control mode PWM/PFM (c) and bandgap reference (d).

3 Results and discussion

This paper proposeds a design proposal offor a dual-mode PWM/PFM buck DC-
DC converter imple-mented in 180nm CMOS technology. The chip layout occupies a
compact area of 0.067 mm², as illustrated in Fig. 8. The converter operates in two dis-
tinct modes PWM and PFM based on load conditions, providing enhanced efficiency
with a peak performance of up to 96% as shows in Fig 7 (b). The simulation results of
varying loads variations in dual-mode PWM/PFM buck DC-DC converters are dis-
played shows in Fig. 6. The transition between PWM and PFM modes is controlled by
the VCTROL signal, with the load current IL switching from Continuous Conduction
Mode (CCM) corresponding to 5 Ω load and theto Discontinuous Conduction Mode
(DCM) corresponding to a 400 Ω load, as shown in Fig 6(a). Conversely, the transition
from PFM to PWM mode is controlled by the VCTROL signal in the opposite direction,
switching from PWM to PFM in shown Fig 6(b). It is noteworthy that in the PWM
mode, the converter is considered to be in a sleep state, and the output voltage is unsta-
ble when compared to the PWM mode where the chip operates withat high efficiency.
Fig 7. (a), it depicteds the variation in the output current IOUT and input current IOUT as
it transitions from a heavy-load mode to a light-load mode have IOUT decreases from
230mA to 3.5mA. By examining the input and output currents, we can calculate the
conversion efficiency of the Buck DC-DC converter allowing us to assess its opera-
tional effectiveness.
6

a) b)

Fig. 6. The simulation waveform model switching mode PWM-PFM and PFM-PFM.

PWM
PFM

a) b)

Fig. 7. The simulation current DC-DC buck converter(a) and efficiently model switching mode
PFM/PWM (b).

Fig. 8. The buck converter layout results.

Table 1. Performance summary and comparison.

Architecture [7] [8] [9] This work

Technology (µm) 0.4 0.18 0.35 0.18
Control Loop PWM PWM PWM/PFM PWM/PFM
 7

Frequency (MHz) 1 0.7 1/0.05

Input Volage (V) 5 3.3 3.6 3.3
Output Volage (V) 1.8 2.4 1.8 1.3
Max Load Current (A) 1 0.25 0.5 0.25
Peak Efficiency (%) 91 94 88 94
Overshoot voltage recovery time (µs) 27 12 28 10
Undershoot voltage recovery time(µs) 31 12 10 8

4 Conclusion

This paper presents a PWM/PFM control technique to improve the output load cur-
rent variation, combined with a soft-start technique for stable startup of the buck DC-
DC converter system, applied in handheld smart electronic devices and biomedical
technology. Switching between the two modes of PWM/PFM improves the conversion
efficiency over the load variation range. The load efficiency is significantly improved
when operating in PFM mode, which helps the converter consume less energy. Simu-
lation results demonstrate that the proposed PWM/PFM control technique can perform
automatic mode switching between PWM and PFM modes during the conversion pro-
cess combined with the soft-start block, the system achieves stable startup.

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