REPORT TITLE:

2021- 2022

Department: computer engineering

Student Name:
‫علي احمد عبد الزهره‬
Stage: Second
Study: Morning study
Class: C
Course Name: Second Course
Email:

College of Engineering
Mustansiriyah University
 comp Eng : ‫قسم الهندسة‬ ‫كلية الهندسة – الجامعة المستنصرية‬

C : ‫الشعبة‬ ‫الثانية‬ : ‫المرحلة‬ ‫علي احمد‬: ‫االسم‬

Experiment No. (10)

TRANSISTOR EMITTERBIASING

Objective:
the purpose of this experiment is to verify the voltages and currents in a base-
biased circuit as well as to construct its dc load line.

THEORY:
the voltages and cur- rents in a base-biased circuit as well as toconstruct
its dc load line.
stabilize a transistor's quiescent point. Consequently, the Q pointis affected
by a transistor's current gain (P).

Required Parts And Equipment:

1. resistors (1/4 W):
2. Two 1kΩ3. 4.7 kΩ
4. MO potentiometer
5. Two 2N3904 NPN silicon
6. transistors
 ‫‪comp Eng‬‬ ‫قسم الهندسة ‪:‬‬ ‫كلية الهندسة – الجامعة المستنصرية‬

‫‪C‬‬ ‫الشعبة ‪:‬‬ ‫الثانية‬ ‫المرحلة ‪:‬‬ ‫االسم ‪:‬علي احمد‬

‫‪Procedure:‬‬

‫‪Fig.10-A‬‬
 comp Eng : ‫قسم الهندسة‬ ‫كلية الهندسة – الجامعة المستنصرية‬

C : ‫الشعبة‬ ‫الثانية‬ : ‫المرحلة‬ ‫علي احمد‬: ‫االسم‬

Data for Experiment:

Transistor 1 Transistor 2
Parameter Measured Expected Measured Expected
Value Value Value Value
ICQ 0.007 A 0.007 A 0.007 A 0.007 A
IBQ 0.000036 A 0.000036A 0.000036 A 0.000036 A
βdc 195 195 195 195
VB 0.169 V 0.169 V 0.169 V 0.169 V
VC -7.01 V -7.01 V -7.01 V -7.01 V
VE -7.05 V -7.05 V -7.05 V -7.05 V
VCEQ 8.92 V 8.92 V 8.92 V 8.92 V

TAIBLE 10-A

Parameter Calculated Value

VCE(off) 7V
IC(sat) 0.0035 A
TAIBLE 9-2
 comp Eng : ‫قسم الهندسة‬ ‫كلية الهندسة – الجامعة المستنصرية‬

C : ‫الشعبة‬ ‫الثانية‬ : ‫المرحلة‬ ‫علي احمد‬: ‫االسم‬

Discussion:
1. For the circuit of Figure 10-1, if β = 100, then VC is:
(A) 6 V.
(B) 8 V.
(C) 10 V.
(D)15 V. (C)
2. If β of the transistor in the circuit of Figure 10-1 increases, then:
(A) IC decreases.
(B)VB decreases.
(C)VCE decreases.
(D)All of the above. (A)
3. If RB is made smaller in the circuit of Figure 10-1, then:
(A) IB decreases .
(B) (B)IC increases.
(C)VCE increases.
(D)All of the above. (D)
4. The collector saturation current for the circuit of Figure 10-1 is
approximately:
(A) 4 mA.
(B) 7.5 mA.
(C) 11.5 mA .
(D) 23 mA. (C)

5. At cutoff, the collector-to-emitter voltage for the circuit of Figure 10-1 is:
(A) 6 V.
(B) 8 V.
(C) 15 V.
(D) 23 V.
(D)